1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_i2c.h" 31 32 #include "atom.h" 33 #include "atom-bits.h" 34 #include "atombios_encoders.h" 35 #include "bif/bif_4_1_d.h" 36 37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, 38 ATOM_GPIO_I2C_ASSIGMENT *gpio, 39 u8 index) 40 { 41 42 } 43 44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 45 { 46 struct amdgpu_i2c_bus_rec i2c; 47 48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 49 50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); 51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); 52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); 53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); 54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); 55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); 56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); 57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); 58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 61 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 66 67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 68 i2c.hw_capable = true; 69 else 70 i2c.hw_capable = false; 71 72 if (gpio->sucI2cId.ucAccess == 0xa0) 73 i2c.mm_i2c = true; 74 else 75 i2c.mm_i2c = false; 76 77 i2c.i2c_id = gpio->sucI2cId.ucAccess; 78 79 if (i2c.mask_clk_reg) 80 i2c.valid = true; 81 else 82 i2c.valid = false; 83 84 return i2c; 85 } 86 87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, 88 uint8_t id) 89 { 90 struct atom_context *ctx = adev->mode_info.atom_context; 91 ATOM_GPIO_I2C_ASSIGMENT *gpio; 92 struct amdgpu_i2c_bus_rec i2c; 93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 94 struct _ATOM_GPIO_I2C_INFO *i2c_info; 95 uint16_t data_offset, size; 96 int i, num_indices; 97 98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 99 i2c.valid = false; 100 101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 103 104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 105 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 106 107 gpio = &i2c_info->asGPIO_Info[0]; 108 for (i = 0; i < num_indices; i++) { 109 110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 111 112 if (gpio->sucI2cId.ucAccess == id) { 113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 114 break; 115 } 116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 118 } 119 } 120 121 return i2c; 122 } 123 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) 125 { 126 struct atom_context *ctx = adev->mode_info.atom_context; 127 ATOM_GPIO_I2C_ASSIGMENT *gpio; 128 struct amdgpu_i2c_bus_rec i2c; 129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 130 struct _ATOM_GPIO_I2C_INFO *i2c_info; 131 uint16_t data_offset, size; 132 int i, num_indices; 133 char stmp[32]; 134 135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 137 138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 139 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 140 141 gpio = &i2c_info->asGPIO_Info[0]; 142 for (i = 0; i < num_indices; i++) { 143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 144 145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 146 147 if (i2c.valid) { 148 sprintf(stmp, "0x%x", i2c.i2c_id); 149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); 150 } 151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 153 } 154 } 155 } 156 157 struct amdgpu_gpio_rec 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, 159 u8 id) 160 { 161 struct atom_context *ctx = adev->mode_info.atom_context; 162 struct amdgpu_gpio_rec gpio; 163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 164 struct _ATOM_GPIO_PIN_LUT *gpio_info; 165 ATOM_GPIO_PIN_ASSIGNMENT *pin; 166 u16 data_offset, size; 167 int i, num_indices; 168 169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); 170 gpio.valid = false; 171 172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 174 175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 177 178 pin = gpio_info->asGPIO_Pin; 179 for (i = 0; i < num_indices; i++) { 180 if (id == pin->ucGPIO_ID) { 181 gpio.id = pin->ucGPIO_ID; 182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); 183 gpio.shift = pin->ucGpioPinBitShift; 184 gpio.mask = (1 << pin->ucGpioPinBitShift); 185 gpio.valid = true; 186 break; 187 } 188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 190 } 191 } 192 193 return gpio; 194 } 195 196 static struct amdgpu_hpd 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, 198 struct amdgpu_gpio_rec *gpio) 199 { 200 struct amdgpu_hpd hpd; 201 u32 reg; 202 203 memset(&hpd, 0, sizeof(struct amdgpu_hpd)); 204 205 reg = amdgpu_display_hpd_get_gpio_reg(adev); 206 207 hpd.gpio = *gpio; 208 if (gpio->reg == reg) { 209 switch(gpio->mask) { 210 case (1 << 0): 211 hpd.hpd = AMDGPU_HPD_1; 212 break; 213 case (1 << 8): 214 hpd.hpd = AMDGPU_HPD_2; 215 break; 216 case (1 << 16): 217 hpd.hpd = AMDGPU_HPD_3; 218 break; 219 case (1 << 24): 220 hpd.hpd = AMDGPU_HPD_4; 221 break; 222 case (1 << 26): 223 hpd.hpd = AMDGPU_HPD_5; 224 break; 225 case (1 << 28): 226 hpd.hpd = AMDGPU_HPD_6; 227 break; 228 default: 229 hpd.hpd = AMDGPU_HPD_NONE; 230 break; 231 } 232 } else 233 hpd.hpd = AMDGPU_HPD_NONE; 234 return hpd; 235 } 236 237 static const int object_connector_convert[] = { 238 DRM_MODE_CONNECTOR_Unknown, 239 DRM_MODE_CONNECTOR_DVII, 240 DRM_MODE_CONNECTOR_DVII, 241 DRM_MODE_CONNECTOR_DVID, 242 DRM_MODE_CONNECTOR_DVID, 243 DRM_MODE_CONNECTOR_VGA, 244 DRM_MODE_CONNECTOR_Composite, 245 DRM_MODE_CONNECTOR_SVIDEO, 246 DRM_MODE_CONNECTOR_Unknown, 247 DRM_MODE_CONNECTOR_Unknown, 248 DRM_MODE_CONNECTOR_9PinDIN, 249 DRM_MODE_CONNECTOR_Unknown, 250 DRM_MODE_CONNECTOR_HDMIA, 251 DRM_MODE_CONNECTOR_HDMIB, 252 DRM_MODE_CONNECTOR_LVDS, 253 DRM_MODE_CONNECTOR_9PinDIN, 254 DRM_MODE_CONNECTOR_Unknown, 255 DRM_MODE_CONNECTOR_Unknown, 256 DRM_MODE_CONNECTOR_Unknown, 257 DRM_MODE_CONNECTOR_DisplayPort, 258 DRM_MODE_CONNECTOR_eDP, 259 DRM_MODE_CONNECTOR_Unknown 260 }; 261 262 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev) 263 { 264 struct amdgpu_mode_info *mode_info = &adev->mode_info; 265 struct atom_context *ctx = mode_info->atom_context; 266 int index = GetIndexIntoMasterTable(DATA, Object_Header); 267 u16 size, data_offset; 268 u8 frev, crev; 269 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 270 ATOM_OBJECT_HEADER *obj_header; 271 272 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 273 return false; 274 275 if (crev < 2) 276 return false; 277 278 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 279 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 280 (ctx->bios + data_offset + 281 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 282 283 if (path_obj->ucNumOfDispPath) 284 return true; 285 else 286 return false; 287 } 288 289 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) 290 { 291 struct amdgpu_mode_info *mode_info = &adev->mode_info; 292 struct atom_context *ctx = mode_info->atom_context; 293 int index = GetIndexIntoMasterTable(DATA, Object_Header); 294 u16 size, data_offset; 295 u8 frev, crev; 296 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 297 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 298 ATOM_OBJECT_TABLE *router_obj; 299 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 300 ATOM_OBJECT_HEADER *obj_header; 301 int i, j, k, path_size, device_support; 302 int connector_type; 303 u16 conn_id, connector_object_id; 304 struct amdgpu_i2c_bus_rec ddc_bus; 305 struct amdgpu_router router; 306 struct amdgpu_gpio_rec gpio; 307 struct amdgpu_hpd hpd; 308 309 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 310 return false; 311 312 if (crev < 2) 313 return false; 314 315 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 316 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 317 (ctx->bios + data_offset + 318 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 319 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 320 (ctx->bios + data_offset + 321 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 322 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 323 (ctx->bios + data_offset + 324 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 325 router_obj = (ATOM_OBJECT_TABLE *) 326 (ctx->bios + data_offset + 327 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 328 device_support = le16_to_cpu(obj_header->usDeviceSupport); 329 330 path_size = 0; 331 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 332 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 333 ATOM_DISPLAY_OBJECT_PATH *path; 334 addr += path_size; 335 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 336 path_size += le16_to_cpu(path->usSize); 337 338 if (device_support & le16_to_cpu(path->usDeviceTag)) { 339 uint8_t con_obj_id, con_obj_num, con_obj_type; 340 341 con_obj_id = 342 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 343 >> OBJECT_ID_SHIFT; 344 con_obj_num = 345 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 346 >> ENUM_ID_SHIFT; 347 con_obj_type = 348 (le16_to_cpu(path->usConnObjectId) & 349 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 350 351 /* Skip TV/CV support */ 352 if ((le16_to_cpu(path->usDeviceTag) == 353 ATOM_DEVICE_TV1_SUPPORT) || 354 (le16_to_cpu(path->usDeviceTag) == 355 ATOM_DEVICE_CV_SUPPORT)) 356 continue; 357 358 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { 359 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", 360 con_obj_id, le16_to_cpu(path->usDeviceTag)); 361 continue; 362 } 363 364 connector_type = 365 object_connector_convert[con_obj_id]; 366 connector_object_id = con_obj_id; 367 368 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 369 continue; 370 371 router.ddc_valid = false; 372 router.cd_valid = false; 373 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 374 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 375 376 grph_obj_id = 377 (le16_to_cpu(path->usGraphicObjIds[j]) & 378 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 379 grph_obj_num = 380 (le16_to_cpu(path->usGraphicObjIds[j]) & 381 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 382 grph_obj_type = 383 (le16_to_cpu(path->usGraphicObjIds[j]) & 384 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 385 386 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 387 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 388 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 389 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 390 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 391 (ctx->bios + data_offset + 392 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 393 ATOM_ENCODER_CAP_RECORD *cap_record; 394 u16 caps = 0; 395 396 while (record->ucRecordSize > 0 && 397 record->ucRecordType > 0 && 398 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 399 switch (record->ucRecordType) { 400 case ATOM_ENCODER_CAP_RECORD_TYPE: 401 cap_record =(ATOM_ENCODER_CAP_RECORD *) 402 record; 403 caps = le16_to_cpu(cap_record->usEncoderCap); 404 break; 405 } 406 record = (ATOM_COMMON_RECORD_HEADER *) 407 ((char *)record + record->ucRecordSize); 408 } 409 amdgpu_display_add_encoder(adev, encoder_obj, 410 le16_to_cpu(path->usDeviceTag), 411 caps); 412 } 413 } 414 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 415 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 416 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 417 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 418 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 419 (ctx->bios + data_offset + 420 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 421 ATOM_I2C_RECORD *i2c_record; 422 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 423 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 424 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 425 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 426 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 427 (ctx->bios + data_offset + 428 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 429 u8 *num_dst_objs = (u8 *) 430 ((u8 *)router_src_dst_table + 1 + 431 (router_src_dst_table->ucNumberOfSrc * 2)); 432 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 433 int enum_id; 434 435 router.router_id = router_obj_id; 436 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 437 if (le16_to_cpu(path->usConnObjectId) == 438 le16_to_cpu(dst_objs[enum_id])) 439 break; 440 } 441 442 while (record->ucRecordSize > 0 && 443 record->ucRecordType > 0 && 444 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 445 switch (record->ucRecordType) { 446 case ATOM_I2C_RECORD_TYPE: 447 i2c_record = 448 (ATOM_I2C_RECORD *) 449 record; 450 i2c_config = 451 (ATOM_I2C_ID_CONFIG_ACCESS *) 452 &i2c_record->sucI2cId; 453 router.i2c_info = 454 amdgpu_atombios_lookup_i2c_gpio(adev, 455 i2c_config-> 456 ucAccess); 457 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 458 break; 459 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 460 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 461 record; 462 router.ddc_valid = true; 463 router.ddc_mux_type = ddc_path->ucMuxType; 464 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 465 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 466 break; 467 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 468 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 469 record; 470 router.cd_valid = true; 471 router.cd_mux_type = cd_path->ucMuxType; 472 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 473 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 474 break; 475 } 476 record = (ATOM_COMMON_RECORD_HEADER *) 477 ((char *)record + record->ucRecordSize); 478 } 479 } 480 } 481 } 482 } 483 484 /* look up gpio for ddc, hpd */ 485 ddc_bus.valid = false; 486 hpd.hpd = AMDGPU_HPD_NONE; 487 if ((le16_to_cpu(path->usDeviceTag) & 488 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 489 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 490 if (le16_to_cpu(path->usConnObjectId) == 491 le16_to_cpu(con_obj->asObjects[j]. 492 usObjectID)) { 493 ATOM_COMMON_RECORD_HEADER 494 *record = 495 (ATOM_COMMON_RECORD_HEADER 496 *) 497 (ctx->bios + data_offset + 498 le16_to_cpu(con_obj-> 499 asObjects[j]. 500 usRecordOffset)); 501 ATOM_I2C_RECORD *i2c_record; 502 ATOM_HPD_INT_RECORD *hpd_record; 503 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 504 505 while (record->ucRecordSize > 0 && 506 record->ucRecordType > 0 && 507 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 508 switch (record->ucRecordType) { 509 case ATOM_I2C_RECORD_TYPE: 510 i2c_record = 511 (ATOM_I2C_RECORD *) 512 record; 513 i2c_config = 514 (ATOM_I2C_ID_CONFIG_ACCESS *) 515 &i2c_record->sucI2cId; 516 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, 517 i2c_config-> 518 ucAccess); 519 break; 520 case ATOM_HPD_INT_RECORD_TYPE: 521 hpd_record = 522 (ATOM_HPD_INT_RECORD *) 523 record; 524 gpio = amdgpu_atombios_lookup_gpio(adev, 525 hpd_record->ucHPDIntGPIOID); 526 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); 527 hpd.plugged_state = hpd_record->ucPlugged_PinState; 528 break; 529 } 530 record = 531 (ATOM_COMMON_RECORD_HEADER 532 *) ((char *)record 533 + 534 record-> 535 ucRecordSize); 536 } 537 break; 538 } 539 } 540 } 541 542 /* needed for aux chan transactions */ 543 ddc_bus.hpd = hpd.hpd; 544 545 conn_id = le16_to_cpu(path->usConnObjectId); 546 547 amdgpu_display_add_connector(adev, 548 conn_id, 549 le16_to_cpu(path->usDeviceTag), 550 connector_type, &ddc_bus, 551 connector_object_id, 552 &hpd, 553 &router); 554 555 } 556 } 557 558 amdgpu_link_encoder_connector(adev->ddev); 559 560 return true; 561 } 562 563 union firmware_info { 564 ATOM_FIRMWARE_INFO info; 565 ATOM_FIRMWARE_INFO_V1_2 info_12; 566 ATOM_FIRMWARE_INFO_V1_3 info_13; 567 ATOM_FIRMWARE_INFO_V1_4 info_14; 568 ATOM_FIRMWARE_INFO_V2_1 info_21; 569 ATOM_FIRMWARE_INFO_V2_2 info_22; 570 }; 571 572 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 573 { 574 struct amdgpu_mode_info *mode_info = &adev->mode_info; 575 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 576 uint8_t frev, crev; 577 uint16_t data_offset; 578 int ret = -EINVAL; 579 580 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 581 &frev, &crev, &data_offset)) { 582 int i; 583 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; 584 struct amdgpu_pll *spll = &adev->clock.spll; 585 struct amdgpu_pll *mpll = &adev->clock.mpll; 586 union firmware_info *firmware_info = 587 (union firmware_info *)(mode_info->atom_context->bios + 588 data_offset); 589 /* pixel clocks */ 590 ppll->reference_freq = 591 le16_to_cpu(firmware_info->info.usReferenceClock); 592 ppll->reference_div = 0; 593 594 ppll->pll_out_min = 595 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 596 ppll->pll_out_max = 597 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 598 599 ppll->lcd_pll_out_min = 600 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 601 if (ppll->lcd_pll_out_min == 0) 602 ppll->lcd_pll_out_min = ppll->pll_out_min; 603 ppll->lcd_pll_out_max = 604 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 605 if (ppll->lcd_pll_out_max == 0) 606 ppll->lcd_pll_out_max = ppll->pll_out_max; 607 608 if (ppll->pll_out_min == 0) 609 ppll->pll_out_min = 64800; 610 611 ppll->pll_in_min = 612 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 613 ppll->pll_in_max = 614 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 615 616 ppll->min_post_div = 2; 617 ppll->max_post_div = 0x7f; 618 ppll->min_frac_feedback_div = 0; 619 ppll->max_frac_feedback_div = 9; 620 ppll->min_ref_div = 2; 621 ppll->max_ref_div = 0x3ff; 622 ppll->min_feedback_div = 4; 623 ppll->max_feedback_div = 0xfff; 624 ppll->best_vco = 0; 625 626 for (i = 1; i < AMDGPU_MAX_PPLL; i++) 627 adev->clock.ppll[i] = *ppll; 628 629 /* system clock */ 630 spll->reference_freq = 631 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 632 spll->reference_div = 0; 633 634 spll->pll_out_min = 635 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 636 spll->pll_out_max = 637 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 638 639 /* ??? */ 640 if (spll->pll_out_min == 0) 641 spll->pll_out_min = 64800; 642 643 spll->pll_in_min = 644 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 645 spll->pll_in_max = 646 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 647 648 spll->min_post_div = 1; 649 spll->max_post_div = 1; 650 spll->min_ref_div = 2; 651 spll->max_ref_div = 0xff; 652 spll->min_feedback_div = 4; 653 spll->max_feedback_div = 0xff; 654 spll->best_vco = 0; 655 656 /* memory clock */ 657 mpll->reference_freq = 658 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 659 mpll->reference_div = 0; 660 661 mpll->pll_out_min = 662 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 663 mpll->pll_out_max = 664 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 665 666 /* ??? */ 667 if (mpll->pll_out_min == 0) 668 mpll->pll_out_min = 64800; 669 670 mpll->pll_in_min = 671 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 672 mpll->pll_in_max = 673 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 674 675 adev->clock.default_sclk = 676 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 677 adev->clock.default_mclk = 678 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 679 680 mpll->min_post_div = 1; 681 mpll->max_post_div = 1; 682 mpll->min_ref_div = 2; 683 mpll->max_ref_div = 0xff; 684 mpll->min_feedback_div = 4; 685 mpll->max_feedback_div = 0xff; 686 mpll->best_vco = 0; 687 688 /* disp clock */ 689 adev->clock.default_dispclk = 690 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 691 /* set a reasonable default for DP */ 692 if (adev->clock.default_dispclk < 53900) { 693 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 694 adev->clock.default_dispclk / 100); 695 adev->clock.default_dispclk = 60000; 696 } 697 adev->clock.dp_extclk = 698 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 699 adev->clock.current_dispclk = adev->clock.default_dispclk; 700 701 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 702 if (adev->clock.max_pixel_clock == 0) 703 adev->clock.max_pixel_clock = 40000; 704 705 /* not technically a clock, but... */ 706 adev->mode_info.firmware_flags = 707 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 708 709 ret = 0; 710 } 711 712 adev->pm.current_sclk = adev->clock.default_sclk; 713 adev->pm.current_mclk = adev->clock.default_mclk; 714 715 return ret; 716 } 717 718 union gfx_info { 719 ATOM_GFX_INFO_V2_1 info; 720 }; 721 722 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) 723 { 724 struct amdgpu_mode_info *mode_info = &adev->mode_info; 725 int index = GetIndexIntoMasterTable(DATA, GFX_Info); 726 uint8_t frev, crev; 727 uint16_t data_offset; 728 int ret = -EINVAL; 729 730 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 731 &frev, &crev, &data_offset)) { 732 union gfx_info *gfx_info = (union gfx_info *) 733 (mode_info->atom_context->bios + data_offset); 734 735 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; 736 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; 737 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; 738 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; 739 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; 740 adev->gfx.config.max_texture_channel_caches = 741 gfx_info->info.max_texture_channel_caches; 742 743 ret = 0; 744 } 745 return ret; 746 } 747 748 union igp_info { 749 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 750 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 751 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 752 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 753 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 754 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; 755 }; 756 757 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, 758 struct amdgpu_atom_ss *ss, 759 int id) 760 { 761 struct amdgpu_mode_info *mode_info = &adev->mode_info; 762 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 763 u16 data_offset, size; 764 union igp_info *igp_info; 765 u8 frev, crev; 766 u16 percentage = 0, rate = 0; 767 768 /* get any igp specific overrides */ 769 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 770 &frev, &crev, &data_offset)) { 771 igp_info = (union igp_info *) 772 (mode_info->atom_context->bios + data_offset); 773 switch (crev) { 774 case 6: 775 switch (id) { 776 case ASIC_INTERNAL_SS_ON_TMDS: 777 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 778 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 779 break; 780 case ASIC_INTERNAL_SS_ON_HDMI: 781 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 782 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 783 break; 784 case ASIC_INTERNAL_SS_ON_LVDS: 785 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 786 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 787 break; 788 } 789 break; 790 case 7: 791 switch (id) { 792 case ASIC_INTERNAL_SS_ON_TMDS: 793 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 794 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 795 break; 796 case ASIC_INTERNAL_SS_ON_HDMI: 797 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 798 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 799 break; 800 case ASIC_INTERNAL_SS_ON_LVDS: 801 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 802 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 803 break; 804 } 805 break; 806 case 8: 807 switch (id) { 808 case ASIC_INTERNAL_SS_ON_TMDS: 809 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 810 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 811 break; 812 case ASIC_INTERNAL_SS_ON_HDMI: 813 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 814 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 815 break; 816 case ASIC_INTERNAL_SS_ON_LVDS: 817 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 818 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 819 break; 820 } 821 break; 822 case 9: 823 switch (id) { 824 case ASIC_INTERNAL_SS_ON_TMDS: 825 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); 826 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); 827 break; 828 case ASIC_INTERNAL_SS_ON_HDMI: 829 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); 830 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); 831 break; 832 case ASIC_INTERNAL_SS_ON_LVDS: 833 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); 834 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); 835 break; 836 } 837 break; 838 default: 839 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 840 break; 841 } 842 if (percentage) 843 ss->percentage = percentage; 844 if (rate) 845 ss->rate = rate; 846 } 847 } 848 849 union asic_ss_info { 850 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 851 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 852 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 853 }; 854 855 union asic_ss_assignment { 856 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 857 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 858 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 859 }; 860 861 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, 862 struct amdgpu_atom_ss *ss, 863 int id, u32 clock) 864 { 865 struct amdgpu_mode_info *mode_info = &adev->mode_info; 866 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 867 uint16_t data_offset, size; 868 union asic_ss_info *ss_info; 869 union asic_ss_assignment *ss_assign; 870 uint8_t frev, crev; 871 int i, num_indices; 872 873 if (id == ASIC_INTERNAL_MEMORY_SS) { 874 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 875 return false; 876 } 877 if (id == ASIC_INTERNAL_ENGINE_SS) { 878 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 879 return false; 880 } 881 882 memset(ss, 0, sizeof(struct amdgpu_atom_ss)); 883 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 884 &frev, &crev, &data_offset)) { 885 886 ss_info = 887 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 888 889 switch (frev) { 890 case 1: 891 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 892 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 893 894 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 895 for (i = 0; i < num_indices; i++) { 896 if ((ss_assign->v1.ucClockIndication == id) && 897 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 898 ss->percentage = 899 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 900 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 901 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 902 ss->percentage_divider = 100; 903 return true; 904 } 905 ss_assign = (union asic_ss_assignment *) 906 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 907 } 908 break; 909 case 2: 910 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 911 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 912 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 913 for (i = 0; i < num_indices; i++) { 914 if ((ss_assign->v2.ucClockIndication == id) && 915 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 916 ss->percentage = 917 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 918 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 919 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 920 ss->percentage_divider = 100; 921 if ((crev == 2) && 922 ((id == ASIC_INTERNAL_ENGINE_SS) || 923 (id == ASIC_INTERNAL_MEMORY_SS))) 924 ss->rate /= 100; 925 return true; 926 } 927 ss_assign = (union asic_ss_assignment *) 928 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 929 } 930 break; 931 case 3: 932 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 933 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 934 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 935 for (i = 0; i < num_indices; i++) { 936 if ((ss_assign->v3.ucClockIndication == id) && 937 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 938 ss->percentage = 939 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 940 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 941 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 942 if (ss_assign->v3.ucSpreadSpectrumMode & 943 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 944 ss->percentage_divider = 1000; 945 else 946 ss->percentage_divider = 100; 947 if ((id == ASIC_INTERNAL_ENGINE_SS) || 948 (id == ASIC_INTERNAL_MEMORY_SS)) 949 ss->rate /= 100; 950 if (adev->flags & AMD_IS_APU) 951 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 952 return true; 953 } 954 ss_assign = (union asic_ss_assignment *) 955 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 956 } 957 break; 958 default: 959 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 960 break; 961 } 962 963 } 964 return false; 965 } 966 967 union get_clock_dividers { 968 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 969 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 970 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 971 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 972 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 973 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 974 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 975 }; 976 977 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 978 u8 clock_type, 979 u32 clock, 980 bool strobe_mode, 981 struct atom_clock_dividers *dividers) 982 { 983 union get_clock_dividers args; 984 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 985 u8 frev, crev; 986 987 memset(&args, 0, sizeof(args)); 988 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 989 990 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 991 return -EINVAL; 992 993 switch (crev) { 994 case 2: 995 case 3: 996 case 5: 997 /* r6xx, r7xx, evergreen, ni, si. 998 * TODO: add support for asic_type <= CHIP_RV770*/ 999 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 1000 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1001 1002 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1003 1004 dividers->post_div = args.v3.ucPostDiv; 1005 dividers->enable_post_div = (args.v3.ucCntlFlag & 1006 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1007 dividers->enable_dithen = (args.v3.ucCntlFlag & 1008 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1009 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 1010 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 1011 dividers->ref_div = args.v3.ucRefDiv; 1012 dividers->vco_mode = (args.v3.ucCntlFlag & 1013 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1014 } else { 1015 /* for SI we use ComputeMemoryClockParam for memory plls */ 1016 if (adev->asic_type >= CHIP_TAHITI) 1017 return -EINVAL; 1018 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1019 if (strobe_mode) 1020 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 1021 1022 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1023 1024 dividers->post_div = args.v5.ucPostDiv; 1025 dividers->enable_post_div = (args.v5.ucCntlFlag & 1026 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1027 dividers->enable_dithen = (args.v5.ucCntlFlag & 1028 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1029 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 1030 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 1031 dividers->ref_div = args.v5.ucRefDiv; 1032 dividers->vco_mode = (args.v5.ucCntlFlag & 1033 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1034 } 1035 break; 1036 case 4: 1037 /* fusion */ 1038 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 1039 1040 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1041 1042 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 1043 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 1044 break; 1045 case 6: 1046 /* CI */ 1047 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 1048 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 1049 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 1050 1051 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1052 1053 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 1054 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 1055 dividers->ref_div = args.v6_out.ucPllRefDiv; 1056 dividers->post_div = args.v6_out.ucPllPostDiv; 1057 dividers->flags = args.v6_out.ucPllCntlFlag; 1058 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 1059 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 1060 break; 1061 default: 1062 return -EINVAL; 1063 } 1064 return 0; 1065 } 1066 1067 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, 1068 u32 clock, 1069 bool strobe_mode, 1070 struct atom_mpll_param *mpll_param) 1071 { 1072 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 1073 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 1074 u8 frev, crev; 1075 1076 memset(&args, 0, sizeof(args)); 1077 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 1078 1079 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1080 return -EINVAL; 1081 1082 switch (frev) { 1083 case 2: 1084 switch (crev) { 1085 case 1: 1086 /* SI */ 1087 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 1088 args.ucInputFlag = 0; 1089 if (strobe_mode) 1090 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 1091 1092 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1093 1094 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 1095 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 1096 mpll_param->post_div = args.ucPostDiv; 1097 mpll_param->dll_speed = args.ucDllSpeed; 1098 mpll_param->bwcntl = args.ucBWCntl; 1099 mpll_param->vco_mode = 1100 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 1101 mpll_param->yclk_sel = 1102 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 1103 mpll_param->qdr = 1104 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 1105 mpll_param->half_rate = 1106 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 1107 break; 1108 default: 1109 return -EINVAL; 1110 } 1111 break; 1112 default: 1113 return -EINVAL; 1114 } 1115 return 0; 1116 } 1117 1118 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) 1119 { 1120 GET_ENGINE_CLOCK_PS_ALLOCATION args; 1121 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 1122 1123 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1124 return le32_to_cpu(args.ulReturnEngineClock); 1125 } 1126 1127 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) 1128 { 1129 GET_MEMORY_CLOCK_PS_ALLOCATION args; 1130 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 1131 1132 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1133 return le32_to_cpu(args.ulReturnMemoryClock); 1134 } 1135 1136 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, 1137 uint32_t eng_clock) 1138 { 1139 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1140 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 1141 1142 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 1143 1144 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1145 } 1146 1147 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, 1148 uint32_t mem_clock) 1149 { 1150 SET_MEMORY_CLOCK_PS_ALLOCATION args; 1151 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 1152 1153 if (adev->flags & AMD_IS_APU) 1154 return; 1155 1156 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 1157 1158 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1159 } 1160 1161 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 1162 u32 eng_clock, u32 mem_clock) 1163 { 1164 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1165 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 1166 u32 tmp; 1167 1168 memset(&args, 0, sizeof(args)); 1169 1170 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 1171 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 1172 1173 args.ulTargetEngineClock = cpu_to_le32(tmp); 1174 if (mem_clock) 1175 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 1176 1177 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1178 } 1179 1180 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, 1181 u16 *vddc, u16 *vddci, u16 *mvdd) 1182 { 1183 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1184 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1185 u8 frev, crev; 1186 u16 data_offset; 1187 union firmware_info *firmware_info; 1188 1189 *vddc = 0; 1190 *vddci = 0; 1191 *mvdd = 0; 1192 1193 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 1194 &frev, &crev, &data_offset)) { 1195 firmware_info = 1196 (union firmware_info *)(mode_info->atom_context->bios + 1197 data_offset); 1198 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 1199 if ((frev == 2) && (crev >= 2)) { 1200 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 1201 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 1202 } 1203 } 1204 } 1205 1206 union set_voltage { 1207 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 1208 struct _SET_VOLTAGE_PARAMETERS v1; 1209 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 1210 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 1211 }; 1212 1213 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, 1214 u16 voltage_id, u16 *voltage) 1215 { 1216 union set_voltage args; 1217 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1218 u8 frev, crev; 1219 1220 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1221 return -EINVAL; 1222 1223 switch (crev) { 1224 case 1: 1225 return -EINVAL; 1226 case 2: 1227 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 1228 args.v2.ucVoltageMode = 0; 1229 args.v2.usVoltageLevel = 0; 1230 1231 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1232 1233 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 1234 break; 1235 case 3: 1236 args.v3.ucVoltageType = voltage_type; 1237 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 1238 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 1239 1240 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1241 1242 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 1243 break; 1244 default: 1245 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1246 return -EINVAL; 1247 } 1248 1249 return 0; 1250 } 1251 1252 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, 1253 u16 *voltage, 1254 u16 leakage_idx) 1255 { 1256 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 1257 } 1258 1259 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, 1260 u16 voltage_level, 1261 u8 voltage_type) 1262 { 1263 union set_voltage args; 1264 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1265 u8 frev, crev, volt_index = voltage_level; 1266 1267 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1268 return; 1269 1270 /* 0xff01 is a flag rather then an actual voltage */ 1271 if (voltage_level == 0xff01) 1272 return; 1273 1274 switch (crev) { 1275 case 1: 1276 args.v1.ucVoltageType = voltage_type; 1277 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 1278 args.v1.ucVoltageIndex = volt_index; 1279 break; 1280 case 2: 1281 args.v2.ucVoltageType = voltage_type; 1282 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 1283 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 1284 break; 1285 case 3: 1286 args.v3.ucVoltageType = voltage_type; 1287 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 1288 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 1289 break; 1290 default: 1291 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1292 return; 1293 } 1294 1295 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1296 } 1297 1298 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, 1299 u16 *leakage_id) 1300 { 1301 union set_voltage args; 1302 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1303 u8 frev, crev; 1304 1305 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1306 return -EINVAL; 1307 1308 switch (crev) { 1309 case 3: 1310 case 4: 1311 args.v3.ucVoltageType = 0; 1312 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 1313 args.v3.usVoltageLevel = 0; 1314 1315 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1316 1317 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 1318 break; 1319 default: 1320 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1321 return -EINVAL; 1322 } 1323 1324 return 0; 1325 } 1326 1327 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, 1328 u16 *vddc, u16 *vddci, 1329 u16 virtual_voltage_id, 1330 u16 vbios_voltage_id) 1331 { 1332 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 1333 u8 frev, crev; 1334 u16 data_offset, size; 1335 int i, j; 1336 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 1337 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 1338 1339 *vddc = 0; 1340 *vddci = 0; 1341 1342 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1343 &frev, &crev, &data_offset)) 1344 return -EINVAL; 1345 1346 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 1347 (adev->mode_info.atom_context->bios + data_offset); 1348 1349 switch (frev) { 1350 case 1: 1351 return -EINVAL; 1352 case 2: 1353 switch (crev) { 1354 case 1: 1355 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 1356 return -EINVAL; 1357 leakage_bin = (u16 *) 1358 (adev->mode_info.atom_context->bios + data_offset + 1359 le16_to_cpu(profile->usLeakageBinArrayOffset)); 1360 vddc_id_buf = (u16 *) 1361 (adev->mode_info.atom_context->bios + data_offset + 1362 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 1363 vddc_buf = (u16 *) 1364 (adev->mode_info.atom_context->bios + data_offset + 1365 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 1366 vddci_id_buf = (u16 *) 1367 (adev->mode_info.atom_context->bios + data_offset + 1368 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 1369 vddci_buf = (u16 *) 1370 (adev->mode_info.atom_context->bios + data_offset + 1371 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 1372 1373 if (profile->ucElbVDDC_Num > 0) { 1374 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 1375 if (vddc_id_buf[i] == virtual_voltage_id) { 1376 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1377 if (vbios_voltage_id <= leakage_bin[j]) { 1378 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 1379 break; 1380 } 1381 } 1382 break; 1383 } 1384 } 1385 } 1386 if (profile->ucElbVDDCI_Num > 0) { 1387 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 1388 if (vddci_id_buf[i] == virtual_voltage_id) { 1389 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1390 if (vbios_voltage_id <= leakage_bin[j]) { 1391 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 1392 break; 1393 } 1394 } 1395 break; 1396 } 1397 } 1398 } 1399 break; 1400 default: 1401 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1402 return -EINVAL; 1403 } 1404 break; 1405 default: 1406 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1407 return -EINVAL; 1408 } 1409 1410 return 0; 1411 } 1412 1413 union get_voltage_info { 1414 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 1415 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 1416 }; 1417 1418 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, 1419 u16 virtual_voltage_id, 1420 u16 *voltage) 1421 { 1422 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 1423 u32 entry_id; 1424 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 1425 union get_voltage_info args; 1426 1427 for (entry_id = 0; entry_id < count; entry_id++) { 1428 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 1429 virtual_voltage_id) 1430 break; 1431 } 1432 1433 if (entry_id >= count) 1434 return -EINVAL; 1435 1436 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 1437 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1438 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 1439 args.in.ulSCLKFreq = 1440 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 1441 1442 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1443 1444 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 1445 1446 return 0; 1447 } 1448 1449 union voltage_object_info { 1450 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 1451 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 1452 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 1453 }; 1454 1455 union voltage_object { 1456 struct _ATOM_VOLTAGE_OBJECT v1; 1457 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 1458 union _ATOM_VOLTAGE_OBJECT_V3 v3; 1459 }; 1460 1461 1462 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 1463 u8 voltage_type, u8 voltage_mode) 1464 { 1465 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 1466 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 1467 u8 *start = (u8*)v3; 1468 1469 while (offset < size) { 1470 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 1471 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 1472 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 1473 return vo; 1474 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 1475 } 1476 return NULL; 1477 } 1478 1479 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, 1480 u8 voltage_type, 1481 u8 *svd_gpio_id, u8 *svc_gpio_id) 1482 { 1483 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1484 u8 frev, crev; 1485 u16 data_offset, size; 1486 union voltage_object_info *voltage_info; 1487 union voltage_object *voltage_object = NULL; 1488 1489 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1490 &frev, &crev, &data_offset)) { 1491 voltage_info = (union voltage_object_info *) 1492 (adev->mode_info.atom_context->bios + data_offset); 1493 1494 switch (frev) { 1495 case 3: 1496 switch (crev) { 1497 case 1: 1498 voltage_object = (union voltage_object *) 1499 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1500 voltage_type, 1501 VOLTAGE_OBJ_SVID2); 1502 if (voltage_object) { 1503 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 1504 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 1505 } else { 1506 return -EINVAL; 1507 } 1508 break; 1509 default: 1510 DRM_ERROR("unknown voltage object table\n"); 1511 return -EINVAL; 1512 } 1513 break; 1514 default: 1515 DRM_ERROR("unknown voltage object table\n"); 1516 return -EINVAL; 1517 } 1518 1519 } 1520 return 0; 1521 } 1522 1523 bool 1524 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, 1525 u8 voltage_type, u8 voltage_mode) 1526 { 1527 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1528 u8 frev, crev; 1529 u16 data_offset, size; 1530 union voltage_object_info *voltage_info; 1531 1532 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1533 &frev, &crev, &data_offset)) { 1534 voltage_info = (union voltage_object_info *) 1535 (adev->mode_info.atom_context->bios + data_offset); 1536 1537 switch (frev) { 1538 case 3: 1539 switch (crev) { 1540 case 1: 1541 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1542 voltage_type, voltage_mode)) 1543 return true; 1544 break; 1545 default: 1546 DRM_ERROR("unknown voltage object table\n"); 1547 return false; 1548 } 1549 break; 1550 default: 1551 DRM_ERROR("unknown voltage object table\n"); 1552 return false; 1553 } 1554 1555 } 1556 return false; 1557 } 1558 1559 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, 1560 u8 voltage_type, u8 voltage_mode, 1561 struct atom_voltage_table *voltage_table) 1562 { 1563 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1564 u8 frev, crev; 1565 u16 data_offset, size; 1566 int i; 1567 union voltage_object_info *voltage_info; 1568 union voltage_object *voltage_object = NULL; 1569 1570 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1571 &frev, &crev, &data_offset)) { 1572 voltage_info = (union voltage_object_info *) 1573 (adev->mode_info.atom_context->bios + data_offset); 1574 1575 switch (frev) { 1576 case 3: 1577 switch (crev) { 1578 case 1: 1579 voltage_object = (union voltage_object *) 1580 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1581 voltage_type, voltage_mode); 1582 if (voltage_object) { 1583 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 1584 &voltage_object->v3.asGpioVoltageObj; 1585 VOLTAGE_LUT_ENTRY_V2 *lut; 1586 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 1587 return -EINVAL; 1588 lut = &gpio->asVolGpioLut[0]; 1589 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 1590 voltage_table->entries[i].value = 1591 le16_to_cpu(lut->usVoltageValue); 1592 voltage_table->entries[i].smio_low = 1593 le32_to_cpu(lut->ulVoltageId); 1594 lut = (VOLTAGE_LUT_ENTRY_V2 *) 1595 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 1596 } 1597 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 1598 voltage_table->count = gpio->ucGpioEntryNum; 1599 voltage_table->phase_delay = gpio->ucPhaseDelay; 1600 return 0; 1601 } 1602 break; 1603 default: 1604 DRM_ERROR("unknown voltage object table\n"); 1605 return -EINVAL; 1606 } 1607 break; 1608 default: 1609 DRM_ERROR("unknown voltage object table\n"); 1610 return -EINVAL; 1611 } 1612 } 1613 return -EINVAL; 1614 } 1615 1616 union vram_info { 1617 struct _ATOM_VRAM_INFO_V3 v1_3; 1618 struct _ATOM_VRAM_INFO_V4 v1_4; 1619 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 1620 }; 1621 1622 #define MEM_ID_MASK 0xff000000 1623 #define MEM_ID_SHIFT 24 1624 #define CLOCK_RANGE_MASK 0x00ffffff 1625 #define CLOCK_RANGE_SHIFT 0 1626 #define LOW_NIBBLE_MASK 0xf 1627 #define DATA_EQU_PREV 0 1628 #define DATA_FROM_TABLE 4 1629 1630 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, 1631 u8 module_index, 1632 struct atom_mc_reg_table *reg_table) 1633 { 1634 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 1635 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 1636 u32 i = 0, j; 1637 u16 data_offset, size; 1638 union vram_info *vram_info; 1639 1640 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 1641 1642 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1643 &frev, &crev, &data_offset)) { 1644 vram_info = (union vram_info *) 1645 (adev->mode_info.atom_context->bios + data_offset); 1646 switch (frev) { 1647 case 1: 1648 DRM_ERROR("old table version %d, %d\n", frev, crev); 1649 return -EINVAL; 1650 case 2: 1651 switch (crev) { 1652 case 1: 1653 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 1654 ATOM_INIT_REG_BLOCK *reg_block = 1655 (ATOM_INIT_REG_BLOCK *) 1656 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 1657 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 1658 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1659 ((u8 *)reg_block + (2 * sizeof(u16)) + 1660 le16_to_cpu(reg_block->usRegIndexTblSize)); 1661 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 1662 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 1663 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 1664 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 1665 return -EINVAL; 1666 while (i < num_entries) { 1667 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 1668 break; 1669 reg_table->mc_reg_address[i].s1 = 1670 (u16)(le16_to_cpu(format->usRegIndex)); 1671 reg_table->mc_reg_address[i].pre_reg_data = 1672 (u8)(format->ucPreRegDataLength); 1673 i++; 1674 format = (ATOM_INIT_REG_INDEX_FORMAT *) 1675 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 1676 } 1677 reg_table->last = i; 1678 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1679 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 1680 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1681 >> MEM_ID_SHIFT); 1682 if (module_index == t_mem_id) { 1683 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 1684 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1685 >> CLOCK_RANGE_SHIFT); 1686 for (i = 0, j = 1; i < reg_table->last; i++) { 1687 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 1688 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1689 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1690 j++; 1691 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 1692 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1693 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 1694 } 1695 } 1696 num_ranges++; 1697 } 1698 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1699 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1700 } 1701 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 1702 return -EINVAL; 1703 reg_table->num_entries = num_ranges; 1704 } else 1705 return -EINVAL; 1706 break; 1707 default: 1708 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1709 return -EINVAL; 1710 } 1711 break; 1712 default: 1713 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1714 return -EINVAL; 1715 } 1716 return 0; 1717 } 1718 return -EINVAL; 1719 } 1720 1721 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) 1722 { 1723 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); 1724 u8 frev, crev; 1725 u16 data_offset, size; 1726 1727 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1728 &frev, &crev, &data_offset)) 1729 return true; 1730 1731 return false; 1732 } 1733 1734 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) 1735 { 1736 uint32_t bios_6_scratch; 1737 1738 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1739 1740 if (lock) { 1741 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1742 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 1743 } else { 1744 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1745 bios_6_scratch |= ATOM_S6_ACC_MODE; 1746 } 1747 1748 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1749 } 1750 1751 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) 1752 { 1753 uint32_t bios_2_scratch, bios_6_scratch; 1754 1755 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); 1756 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1757 1758 /* let the bios control the backlight */ 1759 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1760 1761 /* tell the bios not to handle mode switching */ 1762 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 1763 1764 /* clear the vbios dpms state */ 1765 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 1766 1767 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); 1768 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1769 } 1770 1771 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) 1772 { 1773 int i; 1774 1775 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1776 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); 1777 } 1778 1779 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) 1780 { 1781 int i; 1782 1783 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1784 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); 1785 } 1786 1787 /* Atom needs data in little endian format 1788 * so swap as appropriate when copying data to 1789 * or from atom. Note that atom operates on 1790 * dw units. 1791 */ 1792 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 1793 { 1794 #ifdef __BIG_ENDIAN 1795 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 1796 u32 *dst32, *src32; 1797 int i; 1798 1799 memcpy(src_tmp, src, num_bytes); 1800 src32 = (u32 *)src_tmp; 1801 dst32 = (u32 *)dst_tmp; 1802 if (to_le) { 1803 for (i = 0; i < ((num_bytes + 3) / 4); i++) 1804 dst32[i] = cpu_to_le32(src32[i]); 1805 memcpy(dst, dst_tmp, num_bytes); 1806 } else { 1807 u8 dws = num_bytes & ~3; 1808 for (i = 0; i < ((num_bytes + 3) / 4); i++) 1809 dst32[i] = le32_to_cpu(src32[i]); 1810 memcpy(dst, dst_tmp, dws); 1811 if (num_bytes % 4) { 1812 for (i = 0; i < (num_bytes % 4); i++) 1813 dst[dws+i] = dst_tmp[dws+i]; 1814 } 1815 } 1816 #else 1817 memcpy(dst, src, num_bytes); 1818 #endif 1819 } 1820