1 /* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 #include <drm/drmP.h> 27 #include <drm/amdgpu_drm.h> 28 #include "amdgpu.h" 29 #include "amdgpu_atombios.h" 30 #include "amdgpu_i2c.h" 31 32 #include "atom.h" 33 #include "atom-bits.h" 34 #include "atombios_encoders.h" 35 #include "bif/bif_4_1_d.h" 36 37 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, 38 ATOM_GPIO_I2C_ASSIGMENT *gpio, 39 u8 index) 40 { 41 42 } 43 44 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 45 { 46 struct amdgpu_i2c_bus_rec i2c; 47 48 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 49 50 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); 51 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); 52 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); 53 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); 54 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); 55 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); 56 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); 57 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); 58 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 59 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 60 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 61 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 62 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 63 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 64 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 65 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 66 67 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 68 i2c.hw_capable = true; 69 else 70 i2c.hw_capable = false; 71 72 if (gpio->sucI2cId.ucAccess == 0xa0) 73 i2c.mm_i2c = true; 74 else 75 i2c.mm_i2c = false; 76 77 i2c.i2c_id = gpio->sucI2cId.ucAccess; 78 79 if (i2c.mask_clk_reg) 80 i2c.valid = true; 81 else 82 i2c.valid = false; 83 84 return i2c; 85 } 86 87 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, 88 uint8_t id) 89 { 90 struct atom_context *ctx = adev->mode_info.atom_context; 91 ATOM_GPIO_I2C_ASSIGMENT *gpio; 92 struct amdgpu_i2c_bus_rec i2c; 93 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 94 struct _ATOM_GPIO_I2C_INFO *i2c_info; 95 uint16_t data_offset, size; 96 int i, num_indices; 97 98 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 99 i2c.valid = false; 100 101 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 102 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 103 104 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 105 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 106 107 gpio = &i2c_info->asGPIO_Info[0]; 108 for (i = 0; i < num_indices; i++) { 109 110 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 111 112 if (gpio->sucI2cId.ucAccess == id) { 113 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 114 break; 115 } 116 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 117 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 118 } 119 } 120 121 return i2c; 122 } 123 124 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) 125 { 126 struct atom_context *ctx = adev->mode_info.atom_context; 127 ATOM_GPIO_I2C_ASSIGMENT *gpio; 128 struct amdgpu_i2c_bus_rec i2c; 129 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 130 struct _ATOM_GPIO_I2C_INFO *i2c_info; 131 uint16_t data_offset, size; 132 int i, num_indices; 133 char stmp[32]; 134 135 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 136 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 137 138 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 139 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 140 141 gpio = &i2c_info->asGPIO_Info[0]; 142 for (i = 0; i < num_indices; i++) { 143 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 144 145 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 146 147 if (i2c.valid) { 148 sprintf(stmp, "0x%x", i2c.i2c_id); 149 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); 150 } 151 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 152 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 153 } 154 } 155 } 156 157 struct amdgpu_gpio_rec 158 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, 159 u8 id) 160 { 161 struct atom_context *ctx = adev->mode_info.atom_context; 162 struct amdgpu_gpio_rec gpio; 163 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 164 struct _ATOM_GPIO_PIN_LUT *gpio_info; 165 ATOM_GPIO_PIN_ASSIGNMENT *pin; 166 u16 data_offset, size; 167 int i, num_indices; 168 169 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); 170 gpio.valid = false; 171 172 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 173 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 174 175 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 176 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 177 178 pin = gpio_info->asGPIO_Pin; 179 for (i = 0; i < num_indices; i++) { 180 if (id == pin->ucGPIO_ID) { 181 gpio.id = pin->ucGPIO_ID; 182 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); 183 gpio.shift = pin->ucGpioPinBitShift; 184 gpio.mask = (1 << pin->ucGpioPinBitShift); 185 gpio.valid = true; 186 break; 187 } 188 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 189 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 190 } 191 } 192 193 return gpio; 194 } 195 196 static struct amdgpu_hpd 197 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, 198 struct amdgpu_gpio_rec *gpio) 199 { 200 struct amdgpu_hpd hpd; 201 u32 reg; 202 203 memset(&hpd, 0, sizeof(struct amdgpu_hpd)); 204 205 reg = amdgpu_display_hpd_get_gpio_reg(adev); 206 207 hpd.gpio = *gpio; 208 if (gpio->reg == reg) { 209 switch(gpio->mask) { 210 case (1 << 0): 211 hpd.hpd = AMDGPU_HPD_1; 212 break; 213 case (1 << 8): 214 hpd.hpd = AMDGPU_HPD_2; 215 break; 216 case (1 << 16): 217 hpd.hpd = AMDGPU_HPD_3; 218 break; 219 case (1 << 24): 220 hpd.hpd = AMDGPU_HPD_4; 221 break; 222 case (1 << 26): 223 hpd.hpd = AMDGPU_HPD_5; 224 break; 225 case (1 << 28): 226 hpd.hpd = AMDGPU_HPD_6; 227 break; 228 default: 229 hpd.hpd = AMDGPU_HPD_NONE; 230 break; 231 } 232 } else 233 hpd.hpd = AMDGPU_HPD_NONE; 234 return hpd; 235 } 236 237 static const int object_connector_convert[] = { 238 DRM_MODE_CONNECTOR_Unknown, 239 DRM_MODE_CONNECTOR_DVII, 240 DRM_MODE_CONNECTOR_DVII, 241 DRM_MODE_CONNECTOR_DVID, 242 DRM_MODE_CONNECTOR_DVID, 243 DRM_MODE_CONNECTOR_VGA, 244 DRM_MODE_CONNECTOR_Composite, 245 DRM_MODE_CONNECTOR_SVIDEO, 246 DRM_MODE_CONNECTOR_Unknown, 247 DRM_MODE_CONNECTOR_Unknown, 248 DRM_MODE_CONNECTOR_9PinDIN, 249 DRM_MODE_CONNECTOR_Unknown, 250 DRM_MODE_CONNECTOR_HDMIA, 251 DRM_MODE_CONNECTOR_HDMIB, 252 DRM_MODE_CONNECTOR_LVDS, 253 DRM_MODE_CONNECTOR_9PinDIN, 254 DRM_MODE_CONNECTOR_Unknown, 255 DRM_MODE_CONNECTOR_Unknown, 256 DRM_MODE_CONNECTOR_Unknown, 257 DRM_MODE_CONNECTOR_DisplayPort, 258 DRM_MODE_CONNECTOR_eDP, 259 DRM_MODE_CONNECTOR_Unknown 260 }; 261 262 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) 263 { 264 struct amdgpu_mode_info *mode_info = &adev->mode_info; 265 struct atom_context *ctx = mode_info->atom_context; 266 int index = GetIndexIntoMasterTable(DATA, Object_Header); 267 u16 size, data_offset; 268 u8 frev, crev; 269 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 270 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 271 ATOM_OBJECT_TABLE *router_obj; 272 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 273 ATOM_OBJECT_HEADER *obj_header; 274 int i, j, k, path_size, device_support; 275 int connector_type; 276 u16 conn_id, connector_object_id; 277 struct amdgpu_i2c_bus_rec ddc_bus; 278 struct amdgpu_router router; 279 struct amdgpu_gpio_rec gpio; 280 struct amdgpu_hpd hpd; 281 282 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 283 return false; 284 285 if (crev < 2) 286 return false; 287 288 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 289 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 290 (ctx->bios + data_offset + 291 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 292 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 293 (ctx->bios + data_offset + 294 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 295 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 296 (ctx->bios + data_offset + 297 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 298 router_obj = (ATOM_OBJECT_TABLE *) 299 (ctx->bios + data_offset + 300 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 301 device_support = le16_to_cpu(obj_header->usDeviceSupport); 302 303 path_size = 0; 304 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 305 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 306 ATOM_DISPLAY_OBJECT_PATH *path; 307 addr += path_size; 308 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 309 path_size += le16_to_cpu(path->usSize); 310 311 if (device_support & le16_to_cpu(path->usDeviceTag)) { 312 uint8_t con_obj_id, con_obj_num, con_obj_type; 313 314 con_obj_id = 315 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 316 >> OBJECT_ID_SHIFT; 317 con_obj_num = 318 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 319 >> ENUM_ID_SHIFT; 320 con_obj_type = 321 (le16_to_cpu(path->usConnObjectId) & 322 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 323 324 connector_type = 325 object_connector_convert[con_obj_id]; 326 connector_object_id = con_obj_id; 327 328 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 329 continue; 330 331 router.ddc_valid = false; 332 router.cd_valid = false; 333 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 334 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 335 336 grph_obj_id = 337 (le16_to_cpu(path->usGraphicObjIds[j]) & 338 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 339 grph_obj_num = 340 (le16_to_cpu(path->usGraphicObjIds[j]) & 341 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 342 grph_obj_type = 343 (le16_to_cpu(path->usGraphicObjIds[j]) & 344 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 345 346 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 347 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 348 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 349 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 350 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 351 (ctx->bios + data_offset + 352 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 353 ATOM_ENCODER_CAP_RECORD *cap_record; 354 u16 caps = 0; 355 356 while (record->ucRecordSize > 0 && 357 record->ucRecordType > 0 && 358 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 359 switch (record->ucRecordType) { 360 case ATOM_ENCODER_CAP_RECORD_TYPE: 361 cap_record =(ATOM_ENCODER_CAP_RECORD *) 362 record; 363 caps = le16_to_cpu(cap_record->usEncoderCap); 364 break; 365 } 366 record = (ATOM_COMMON_RECORD_HEADER *) 367 ((char *)record + record->ucRecordSize); 368 } 369 amdgpu_display_add_encoder(adev, encoder_obj, 370 le16_to_cpu(path->usDeviceTag), 371 caps); 372 } 373 } 374 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 375 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 376 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 377 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 378 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 379 (ctx->bios + data_offset + 380 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 381 ATOM_I2C_RECORD *i2c_record; 382 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 383 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 384 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 385 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 386 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 387 (ctx->bios + data_offset + 388 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 389 u8 *num_dst_objs = (u8 *) 390 ((u8 *)router_src_dst_table + 1 + 391 (router_src_dst_table->ucNumberOfSrc * 2)); 392 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 393 int enum_id; 394 395 router.router_id = router_obj_id; 396 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 397 if (le16_to_cpu(path->usConnObjectId) == 398 le16_to_cpu(dst_objs[enum_id])) 399 break; 400 } 401 402 while (record->ucRecordSize > 0 && 403 record->ucRecordType > 0 && 404 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 405 switch (record->ucRecordType) { 406 case ATOM_I2C_RECORD_TYPE: 407 i2c_record = 408 (ATOM_I2C_RECORD *) 409 record; 410 i2c_config = 411 (ATOM_I2C_ID_CONFIG_ACCESS *) 412 &i2c_record->sucI2cId; 413 router.i2c_info = 414 amdgpu_atombios_lookup_i2c_gpio(adev, 415 i2c_config-> 416 ucAccess); 417 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 418 break; 419 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 420 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 421 record; 422 router.ddc_valid = true; 423 router.ddc_mux_type = ddc_path->ucMuxType; 424 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 425 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 426 break; 427 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 428 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 429 record; 430 router.cd_valid = true; 431 router.cd_mux_type = cd_path->ucMuxType; 432 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 433 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 434 break; 435 } 436 record = (ATOM_COMMON_RECORD_HEADER *) 437 ((char *)record + record->ucRecordSize); 438 } 439 } 440 } 441 } 442 } 443 444 /* look up gpio for ddc, hpd */ 445 ddc_bus.valid = false; 446 hpd.hpd = AMDGPU_HPD_NONE; 447 if ((le16_to_cpu(path->usDeviceTag) & 448 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 449 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 450 if (le16_to_cpu(path->usConnObjectId) == 451 le16_to_cpu(con_obj->asObjects[j]. 452 usObjectID)) { 453 ATOM_COMMON_RECORD_HEADER 454 *record = 455 (ATOM_COMMON_RECORD_HEADER 456 *) 457 (ctx->bios + data_offset + 458 le16_to_cpu(con_obj-> 459 asObjects[j]. 460 usRecordOffset)); 461 ATOM_I2C_RECORD *i2c_record; 462 ATOM_HPD_INT_RECORD *hpd_record; 463 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 464 465 while (record->ucRecordSize > 0 && 466 record->ucRecordType > 0 && 467 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 468 switch (record->ucRecordType) { 469 case ATOM_I2C_RECORD_TYPE: 470 i2c_record = 471 (ATOM_I2C_RECORD *) 472 record; 473 i2c_config = 474 (ATOM_I2C_ID_CONFIG_ACCESS *) 475 &i2c_record->sucI2cId; 476 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, 477 i2c_config-> 478 ucAccess); 479 break; 480 case ATOM_HPD_INT_RECORD_TYPE: 481 hpd_record = 482 (ATOM_HPD_INT_RECORD *) 483 record; 484 gpio = amdgpu_atombios_lookup_gpio(adev, 485 hpd_record->ucHPDIntGPIOID); 486 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); 487 hpd.plugged_state = hpd_record->ucPlugged_PinState; 488 break; 489 } 490 record = 491 (ATOM_COMMON_RECORD_HEADER 492 *) ((char *)record 493 + 494 record-> 495 ucRecordSize); 496 } 497 break; 498 } 499 } 500 } 501 502 /* needed for aux chan transactions */ 503 ddc_bus.hpd = hpd.hpd; 504 505 conn_id = le16_to_cpu(path->usConnObjectId); 506 507 amdgpu_display_add_connector(adev, 508 conn_id, 509 le16_to_cpu(path->usDeviceTag), 510 connector_type, &ddc_bus, 511 connector_object_id, 512 &hpd, 513 &router); 514 515 } 516 } 517 518 amdgpu_link_encoder_connector(adev->ddev); 519 520 return true; 521 } 522 523 union firmware_info { 524 ATOM_FIRMWARE_INFO info; 525 ATOM_FIRMWARE_INFO_V1_2 info_12; 526 ATOM_FIRMWARE_INFO_V1_3 info_13; 527 ATOM_FIRMWARE_INFO_V1_4 info_14; 528 ATOM_FIRMWARE_INFO_V2_1 info_21; 529 ATOM_FIRMWARE_INFO_V2_2 info_22; 530 }; 531 532 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 533 { 534 struct amdgpu_mode_info *mode_info = &adev->mode_info; 535 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 536 uint8_t frev, crev; 537 uint16_t data_offset; 538 int ret = -EINVAL; 539 540 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 541 &frev, &crev, &data_offset)) { 542 int i; 543 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; 544 struct amdgpu_pll *spll = &adev->clock.spll; 545 struct amdgpu_pll *mpll = &adev->clock.mpll; 546 union firmware_info *firmware_info = 547 (union firmware_info *)(mode_info->atom_context->bios + 548 data_offset); 549 /* pixel clocks */ 550 ppll->reference_freq = 551 le16_to_cpu(firmware_info->info.usReferenceClock); 552 ppll->reference_div = 0; 553 554 ppll->pll_out_min = 555 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 556 ppll->pll_out_max = 557 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 558 559 ppll->lcd_pll_out_min = 560 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 561 if (ppll->lcd_pll_out_min == 0) 562 ppll->lcd_pll_out_min = ppll->pll_out_min; 563 ppll->lcd_pll_out_max = 564 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 565 if (ppll->lcd_pll_out_max == 0) 566 ppll->lcd_pll_out_max = ppll->pll_out_max; 567 568 if (ppll->pll_out_min == 0) 569 ppll->pll_out_min = 64800; 570 571 ppll->pll_in_min = 572 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 573 ppll->pll_in_max = 574 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 575 576 ppll->min_post_div = 2; 577 ppll->max_post_div = 0x7f; 578 ppll->min_frac_feedback_div = 0; 579 ppll->max_frac_feedback_div = 9; 580 ppll->min_ref_div = 2; 581 ppll->max_ref_div = 0x3ff; 582 ppll->min_feedback_div = 4; 583 ppll->max_feedback_div = 0xfff; 584 ppll->best_vco = 0; 585 586 for (i = 1; i < AMDGPU_MAX_PPLL; i++) 587 adev->clock.ppll[i] = *ppll; 588 589 /* system clock */ 590 spll->reference_freq = 591 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 592 spll->reference_div = 0; 593 594 spll->pll_out_min = 595 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 596 spll->pll_out_max = 597 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 598 599 /* ??? */ 600 if (spll->pll_out_min == 0) 601 spll->pll_out_min = 64800; 602 603 spll->pll_in_min = 604 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 605 spll->pll_in_max = 606 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 607 608 spll->min_post_div = 1; 609 spll->max_post_div = 1; 610 spll->min_ref_div = 2; 611 spll->max_ref_div = 0xff; 612 spll->min_feedback_div = 4; 613 spll->max_feedback_div = 0xff; 614 spll->best_vco = 0; 615 616 /* memory clock */ 617 mpll->reference_freq = 618 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 619 mpll->reference_div = 0; 620 621 mpll->pll_out_min = 622 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 623 mpll->pll_out_max = 624 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 625 626 /* ??? */ 627 if (mpll->pll_out_min == 0) 628 mpll->pll_out_min = 64800; 629 630 mpll->pll_in_min = 631 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 632 mpll->pll_in_max = 633 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 634 635 adev->clock.default_sclk = 636 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 637 adev->clock.default_mclk = 638 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 639 640 mpll->min_post_div = 1; 641 mpll->max_post_div = 1; 642 mpll->min_ref_div = 2; 643 mpll->max_ref_div = 0xff; 644 mpll->min_feedback_div = 4; 645 mpll->max_feedback_div = 0xff; 646 mpll->best_vco = 0; 647 648 /* disp clock */ 649 adev->clock.default_dispclk = 650 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 651 /* set a reasonable default for DP */ 652 if (adev->clock.default_dispclk < 53900) { 653 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 654 adev->clock.default_dispclk / 100); 655 adev->clock.default_dispclk = 60000; 656 } 657 adev->clock.dp_extclk = 658 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 659 adev->clock.current_dispclk = adev->clock.default_dispclk; 660 661 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 662 if (adev->clock.max_pixel_clock == 0) 663 adev->clock.max_pixel_clock = 40000; 664 665 /* not technically a clock, but... */ 666 adev->mode_info.firmware_flags = 667 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 668 669 ret = 0; 670 } 671 672 adev->pm.current_sclk = adev->clock.default_sclk; 673 adev->pm.current_mclk = adev->clock.default_mclk; 674 675 return ret; 676 } 677 678 union gfx_info { 679 ATOM_GFX_INFO_V2_1 info; 680 }; 681 682 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) 683 { 684 struct amdgpu_mode_info *mode_info = &adev->mode_info; 685 int index = GetIndexIntoMasterTable(DATA, GFX_Info); 686 uint8_t frev, crev; 687 uint16_t data_offset; 688 int ret = -EINVAL; 689 690 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 691 &frev, &crev, &data_offset)) { 692 union gfx_info *gfx_info = (union gfx_info *) 693 (mode_info->atom_context->bios + data_offset); 694 695 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; 696 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; 697 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; 698 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; 699 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; 700 adev->gfx.config.max_texture_channel_caches = 701 gfx_info->info.max_texture_channel_caches; 702 703 ret = 0; 704 } 705 return ret; 706 } 707 708 union igp_info { 709 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 710 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 711 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 712 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 713 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 714 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; 715 }; 716 717 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, 718 struct amdgpu_atom_ss *ss, 719 int id) 720 { 721 struct amdgpu_mode_info *mode_info = &adev->mode_info; 722 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 723 u16 data_offset, size; 724 union igp_info *igp_info; 725 u8 frev, crev; 726 u16 percentage = 0, rate = 0; 727 728 /* get any igp specific overrides */ 729 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 730 &frev, &crev, &data_offset)) { 731 igp_info = (union igp_info *) 732 (mode_info->atom_context->bios + data_offset); 733 switch (crev) { 734 case 6: 735 switch (id) { 736 case ASIC_INTERNAL_SS_ON_TMDS: 737 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 738 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 739 break; 740 case ASIC_INTERNAL_SS_ON_HDMI: 741 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 742 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 743 break; 744 case ASIC_INTERNAL_SS_ON_LVDS: 745 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 746 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 747 break; 748 } 749 break; 750 case 7: 751 switch (id) { 752 case ASIC_INTERNAL_SS_ON_TMDS: 753 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 754 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 755 break; 756 case ASIC_INTERNAL_SS_ON_HDMI: 757 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 758 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 759 break; 760 case ASIC_INTERNAL_SS_ON_LVDS: 761 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 762 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 763 break; 764 } 765 break; 766 case 8: 767 switch (id) { 768 case ASIC_INTERNAL_SS_ON_TMDS: 769 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 770 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 771 break; 772 case ASIC_INTERNAL_SS_ON_HDMI: 773 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 774 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 775 break; 776 case ASIC_INTERNAL_SS_ON_LVDS: 777 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 778 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 779 break; 780 } 781 break; 782 case 9: 783 switch (id) { 784 case ASIC_INTERNAL_SS_ON_TMDS: 785 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); 786 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); 787 break; 788 case ASIC_INTERNAL_SS_ON_HDMI: 789 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); 790 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); 791 break; 792 case ASIC_INTERNAL_SS_ON_LVDS: 793 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); 794 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); 795 break; 796 } 797 break; 798 default: 799 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 800 break; 801 } 802 if (percentage) 803 ss->percentage = percentage; 804 if (rate) 805 ss->rate = rate; 806 } 807 } 808 809 union asic_ss_info { 810 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 811 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 812 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 813 }; 814 815 union asic_ss_assignment { 816 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 817 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 818 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 819 }; 820 821 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, 822 struct amdgpu_atom_ss *ss, 823 int id, u32 clock) 824 { 825 struct amdgpu_mode_info *mode_info = &adev->mode_info; 826 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 827 uint16_t data_offset, size; 828 union asic_ss_info *ss_info; 829 union asic_ss_assignment *ss_assign; 830 uint8_t frev, crev; 831 int i, num_indices; 832 833 if (id == ASIC_INTERNAL_MEMORY_SS) { 834 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 835 return false; 836 } 837 if (id == ASIC_INTERNAL_ENGINE_SS) { 838 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 839 return false; 840 } 841 842 memset(ss, 0, sizeof(struct amdgpu_atom_ss)); 843 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 844 &frev, &crev, &data_offset)) { 845 846 ss_info = 847 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 848 849 switch (frev) { 850 case 1: 851 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 852 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 853 854 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 855 for (i = 0; i < num_indices; i++) { 856 if ((ss_assign->v1.ucClockIndication == id) && 857 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 858 ss->percentage = 859 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 860 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 861 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 862 ss->percentage_divider = 100; 863 return true; 864 } 865 ss_assign = (union asic_ss_assignment *) 866 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 867 } 868 break; 869 case 2: 870 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 871 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 872 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 873 for (i = 0; i < num_indices; i++) { 874 if ((ss_assign->v2.ucClockIndication == id) && 875 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 876 ss->percentage = 877 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 878 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 879 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 880 ss->percentage_divider = 100; 881 if ((crev == 2) && 882 ((id == ASIC_INTERNAL_ENGINE_SS) || 883 (id == ASIC_INTERNAL_MEMORY_SS))) 884 ss->rate /= 100; 885 return true; 886 } 887 ss_assign = (union asic_ss_assignment *) 888 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 889 } 890 break; 891 case 3: 892 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 893 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 894 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 895 for (i = 0; i < num_indices; i++) { 896 if ((ss_assign->v3.ucClockIndication == id) && 897 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 898 ss->percentage = 899 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 900 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 901 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 902 if (ss_assign->v3.ucSpreadSpectrumMode & 903 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 904 ss->percentage_divider = 1000; 905 else 906 ss->percentage_divider = 100; 907 if ((id == ASIC_INTERNAL_ENGINE_SS) || 908 (id == ASIC_INTERNAL_MEMORY_SS)) 909 ss->rate /= 100; 910 if (adev->flags & AMD_IS_APU) 911 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 912 return true; 913 } 914 ss_assign = (union asic_ss_assignment *) 915 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 916 } 917 break; 918 default: 919 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 920 break; 921 } 922 923 } 924 return false; 925 } 926 927 union get_clock_dividers { 928 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 929 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 930 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 931 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 932 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 933 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 934 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 935 }; 936 937 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 938 u8 clock_type, 939 u32 clock, 940 bool strobe_mode, 941 struct atom_clock_dividers *dividers) 942 { 943 union get_clock_dividers args; 944 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 945 u8 frev, crev; 946 947 memset(&args, 0, sizeof(args)); 948 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 949 950 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 951 return -EINVAL; 952 953 switch (crev) { 954 case 4: 955 /* fusion */ 956 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 957 958 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 959 960 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 961 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 962 break; 963 case 6: 964 /* CI */ 965 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 966 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 967 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 968 969 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 970 971 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 972 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 973 dividers->ref_div = args.v6_out.ucPllRefDiv; 974 dividers->post_div = args.v6_out.ucPllPostDiv; 975 dividers->flags = args.v6_out.ucPllCntlFlag; 976 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 977 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 978 break; 979 default: 980 return -EINVAL; 981 } 982 return 0; 983 } 984 985 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, 986 u32 clock, 987 bool strobe_mode, 988 struct atom_mpll_param *mpll_param) 989 { 990 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 991 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 992 u8 frev, crev; 993 994 memset(&args, 0, sizeof(args)); 995 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 996 997 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 998 return -EINVAL; 999 1000 switch (frev) { 1001 case 2: 1002 switch (crev) { 1003 case 1: 1004 /* SI */ 1005 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 1006 args.ucInputFlag = 0; 1007 if (strobe_mode) 1008 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 1009 1010 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1011 1012 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 1013 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 1014 mpll_param->post_div = args.ucPostDiv; 1015 mpll_param->dll_speed = args.ucDllSpeed; 1016 mpll_param->bwcntl = args.ucBWCntl; 1017 mpll_param->vco_mode = 1018 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 1019 mpll_param->yclk_sel = 1020 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 1021 mpll_param->qdr = 1022 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 1023 mpll_param->half_rate = 1024 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 1025 break; 1026 default: 1027 return -EINVAL; 1028 } 1029 break; 1030 default: 1031 return -EINVAL; 1032 } 1033 return 0; 1034 } 1035 1036 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) 1037 { 1038 GET_ENGINE_CLOCK_PS_ALLOCATION args; 1039 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 1040 1041 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1042 return le32_to_cpu(args.ulReturnEngineClock); 1043 } 1044 1045 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) 1046 { 1047 GET_MEMORY_CLOCK_PS_ALLOCATION args; 1048 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 1049 1050 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1051 return le32_to_cpu(args.ulReturnMemoryClock); 1052 } 1053 1054 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, 1055 uint32_t eng_clock) 1056 { 1057 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1058 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 1059 1060 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 1061 1062 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1063 } 1064 1065 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, 1066 uint32_t mem_clock) 1067 { 1068 SET_MEMORY_CLOCK_PS_ALLOCATION args; 1069 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 1070 1071 if (adev->flags & AMD_IS_APU) 1072 return; 1073 1074 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 1075 1076 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1077 } 1078 1079 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 1080 u32 eng_clock, u32 mem_clock) 1081 { 1082 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1083 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 1084 u32 tmp; 1085 1086 memset(&args, 0, sizeof(args)); 1087 1088 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 1089 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 1090 1091 args.ulTargetEngineClock = cpu_to_le32(tmp); 1092 if (mem_clock) 1093 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 1094 1095 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1096 } 1097 1098 union set_voltage { 1099 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 1100 struct _SET_VOLTAGE_PARAMETERS v1; 1101 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 1102 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 1103 }; 1104 1105 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, 1106 u16 voltage_level, 1107 u8 voltage_type) 1108 { 1109 union set_voltage args; 1110 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1111 u8 frev, crev, volt_index = voltage_level; 1112 1113 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1114 return; 1115 1116 /* 0xff01 is a flag rather then an actual voltage */ 1117 if (voltage_level == 0xff01) 1118 return; 1119 1120 switch (crev) { 1121 case 1: 1122 args.v1.ucVoltageType = voltage_type; 1123 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 1124 args.v1.ucVoltageIndex = volt_index; 1125 break; 1126 case 2: 1127 args.v2.ucVoltageType = voltage_type; 1128 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 1129 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 1130 break; 1131 case 3: 1132 args.v3.ucVoltageType = voltage_type; 1133 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 1134 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 1135 break; 1136 default: 1137 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1138 return; 1139 } 1140 1141 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1142 } 1143 1144 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, 1145 u16 *leakage_id) 1146 { 1147 union set_voltage args; 1148 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1149 u8 frev, crev; 1150 1151 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1152 return -EINVAL; 1153 1154 switch (crev) { 1155 case 3: 1156 case 4: 1157 args.v3.ucVoltageType = 0; 1158 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 1159 args.v3.usVoltageLevel = 0; 1160 1161 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1162 1163 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 1164 break; 1165 default: 1166 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1167 return -EINVAL; 1168 } 1169 1170 return 0; 1171 } 1172 1173 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, 1174 u16 *vddc, u16 *vddci, 1175 u16 virtual_voltage_id, 1176 u16 vbios_voltage_id) 1177 { 1178 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 1179 u8 frev, crev; 1180 u16 data_offset, size; 1181 int i, j; 1182 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 1183 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 1184 1185 *vddc = 0; 1186 *vddci = 0; 1187 1188 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1189 &frev, &crev, &data_offset)) 1190 return -EINVAL; 1191 1192 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 1193 (adev->mode_info.atom_context->bios + data_offset); 1194 1195 switch (frev) { 1196 case 1: 1197 return -EINVAL; 1198 case 2: 1199 switch (crev) { 1200 case 1: 1201 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 1202 return -EINVAL; 1203 leakage_bin = (u16 *) 1204 (adev->mode_info.atom_context->bios + data_offset + 1205 le16_to_cpu(profile->usLeakageBinArrayOffset)); 1206 vddc_id_buf = (u16 *) 1207 (adev->mode_info.atom_context->bios + data_offset + 1208 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 1209 vddc_buf = (u16 *) 1210 (adev->mode_info.atom_context->bios + data_offset + 1211 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 1212 vddci_id_buf = (u16 *) 1213 (adev->mode_info.atom_context->bios + data_offset + 1214 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 1215 vddci_buf = (u16 *) 1216 (adev->mode_info.atom_context->bios + data_offset + 1217 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 1218 1219 if (profile->ucElbVDDC_Num > 0) { 1220 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 1221 if (vddc_id_buf[i] == virtual_voltage_id) { 1222 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1223 if (vbios_voltage_id <= leakage_bin[j]) { 1224 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 1225 break; 1226 } 1227 } 1228 break; 1229 } 1230 } 1231 } 1232 if (profile->ucElbVDDCI_Num > 0) { 1233 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 1234 if (vddci_id_buf[i] == virtual_voltage_id) { 1235 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1236 if (vbios_voltage_id <= leakage_bin[j]) { 1237 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 1238 break; 1239 } 1240 } 1241 break; 1242 } 1243 } 1244 } 1245 break; 1246 default: 1247 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1248 return -EINVAL; 1249 } 1250 break; 1251 default: 1252 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1253 return -EINVAL; 1254 } 1255 1256 return 0; 1257 } 1258 1259 union get_voltage_info { 1260 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 1261 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 1262 }; 1263 1264 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, 1265 u16 virtual_voltage_id, 1266 u16 *voltage) 1267 { 1268 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 1269 u32 entry_id; 1270 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 1271 union get_voltage_info args; 1272 1273 for (entry_id = 0; entry_id < count; entry_id++) { 1274 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 1275 virtual_voltage_id) 1276 break; 1277 } 1278 1279 if (entry_id >= count) 1280 return -EINVAL; 1281 1282 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 1283 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1284 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 1285 args.in.ulSCLKFreq = 1286 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 1287 1288 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1289 1290 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 1291 1292 return 0; 1293 } 1294 1295 union voltage_object_info { 1296 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 1297 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 1298 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 1299 }; 1300 1301 union voltage_object { 1302 struct _ATOM_VOLTAGE_OBJECT v1; 1303 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 1304 union _ATOM_VOLTAGE_OBJECT_V3 v3; 1305 }; 1306 1307 1308 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 1309 u8 voltage_type, u8 voltage_mode) 1310 { 1311 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 1312 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 1313 u8 *start = (u8*)v3; 1314 1315 while (offset < size) { 1316 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 1317 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 1318 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 1319 return vo; 1320 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 1321 } 1322 return NULL; 1323 } 1324 1325 bool 1326 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, 1327 u8 voltage_type, u8 voltage_mode) 1328 { 1329 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1330 u8 frev, crev; 1331 u16 data_offset, size; 1332 union voltage_object_info *voltage_info; 1333 1334 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1335 &frev, &crev, &data_offset)) { 1336 voltage_info = (union voltage_object_info *) 1337 (adev->mode_info.atom_context->bios + data_offset); 1338 1339 switch (frev) { 1340 case 3: 1341 switch (crev) { 1342 case 1: 1343 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1344 voltage_type, voltage_mode)) 1345 return true; 1346 break; 1347 default: 1348 DRM_ERROR("unknown voltage object table\n"); 1349 return false; 1350 } 1351 break; 1352 default: 1353 DRM_ERROR("unknown voltage object table\n"); 1354 return false; 1355 } 1356 1357 } 1358 return false; 1359 } 1360 1361 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, 1362 u8 voltage_type, u8 voltage_mode, 1363 struct atom_voltage_table *voltage_table) 1364 { 1365 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1366 u8 frev, crev; 1367 u16 data_offset, size; 1368 int i; 1369 union voltage_object_info *voltage_info; 1370 union voltage_object *voltage_object = NULL; 1371 1372 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1373 &frev, &crev, &data_offset)) { 1374 voltage_info = (union voltage_object_info *) 1375 (adev->mode_info.atom_context->bios + data_offset); 1376 1377 switch (frev) { 1378 case 3: 1379 switch (crev) { 1380 case 1: 1381 voltage_object = (union voltage_object *) 1382 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1383 voltage_type, voltage_mode); 1384 if (voltage_object) { 1385 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 1386 &voltage_object->v3.asGpioVoltageObj; 1387 VOLTAGE_LUT_ENTRY_V2 *lut; 1388 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 1389 return -EINVAL; 1390 lut = &gpio->asVolGpioLut[0]; 1391 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 1392 voltage_table->entries[i].value = 1393 le16_to_cpu(lut->usVoltageValue); 1394 voltage_table->entries[i].smio_low = 1395 le32_to_cpu(lut->ulVoltageId); 1396 lut = (VOLTAGE_LUT_ENTRY_V2 *) 1397 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 1398 } 1399 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 1400 voltage_table->count = gpio->ucGpioEntryNum; 1401 voltage_table->phase_delay = gpio->ucPhaseDelay; 1402 return 0; 1403 } 1404 break; 1405 default: 1406 DRM_ERROR("unknown voltage object table\n"); 1407 return -EINVAL; 1408 } 1409 break; 1410 default: 1411 DRM_ERROR("unknown voltage object table\n"); 1412 return -EINVAL; 1413 } 1414 } 1415 return -EINVAL; 1416 } 1417 1418 union vram_info { 1419 struct _ATOM_VRAM_INFO_V3 v1_3; 1420 struct _ATOM_VRAM_INFO_V4 v1_4; 1421 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 1422 }; 1423 1424 #define MEM_ID_MASK 0xff000000 1425 #define MEM_ID_SHIFT 24 1426 #define CLOCK_RANGE_MASK 0x00ffffff 1427 #define CLOCK_RANGE_SHIFT 0 1428 #define LOW_NIBBLE_MASK 0xf 1429 #define DATA_EQU_PREV 0 1430 #define DATA_FROM_TABLE 4 1431 1432 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, 1433 u8 module_index, 1434 struct atom_mc_reg_table *reg_table) 1435 { 1436 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 1437 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 1438 u32 i = 0, j; 1439 u16 data_offset, size; 1440 union vram_info *vram_info; 1441 1442 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 1443 1444 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1445 &frev, &crev, &data_offset)) { 1446 vram_info = (union vram_info *) 1447 (adev->mode_info.atom_context->bios + data_offset); 1448 switch (frev) { 1449 case 1: 1450 DRM_ERROR("old table version %d, %d\n", frev, crev); 1451 return -EINVAL; 1452 case 2: 1453 switch (crev) { 1454 case 1: 1455 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 1456 ATOM_INIT_REG_BLOCK *reg_block = 1457 (ATOM_INIT_REG_BLOCK *) 1458 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 1459 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 1460 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1461 ((u8 *)reg_block + (2 * sizeof(u16)) + 1462 le16_to_cpu(reg_block->usRegIndexTblSize)); 1463 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 1464 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 1465 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 1466 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 1467 return -EINVAL; 1468 while (i < num_entries) { 1469 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 1470 break; 1471 reg_table->mc_reg_address[i].s1 = 1472 (u16)(le16_to_cpu(format->usRegIndex)); 1473 reg_table->mc_reg_address[i].pre_reg_data = 1474 (u8)(format->ucPreRegDataLength); 1475 i++; 1476 format = (ATOM_INIT_REG_INDEX_FORMAT *) 1477 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 1478 } 1479 reg_table->last = i; 1480 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1481 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 1482 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1483 >> MEM_ID_SHIFT); 1484 if (module_index == t_mem_id) { 1485 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 1486 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1487 >> CLOCK_RANGE_SHIFT); 1488 for (i = 0, j = 1; i < reg_table->last; i++) { 1489 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 1490 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1491 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1492 j++; 1493 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 1494 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1495 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 1496 } 1497 } 1498 num_ranges++; 1499 } 1500 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1501 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1502 } 1503 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 1504 return -EINVAL; 1505 reg_table->num_entries = num_ranges; 1506 } else 1507 return -EINVAL; 1508 break; 1509 default: 1510 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1511 return -EINVAL; 1512 } 1513 break; 1514 default: 1515 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1516 return -EINVAL; 1517 } 1518 return 0; 1519 } 1520 return -EINVAL; 1521 } 1522 1523 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) 1524 { 1525 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); 1526 u8 frev, crev; 1527 u16 data_offset, size; 1528 1529 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1530 &frev, &crev, &data_offset)) 1531 return true; 1532 1533 return false; 1534 } 1535 1536 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) 1537 { 1538 uint32_t bios_6_scratch; 1539 1540 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1541 1542 if (lock) { 1543 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1544 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 1545 } else { 1546 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1547 bios_6_scratch |= ATOM_S6_ACC_MODE; 1548 } 1549 1550 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1551 } 1552 1553 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) 1554 { 1555 uint32_t bios_2_scratch, bios_6_scratch; 1556 1557 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); 1558 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1559 1560 /* let the bios control the backlight */ 1561 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1562 1563 /* tell the bios not to handle mode switching */ 1564 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 1565 1566 /* clear the vbios dpms state */ 1567 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 1568 1569 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); 1570 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1571 } 1572 1573 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) 1574 { 1575 int i; 1576 1577 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1578 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); 1579 } 1580 1581 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) 1582 { 1583 int i; 1584 1585 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1586 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); 1587 } 1588 1589 /* Atom needs data in little endian format 1590 * so swap as appropriate when copying data to 1591 * or from atom. Note that atom operates on 1592 * dw units. 1593 */ 1594 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 1595 { 1596 #ifdef __BIG_ENDIAN 1597 u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */ 1598 u32 *dst32, *src32; 1599 int i; 1600 1601 memcpy(src_tmp, src, num_bytes); 1602 src32 = (u32 *)src_tmp; 1603 dst32 = (u32 *)dst_tmp; 1604 if (to_le) { 1605 for (i = 0; i < ((num_bytes + 3) / 4); i++) 1606 dst32[i] = cpu_to_le32(src32[i]); 1607 memcpy(dst, dst_tmp, num_bytes); 1608 } else { 1609 u8 dws = num_bytes & ~3; 1610 for (i = 0; i < ((num_bytes + 3) / 4); i++) 1611 dst32[i] = le32_to_cpu(src32[i]); 1612 memcpy(dst, dst_tmp, dws); 1613 if (num_bytes % 4) { 1614 for (i = 0; i < (num_bytes % 4); i++) 1615 dst[dws+i] = dst_tmp[dws+i]; 1616 } 1617 } 1618 #else 1619 memcpy(dst, src, num_bytes); 1620 #endif 1621 } 1622