1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014-2018 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <linux/dma-buf.h> 24 #include <linux/list.h> 25 #include <linux/pagemap.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/task.h> 28 29 #include "amdgpu_object.h" 30 #include "amdgpu_gem.h" 31 #include "amdgpu_vm.h" 32 #include "amdgpu_hmm.h" 33 #include "amdgpu_amdkfd.h" 34 #include "amdgpu_dma_buf.h" 35 #include <uapi/linux/kfd_ioctl.h> 36 #include "amdgpu_xgmi.h" 37 #include "kfd_smi_events.h" 38 39 /* Userptr restore delay, just long enough to allow consecutive VM 40 * changes to accumulate 41 */ 42 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1 43 44 /* 45 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB 46 * BO chunk 47 */ 48 #define VRAM_AVAILABLITY_ALIGN (1 << 21) 49 50 /* Impose limit on how much memory KFD can use */ 51 static struct { 52 uint64_t max_system_mem_limit; 53 uint64_t max_ttm_mem_limit; 54 int64_t system_mem_used; 55 int64_t ttm_mem_used; 56 spinlock_t mem_limit_lock; 57 } kfd_mem_limit; 58 59 static const char * const domain_bit_to_string[] = { 60 "CPU", 61 "GTT", 62 "VRAM", 63 "GDS", 64 "GWS", 65 "OA" 66 }; 67 68 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1] 69 70 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work); 71 72 static bool kfd_mem_is_attached(struct amdgpu_vm *avm, 73 struct kgd_mem *mem) 74 { 75 struct kfd_mem_attachment *entry; 76 77 list_for_each_entry(entry, &mem->attachments, list) 78 if (entry->bo_va->base.vm == avm) 79 return true; 80 81 return false; 82 } 83 84 /* Set memory usage limits. Current, limits are 85 * System (TTM + userptr) memory - 15/16th System RAM 86 * TTM memory - 3/8th System RAM 87 */ 88 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 89 { 90 struct sysinfo si; 91 uint64_t mem; 92 93 si_meminfo(&si); 94 mem = si.freeram - si.freehigh; 95 mem *= si.mem_unit; 96 97 spin_lock_init(&kfd_mem_limit.mem_limit_lock); 98 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4); 99 kfd_mem_limit.max_ttm_mem_limit = (mem >> 1) - (mem >> 3); 100 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n", 101 (kfd_mem_limit.max_system_mem_limit >> 20), 102 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 103 } 104 105 void amdgpu_amdkfd_reserve_system_mem(uint64_t size) 106 { 107 kfd_mem_limit.system_mem_used += size; 108 } 109 110 /* Estimate page table size needed to represent a given memory size 111 * 112 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory 113 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB 114 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize 115 * for 2MB pages for TLB efficiency. However, small allocations and 116 * fragmented system memory still need some 4KB pages. We choose a 117 * compromise that should work in most cases without reserving too 118 * much memory for page tables unnecessarily (factor 16K, >> 14). 119 */ 120 121 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM) 122 123 /** 124 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size 125 * of buffer. 126 * 127 * @adev: Device to which allocated BO belongs to 128 * @size: Size of buffer, in bytes, encapsulated by B0. This should be 129 * equivalent to amdgpu_bo_size(BO) 130 * @alloc_flag: Flag used in allocating a BO as noted above 131 * 132 * Return: returns -ENOMEM in case of error, ZERO otherwise 133 */ 134 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 135 uint64_t size, u32 alloc_flag) 136 { 137 uint64_t reserved_for_pt = 138 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 139 size_t system_mem_needed, ttm_mem_needed, vram_needed; 140 int ret = 0; 141 142 system_mem_needed = 0; 143 ttm_mem_needed = 0; 144 vram_needed = 0; 145 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 146 system_mem_needed = size; 147 ttm_mem_needed = size; 148 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 149 /* 150 * Conservatively round up the allocation requirement to 2 MB 151 * to avoid fragmentation caused by 4K allocations in the tail 152 * 2M BO chunk. 153 */ 154 vram_needed = size; 155 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 156 system_mem_needed = size; 157 } else if (!(alloc_flag & 158 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 159 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 160 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 161 return -ENOMEM; 162 } 163 164 spin_lock(&kfd_mem_limit.mem_limit_lock); 165 166 if (kfd_mem_limit.system_mem_used + system_mem_needed > 167 kfd_mem_limit.max_system_mem_limit) 168 pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); 169 170 if ((kfd_mem_limit.system_mem_used + system_mem_needed > 171 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) || 172 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 173 kfd_mem_limit.max_ttm_mem_limit) || 174 (adev && adev->kfd.vram_used + vram_needed > 175 adev->gmc.real_vram_size - reserved_for_pt)) { 176 ret = -ENOMEM; 177 goto release; 178 } 179 180 /* Update memory accounting by decreasing available system 181 * memory, TTM memory and GPU memory as computed above 182 */ 183 WARN_ONCE(vram_needed && !adev, 184 "adev reference can't be null when vram is used"); 185 if (adev) { 186 adev->kfd.vram_used += vram_needed; 187 adev->kfd.vram_used_aligned += ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN); 188 } 189 kfd_mem_limit.system_mem_used += system_mem_needed; 190 kfd_mem_limit.ttm_mem_used += ttm_mem_needed; 191 192 release: 193 spin_unlock(&kfd_mem_limit.mem_limit_lock); 194 return ret; 195 } 196 197 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 198 uint64_t size, u32 alloc_flag) 199 { 200 spin_lock(&kfd_mem_limit.mem_limit_lock); 201 202 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 203 kfd_mem_limit.system_mem_used -= size; 204 kfd_mem_limit.ttm_mem_used -= size; 205 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 206 WARN_ONCE(!adev, 207 "adev reference can't be null when alloc mem flags vram is set"); 208 if (adev) { 209 adev->kfd.vram_used -= size; 210 adev->kfd.vram_used_aligned -= ALIGN(size, VRAM_AVAILABLITY_ALIGN); 211 } 212 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 213 kfd_mem_limit.system_mem_used -= size; 214 } else if (!(alloc_flag & 215 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 216 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 217 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 218 goto release; 219 } 220 WARN_ONCE(adev && adev->kfd.vram_used < 0, 221 "KFD VRAM memory accounting unbalanced"); 222 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0, 223 "KFD TTM memory accounting unbalanced"); 224 WARN_ONCE(kfd_mem_limit.system_mem_used < 0, 225 "KFD system memory accounting unbalanced"); 226 227 release: 228 spin_unlock(&kfd_mem_limit.mem_limit_lock); 229 } 230 231 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 232 { 233 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 234 u32 alloc_flags = bo->kfd_bo->alloc_flags; 235 u64 size = amdgpu_bo_size(bo); 236 237 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags); 238 239 kfree(bo->kfd_bo); 240 } 241 242 /** 243 * @create_dmamap_sg_bo: Creates a amdgpu_bo object to reflect information 244 * about USERPTR or DOOREBELL or MMIO BO. 245 * @adev: Device for which dmamap BO is being created 246 * @mem: BO of peer device that is being DMA mapped. Provides parameters 247 * in building the dmamap BO 248 * @bo_out: Output parameter updated with handle of dmamap BO 249 */ 250 static int 251 create_dmamap_sg_bo(struct amdgpu_device *adev, 252 struct kgd_mem *mem, struct amdgpu_bo **bo_out) 253 { 254 struct drm_gem_object *gem_obj; 255 int ret, align; 256 257 ret = amdgpu_bo_reserve(mem->bo, false); 258 if (ret) 259 return ret; 260 261 align = 1; 262 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, align, 263 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE, 264 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj); 265 266 amdgpu_bo_unreserve(mem->bo); 267 268 if (ret) { 269 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret); 270 return -EINVAL; 271 } 272 273 *bo_out = gem_to_amdgpu_bo(gem_obj); 274 (*bo_out)->parent = amdgpu_bo_ref(mem->bo); 275 return ret; 276 } 277 278 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's 279 * reservation object. 280 * 281 * @bo: [IN] Remove eviction fence(s) from this BO 282 * @ef: [IN] This eviction fence is removed if it 283 * is present in the shared list. 284 * 285 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held. 286 */ 287 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, 288 struct amdgpu_amdkfd_fence *ef) 289 { 290 struct dma_fence *replacement; 291 292 if (!ef) 293 return -EINVAL; 294 295 /* TODO: Instead of block before we should use the fence of the page 296 * table update and TLB flush here directly. 297 */ 298 replacement = dma_fence_get_stub(); 299 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, 300 replacement, DMA_RESV_USAGE_BOOKKEEP); 301 dma_fence_put(replacement); 302 return 0; 303 } 304 305 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 306 { 307 struct amdgpu_bo *root = bo; 308 struct amdgpu_vm_bo_base *vm_bo; 309 struct amdgpu_vm *vm; 310 struct amdkfd_process_info *info; 311 struct amdgpu_amdkfd_fence *ef; 312 int ret; 313 314 /* we can always get vm_bo from root PD bo.*/ 315 while (root->parent) 316 root = root->parent; 317 318 vm_bo = root->vm_bo; 319 if (!vm_bo) 320 return 0; 321 322 vm = vm_bo->vm; 323 if (!vm) 324 return 0; 325 326 info = vm->process_info; 327 if (!info || !info->eviction_fence) 328 return 0; 329 330 ef = container_of(dma_fence_get(&info->eviction_fence->base), 331 struct amdgpu_amdkfd_fence, base); 332 333 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv)); 334 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef); 335 dma_resv_unlock(bo->tbo.base.resv); 336 337 dma_fence_put(&ef->base); 338 return ret; 339 } 340 341 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain, 342 bool wait) 343 { 344 struct ttm_operation_ctx ctx = { false, false }; 345 int ret; 346 347 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm), 348 "Called with userptr BO")) 349 return -EINVAL; 350 351 amdgpu_bo_placement_from_domain(bo, domain); 352 353 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 354 if (ret) 355 goto validate_fail; 356 if (wait) 357 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 358 359 validate_fail: 360 return ret; 361 } 362 363 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) 364 { 365 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false); 366 } 367 368 /* vm_validate_pt_pd_bos - Validate page table and directory BOs 369 * 370 * Page directories are not updated here because huge page handling 371 * during page table updates can invalidate page directory entries 372 * again. Page directories are only updated after updating page 373 * tables. 374 */ 375 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) 376 { 377 struct amdgpu_bo *pd = vm->root.bo; 378 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 379 int ret; 380 381 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL); 382 if (ret) { 383 pr_err("failed to validate PT BOs\n"); 384 return ret; 385 } 386 387 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo); 388 389 return 0; 390 } 391 392 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) 393 { 394 struct amdgpu_bo *pd = vm->root.bo; 395 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 396 int ret; 397 398 ret = amdgpu_vm_update_pdes(adev, vm, false); 399 if (ret) 400 return ret; 401 402 return amdgpu_sync_fence(sync, vm->last_update); 403 } 404 405 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) 406 { 407 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE | 408 AMDGPU_VM_MTYPE_DEFAULT; 409 410 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE) 411 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE; 412 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE) 413 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; 414 415 return amdgpu_gem_va_map_flags(adev, mapping_flags); 416 } 417 418 /** 419 * create_sg_table() - Create an sg_table for a contiguous DMA addr range 420 * @addr: The starting address to point to 421 * @size: Size of memory area in bytes being pointed to 422 * 423 * Allocates an instance of sg_table and initializes it to point to memory 424 * area specified by input parameters. The address used to build is assumed 425 * to be DMA mapped, if needed. 426 * 427 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table 428 * because they are physically contiguous. 429 * 430 * Return: Initialized instance of SG Table or NULL 431 */ 432 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size) 433 { 434 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL); 435 436 if (!sg) 437 return NULL; 438 if (sg_alloc_table(sg, 1, GFP_KERNEL)) { 439 kfree(sg); 440 return NULL; 441 } 442 sg_dma_address(sg->sgl) = addr; 443 sg->sgl->length = size; 444 #ifdef CONFIG_NEED_SG_DMA_LENGTH 445 sg->sgl->dma_length = size; 446 #endif 447 return sg; 448 } 449 450 static int 451 kfd_mem_dmamap_userptr(struct kgd_mem *mem, 452 struct kfd_mem_attachment *attachment) 453 { 454 enum dma_data_direction direction = 455 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 456 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 457 struct ttm_operation_ctx ctx = {.interruptible = true}; 458 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 459 struct amdgpu_device *adev = attachment->adev; 460 struct ttm_tt *src_ttm = mem->bo->tbo.ttm; 461 struct ttm_tt *ttm = bo->tbo.ttm; 462 int ret; 463 464 if (WARN_ON(ttm->num_pages != src_ttm->num_pages)) 465 return -EINVAL; 466 467 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL); 468 if (unlikely(!ttm->sg)) 469 return -ENOMEM; 470 471 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */ 472 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages, 473 ttm->num_pages, 0, 474 (u64)ttm->num_pages << PAGE_SHIFT, 475 GFP_KERNEL); 476 if (unlikely(ret)) 477 goto free_sg; 478 479 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 480 if (unlikely(ret)) 481 goto release_sg; 482 483 drm_prime_sg_to_dma_addr_array(ttm->sg, ttm->dma_address, 484 ttm->num_pages); 485 486 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 487 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 488 if (ret) 489 goto unmap_sg; 490 491 return 0; 492 493 unmap_sg: 494 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 495 release_sg: 496 pr_err("DMA map userptr failed: %d\n", ret); 497 sg_free_table(ttm->sg); 498 free_sg: 499 kfree(ttm->sg); 500 ttm->sg = NULL; 501 return ret; 502 } 503 504 static int 505 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment) 506 { 507 struct ttm_operation_ctx ctx = {.interruptible = true}; 508 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 509 510 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 511 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 512 } 513 514 /** 515 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO 516 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 517 * @attachment: Virtual address attachment of the BO on accessing device 518 * 519 * An access request from the device that owns DOORBELL does not require DMA mapping. 520 * This is because the request doesn't go through PCIe root complex i.e. it instead 521 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL 522 * 523 * In contrast, all access requests for MMIO need to be DMA mapped without regard to 524 * device ownership. This is because access requests for MMIO go through PCIe root 525 * complex. 526 * 527 * This is accomplished in two steps: 528 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used 529 * in updating requesting device's page table 530 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU 531 * accessible. This allows an update of requesting device's page table 532 * with entries associated with DOOREBELL or MMIO memory 533 * 534 * This method is invoked in the following contexts: 535 * - Mapping of DOORBELL or MMIO BO of same or peer device 536 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access 537 * 538 * Return: ZERO if successful, NON-ZERO otherwise 539 */ 540 static int 541 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem, 542 struct kfd_mem_attachment *attachment) 543 { 544 struct ttm_operation_ctx ctx = {.interruptible = true}; 545 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 546 struct amdgpu_device *adev = attachment->adev; 547 struct ttm_tt *ttm = bo->tbo.ttm; 548 enum dma_data_direction dir; 549 dma_addr_t dma_addr; 550 bool mmio; 551 int ret; 552 553 /* Expect SG Table of dmapmap BO to be NULL */ 554 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); 555 if (unlikely(ttm->sg)) { 556 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio); 557 return -EINVAL; 558 } 559 560 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 561 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 562 dma_addr = mem->bo->tbo.sg->sgl->dma_address; 563 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length); 564 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr); 565 dma_addr = dma_map_resource(adev->dev, dma_addr, 566 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 567 ret = dma_mapping_error(adev->dev, dma_addr); 568 if (unlikely(ret)) 569 return ret; 570 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr); 571 572 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length); 573 if (unlikely(!ttm->sg)) { 574 ret = -ENOMEM; 575 goto unmap_sg; 576 } 577 578 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 579 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 580 if (unlikely(ret)) 581 goto free_sg; 582 583 return ret; 584 585 free_sg: 586 sg_free_table(ttm->sg); 587 kfree(ttm->sg); 588 ttm->sg = NULL; 589 unmap_sg: 590 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length, 591 dir, DMA_ATTR_SKIP_CPU_SYNC); 592 return ret; 593 } 594 595 static int 596 kfd_mem_dmamap_attachment(struct kgd_mem *mem, 597 struct kfd_mem_attachment *attachment) 598 { 599 switch (attachment->type) { 600 case KFD_MEM_ATT_SHARED: 601 return 0; 602 case KFD_MEM_ATT_USERPTR: 603 return kfd_mem_dmamap_userptr(mem, attachment); 604 case KFD_MEM_ATT_DMABUF: 605 return kfd_mem_dmamap_dmabuf(attachment); 606 case KFD_MEM_ATT_SG: 607 return kfd_mem_dmamap_sg_bo(mem, attachment); 608 default: 609 WARN_ON_ONCE(1); 610 } 611 return -EINVAL; 612 } 613 614 static void 615 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem, 616 struct kfd_mem_attachment *attachment) 617 { 618 enum dma_data_direction direction = 619 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 620 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 621 struct ttm_operation_ctx ctx = {.interruptible = false}; 622 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 623 struct amdgpu_device *adev = attachment->adev; 624 struct ttm_tt *ttm = bo->tbo.ttm; 625 626 if (unlikely(!ttm->sg)) 627 return; 628 629 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 630 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 631 632 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 633 sg_free_table(ttm->sg); 634 kfree(ttm->sg); 635 ttm->sg = NULL; 636 } 637 638 static void 639 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment) 640 { 641 struct ttm_operation_ctx ctx = {.interruptible = true}; 642 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 643 644 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 645 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 646 } 647 648 /** 649 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO 650 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 651 * @attachment: Virtual address attachment of the BO on accessing device 652 * 653 * The method performs following steps: 654 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible 655 * - Free SG Table that is used to encapsulate DMA mapped memory of 656 * peer device's DOORBELL or MMIO memory 657 * 658 * This method is invoked in the following contexts: 659 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory 660 * Eviction of DOOREBELL or MMIO BO on device having access to its memory 661 * 662 * Return: void 663 */ 664 static void 665 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem, 666 struct kfd_mem_attachment *attachment) 667 { 668 struct ttm_operation_ctx ctx = {.interruptible = true}; 669 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 670 struct amdgpu_device *adev = attachment->adev; 671 struct ttm_tt *ttm = bo->tbo.ttm; 672 enum dma_data_direction dir; 673 674 if (unlikely(!ttm->sg)) { 675 pr_err("SG Table of BO is UNEXPECTEDLY NULL"); 676 return; 677 } 678 679 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 680 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 681 682 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 683 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 684 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address, 685 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 686 sg_free_table(ttm->sg); 687 kfree(ttm->sg); 688 ttm->sg = NULL; 689 bo->tbo.sg = NULL; 690 } 691 692 static void 693 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, 694 struct kfd_mem_attachment *attachment) 695 { 696 switch (attachment->type) { 697 case KFD_MEM_ATT_SHARED: 698 break; 699 case KFD_MEM_ATT_USERPTR: 700 kfd_mem_dmaunmap_userptr(mem, attachment); 701 break; 702 case KFD_MEM_ATT_DMABUF: 703 kfd_mem_dmaunmap_dmabuf(attachment); 704 break; 705 case KFD_MEM_ATT_SG: 706 kfd_mem_dmaunmap_sg_bo(mem, attachment); 707 break; 708 default: 709 WARN_ON_ONCE(1); 710 } 711 } 712 713 static int 714 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, 715 struct amdgpu_bo **bo) 716 { 717 struct drm_gem_object *gobj; 718 int ret; 719 720 if (!mem->dmabuf) { 721 mem->dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 722 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 723 DRM_RDWR : 0); 724 if (IS_ERR(mem->dmabuf)) { 725 ret = PTR_ERR(mem->dmabuf); 726 mem->dmabuf = NULL; 727 return ret; 728 } 729 } 730 731 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); 732 if (IS_ERR(gobj)) 733 return PTR_ERR(gobj); 734 735 *bo = gem_to_amdgpu_bo(gobj); 736 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; 737 738 return 0; 739 } 740 741 /* kfd_mem_attach - Add a BO to a VM 742 * 743 * Everything that needs to bo done only once when a BO is first added 744 * to a VM. It can later be mapped and unmapped many times without 745 * repeating these steps. 746 * 747 * 0. Create BO for DMA mapping, if needed 748 * 1. Allocate and initialize BO VA entry data structure 749 * 2. Add BO to the VM 750 * 3. Determine ASIC-specific PTE flags 751 * 4. Alloc page tables and directories if needed 752 * 4a. Validate new page tables and directories 753 */ 754 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, 755 struct amdgpu_vm *vm, bool is_aql) 756 { 757 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); 758 unsigned long bo_size = mem->bo->tbo.base.size; 759 uint64_t va = mem->va; 760 struct kfd_mem_attachment *attachment[2] = {NULL, NULL}; 761 struct amdgpu_bo *bo[2] = {NULL, NULL}; 762 bool same_hive = false; 763 int i, ret; 764 765 if (!va) { 766 pr_err("Invalid VA when adding BO to VM\n"); 767 return -EINVAL; 768 } 769 770 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices 771 * 772 * The access path of MMIO and DOORBELL BOs of is always over PCIe. 773 * In contrast the access path of VRAM BOs depens upon the type of 774 * link that connects the peer device. Access over PCIe is allowed 775 * if peer device has large BAR. In contrast, access over xGMI is 776 * allowed for both small and large BAR configurations of peer device 777 */ 778 if ((adev != bo_adev) && 779 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) || 780 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || 781 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 782 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) 783 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev); 784 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev)) 785 return -EINVAL; 786 } 787 788 for (i = 0; i <= is_aql; i++) { 789 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL); 790 if (unlikely(!attachment[i])) { 791 ret = -ENOMEM; 792 goto unwind; 793 } 794 795 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, 796 va + bo_size, vm); 797 798 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) || 799 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && adev->ram_is_direct_mapped) || 800 same_hive) { 801 /* Mappings on the local GPU, or VRAM mappings in the 802 * local hive, or userptr mapping IOMMU direct map mode 803 * share the original BO 804 */ 805 attachment[i]->type = KFD_MEM_ATT_SHARED; 806 bo[i] = mem->bo; 807 drm_gem_object_get(&bo[i]->tbo.base); 808 } else if (i > 0) { 809 /* Multiple mappings on the same GPU share the BO */ 810 attachment[i]->type = KFD_MEM_ATT_SHARED; 811 bo[i] = bo[0]; 812 drm_gem_object_get(&bo[i]->tbo.base); 813 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 814 /* Create an SG BO to DMA-map userptrs on other GPUs */ 815 attachment[i]->type = KFD_MEM_ATT_USERPTR; 816 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 817 if (ret) 818 goto unwind; 819 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ 820 } else if (mem->bo->tbo.type == ttm_bo_type_sg) { 821 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || 822 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), 823 "Handing invalid SG BO in ATTACH request"); 824 attachment[i]->type = KFD_MEM_ATT_SG; 825 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 826 if (ret) 827 goto unwind; 828 /* Enable acces to GTT and VRAM BOs of peer devices */ 829 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || 830 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { 831 attachment[i]->type = KFD_MEM_ATT_DMABUF; 832 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); 833 if (ret) 834 goto unwind; 835 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); 836 } else { 837 WARN_ONCE(true, "Handling invalid ATTACH request"); 838 ret = -EINVAL; 839 goto unwind; 840 } 841 842 /* Add BO to VM internal data structures */ 843 ret = amdgpu_bo_reserve(bo[i], false); 844 if (ret) { 845 pr_debug("Unable to reserve BO during memory attach"); 846 goto unwind; 847 } 848 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); 849 amdgpu_bo_unreserve(bo[i]); 850 if (unlikely(!attachment[i]->bo_va)) { 851 ret = -ENOMEM; 852 pr_err("Failed to add BO object to VM. ret == %d\n", 853 ret); 854 goto unwind; 855 } 856 attachment[i]->va = va; 857 attachment[i]->pte_flags = get_pte_flags(adev, mem); 858 attachment[i]->adev = adev; 859 list_add(&attachment[i]->list, &mem->attachments); 860 861 va += bo_size; 862 } 863 864 return 0; 865 866 unwind: 867 for (; i >= 0; i--) { 868 if (!attachment[i]) 869 continue; 870 if (attachment[i]->bo_va) { 871 amdgpu_bo_reserve(bo[i], true); 872 amdgpu_vm_bo_del(adev, attachment[i]->bo_va); 873 amdgpu_bo_unreserve(bo[i]); 874 list_del(&attachment[i]->list); 875 } 876 if (bo[i]) 877 drm_gem_object_put(&bo[i]->tbo.base); 878 kfree(attachment[i]); 879 } 880 return ret; 881 } 882 883 static void kfd_mem_detach(struct kfd_mem_attachment *attachment) 884 { 885 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 886 887 pr_debug("\t remove VA 0x%llx in entry %p\n", 888 attachment->va, attachment); 889 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va); 890 drm_gem_object_put(&bo->tbo.base); 891 list_del(&attachment->list); 892 kfree(attachment); 893 } 894 895 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem, 896 struct amdkfd_process_info *process_info, 897 bool userptr) 898 { 899 struct ttm_validate_buffer *entry = &mem->validate_list; 900 struct amdgpu_bo *bo = mem->bo; 901 902 INIT_LIST_HEAD(&entry->head); 903 entry->num_shared = 1; 904 entry->bo = &bo->tbo; 905 mutex_lock(&process_info->lock); 906 if (userptr) 907 list_add_tail(&entry->head, &process_info->userptr_valid_list); 908 else 909 list_add_tail(&entry->head, &process_info->kfd_bo_list); 910 mutex_unlock(&process_info->lock); 911 } 912 913 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem, 914 struct amdkfd_process_info *process_info) 915 { 916 struct ttm_validate_buffer *bo_list_entry; 917 918 bo_list_entry = &mem->validate_list; 919 mutex_lock(&process_info->lock); 920 list_del(&bo_list_entry->head); 921 mutex_unlock(&process_info->lock); 922 } 923 924 /* Initializes user pages. It registers the MMU notifier and validates 925 * the userptr BO in the GTT domain. 926 * 927 * The BO must already be on the userptr_valid_list. Otherwise an 928 * eviction and restore may happen that leaves the new BO unmapped 929 * with the user mode queues running. 930 * 931 * Takes the process_info->lock to protect against concurrent restore 932 * workers. 933 * 934 * Returns 0 for success, negative errno for errors. 935 */ 936 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, 937 bool criu_resume) 938 { 939 struct amdkfd_process_info *process_info = mem->process_info; 940 struct amdgpu_bo *bo = mem->bo; 941 struct ttm_operation_ctx ctx = { true, false }; 942 struct hmm_range *range; 943 int ret = 0; 944 945 mutex_lock(&process_info->lock); 946 947 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0); 948 if (ret) { 949 pr_err("%s: Failed to set userptr: %d\n", __func__, ret); 950 goto out; 951 } 952 953 ret = amdgpu_hmm_register(bo, user_addr); 954 if (ret) { 955 pr_err("%s: Failed to register MMU notifier: %d\n", 956 __func__, ret); 957 goto out; 958 } 959 960 if (criu_resume) { 961 /* 962 * During a CRIU restore operation, the userptr buffer objects 963 * will be validated in the restore_userptr_work worker at a 964 * later stage when it is scheduled by another ioctl called by 965 * CRIU master process for the target pid for restore. 966 */ 967 atomic_inc(&mem->invalid); 968 mutex_unlock(&process_info->lock); 969 return 0; 970 } 971 972 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); 973 if (ret) { 974 pr_err("%s: Failed to get user pages: %d\n", __func__, ret); 975 goto unregister_out; 976 } 977 978 ret = amdgpu_bo_reserve(bo, true); 979 if (ret) { 980 pr_err("%s: Failed to reserve BO\n", __func__); 981 goto release_out; 982 } 983 amdgpu_bo_placement_from_domain(bo, mem->domain); 984 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 985 if (ret) 986 pr_err("%s: failed to validate BO\n", __func__); 987 amdgpu_bo_unreserve(bo); 988 989 release_out: 990 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 991 unregister_out: 992 if (ret) 993 amdgpu_hmm_unregister(bo); 994 out: 995 mutex_unlock(&process_info->lock); 996 return ret; 997 } 998 999 /* Reserving a BO and its page table BOs must happen atomically to 1000 * avoid deadlocks. Some operations update multiple VMs at once. Track 1001 * all the reservation info in a context structure. Optionally a sync 1002 * object can track VM updates. 1003 */ 1004 struct bo_vm_reservation_context { 1005 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */ 1006 unsigned int n_vms; /* Number of VMs reserved */ 1007 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */ 1008 struct ww_acquire_ctx ticket; /* Reservation ticket */ 1009 struct list_head list, duplicates; /* BO lists */ 1010 struct amdgpu_sync *sync; /* Pointer to sync object */ 1011 bool reserved; /* Whether BOs are reserved */ 1012 }; 1013 1014 enum bo_vm_match { 1015 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */ 1016 BO_VM_MAPPED, /* Match VMs where a BO is mapped */ 1017 BO_VM_ALL, /* Match all VMs a BO was added to */ 1018 }; 1019 1020 /** 1021 * reserve_bo_and_vm - reserve a BO and a VM unconditionally. 1022 * @mem: KFD BO structure. 1023 * @vm: the VM to reserve. 1024 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1025 */ 1026 static int reserve_bo_and_vm(struct kgd_mem *mem, 1027 struct amdgpu_vm *vm, 1028 struct bo_vm_reservation_context *ctx) 1029 { 1030 struct amdgpu_bo *bo = mem->bo; 1031 int ret; 1032 1033 WARN_ON(!vm); 1034 1035 ctx->reserved = false; 1036 ctx->n_vms = 1; 1037 ctx->sync = &mem->sync; 1038 1039 INIT_LIST_HEAD(&ctx->list); 1040 INIT_LIST_HEAD(&ctx->duplicates); 1041 1042 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL); 1043 if (!ctx->vm_pd) 1044 return -ENOMEM; 1045 1046 ctx->kfd_bo.priority = 0; 1047 ctx->kfd_bo.tv.bo = &bo->tbo; 1048 ctx->kfd_bo.tv.num_shared = 1; 1049 list_add(&ctx->kfd_bo.tv.head, &ctx->list); 1050 1051 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]); 1052 1053 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list, 1054 false, &ctx->duplicates); 1055 if (ret) { 1056 pr_err("Failed to reserve buffers in ttm.\n"); 1057 kfree(ctx->vm_pd); 1058 ctx->vm_pd = NULL; 1059 return ret; 1060 } 1061 1062 ctx->reserved = true; 1063 return 0; 1064 } 1065 1066 /** 1067 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally 1068 * @mem: KFD BO structure. 1069 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO 1070 * is used. Otherwise, a single VM associated with the BO. 1071 * @map_type: the mapping status that will be used to filter the VMs. 1072 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1073 * 1074 * Returns 0 for success, negative for failure. 1075 */ 1076 static int reserve_bo_and_cond_vms(struct kgd_mem *mem, 1077 struct amdgpu_vm *vm, enum bo_vm_match map_type, 1078 struct bo_vm_reservation_context *ctx) 1079 { 1080 struct amdgpu_bo *bo = mem->bo; 1081 struct kfd_mem_attachment *entry; 1082 unsigned int i; 1083 int ret; 1084 1085 ctx->reserved = false; 1086 ctx->n_vms = 0; 1087 ctx->vm_pd = NULL; 1088 ctx->sync = &mem->sync; 1089 1090 INIT_LIST_HEAD(&ctx->list); 1091 INIT_LIST_HEAD(&ctx->duplicates); 1092 1093 list_for_each_entry(entry, &mem->attachments, list) { 1094 if ((vm && vm != entry->bo_va->base.vm) || 1095 (entry->is_mapped != map_type 1096 && map_type != BO_VM_ALL)) 1097 continue; 1098 1099 ctx->n_vms++; 1100 } 1101 1102 if (ctx->n_vms != 0) { 1103 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), 1104 GFP_KERNEL); 1105 if (!ctx->vm_pd) 1106 return -ENOMEM; 1107 } 1108 1109 ctx->kfd_bo.priority = 0; 1110 ctx->kfd_bo.tv.bo = &bo->tbo; 1111 ctx->kfd_bo.tv.num_shared = 1; 1112 list_add(&ctx->kfd_bo.tv.head, &ctx->list); 1113 1114 i = 0; 1115 list_for_each_entry(entry, &mem->attachments, list) { 1116 if ((vm && vm != entry->bo_va->base.vm) || 1117 (entry->is_mapped != map_type 1118 && map_type != BO_VM_ALL)) 1119 continue; 1120 1121 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list, 1122 &ctx->vm_pd[i]); 1123 i++; 1124 } 1125 1126 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list, 1127 false, &ctx->duplicates); 1128 if (ret) { 1129 pr_err("Failed to reserve buffers in ttm.\n"); 1130 kfree(ctx->vm_pd); 1131 ctx->vm_pd = NULL; 1132 return ret; 1133 } 1134 1135 ctx->reserved = true; 1136 return 0; 1137 } 1138 1139 /** 1140 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context 1141 * @ctx: Reservation context to unreserve 1142 * @wait: Optionally wait for a sync object representing pending VM updates 1143 * @intr: Whether the wait is interruptible 1144 * 1145 * Also frees any resources allocated in 1146 * reserve_bo_and_(cond_)vm(s). Returns the status from 1147 * amdgpu_sync_wait. 1148 */ 1149 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx, 1150 bool wait, bool intr) 1151 { 1152 int ret = 0; 1153 1154 if (wait) 1155 ret = amdgpu_sync_wait(ctx->sync, intr); 1156 1157 if (ctx->reserved) 1158 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list); 1159 kfree(ctx->vm_pd); 1160 1161 ctx->sync = NULL; 1162 1163 ctx->reserved = false; 1164 ctx->vm_pd = NULL; 1165 1166 return ret; 1167 } 1168 1169 static void unmap_bo_from_gpuvm(struct kgd_mem *mem, 1170 struct kfd_mem_attachment *entry, 1171 struct amdgpu_sync *sync) 1172 { 1173 struct amdgpu_bo_va *bo_va = entry->bo_va; 1174 struct amdgpu_device *adev = entry->adev; 1175 struct amdgpu_vm *vm = bo_va->base.vm; 1176 1177 amdgpu_vm_bo_unmap(adev, bo_va, entry->va); 1178 1179 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); 1180 1181 amdgpu_sync_fence(sync, bo_va->last_pt_update); 1182 1183 kfd_mem_dmaunmap_attachment(mem, entry); 1184 } 1185 1186 static int update_gpuvm_pte(struct kgd_mem *mem, 1187 struct kfd_mem_attachment *entry, 1188 struct amdgpu_sync *sync) 1189 { 1190 struct amdgpu_bo_va *bo_va = entry->bo_va; 1191 struct amdgpu_device *adev = entry->adev; 1192 int ret; 1193 1194 ret = kfd_mem_dmamap_attachment(mem, entry); 1195 if (ret) 1196 return ret; 1197 1198 /* Update the page tables */ 1199 ret = amdgpu_vm_bo_update(adev, bo_va, false); 1200 if (ret) { 1201 pr_err("amdgpu_vm_bo_update failed\n"); 1202 return ret; 1203 } 1204 1205 return amdgpu_sync_fence(sync, bo_va->last_pt_update); 1206 } 1207 1208 static int map_bo_to_gpuvm(struct kgd_mem *mem, 1209 struct kfd_mem_attachment *entry, 1210 struct amdgpu_sync *sync, 1211 bool no_update_pte) 1212 { 1213 int ret; 1214 1215 /* Set virtual address for the allocation */ 1216 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0, 1217 amdgpu_bo_size(entry->bo_va->base.bo), 1218 entry->pte_flags); 1219 if (ret) { 1220 pr_err("Failed to map VA 0x%llx in vm. ret %d\n", 1221 entry->va, ret); 1222 return ret; 1223 } 1224 1225 if (no_update_pte) 1226 return 0; 1227 1228 ret = update_gpuvm_pte(mem, entry, sync); 1229 if (ret) { 1230 pr_err("update_gpuvm_pte() failed\n"); 1231 goto update_gpuvm_pte_failed; 1232 } 1233 1234 return 0; 1235 1236 update_gpuvm_pte_failed: 1237 unmap_bo_from_gpuvm(mem, entry, sync); 1238 return ret; 1239 } 1240 1241 static int process_validate_vms(struct amdkfd_process_info *process_info) 1242 { 1243 struct amdgpu_vm *peer_vm; 1244 int ret; 1245 1246 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1247 vm_list_node) { 1248 ret = vm_validate_pt_pd_bos(peer_vm); 1249 if (ret) 1250 return ret; 1251 } 1252 1253 return 0; 1254 } 1255 1256 static int process_sync_pds_resv(struct amdkfd_process_info *process_info, 1257 struct amdgpu_sync *sync) 1258 { 1259 struct amdgpu_vm *peer_vm; 1260 int ret; 1261 1262 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1263 vm_list_node) { 1264 struct amdgpu_bo *pd = peer_vm->root.bo; 1265 1266 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, 1267 AMDGPU_SYNC_NE_OWNER, 1268 AMDGPU_FENCE_OWNER_KFD); 1269 if (ret) 1270 return ret; 1271 } 1272 1273 return 0; 1274 } 1275 1276 static int process_update_pds(struct amdkfd_process_info *process_info, 1277 struct amdgpu_sync *sync) 1278 { 1279 struct amdgpu_vm *peer_vm; 1280 int ret; 1281 1282 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1283 vm_list_node) { 1284 ret = vm_update_pds(peer_vm, sync); 1285 if (ret) 1286 return ret; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 1293 struct dma_fence **ef) 1294 { 1295 struct amdkfd_process_info *info = NULL; 1296 int ret; 1297 1298 if (!*process_info) { 1299 info = kzalloc(sizeof(*info), GFP_KERNEL); 1300 if (!info) 1301 return -ENOMEM; 1302 1303 mutex_init(&info->lock); 1304 INIT_LIST_HEAD(&info->vm_list_head); 1305 INIT_LIST_HEAD(&info->kfd_bo_list); 1306 INIT_LIST_HEAD(&info->userptr_valid_list); 1307 INIT_LIST_HEAD(&info->userptr_inval_list); 1308 1309 info->eviction_fence = 1310 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), 1311 current->mm, 1312 NULL); 1313 if (!info->eviction_fence) { 1314 pr_err("Failed to create eviction fence\n"); 1315 ret = -ENOMEM; 1316 goto create_evict_fence_fail; 1317 } 1318 1319 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID); 1320 atomic_set(&info->evicted_bos, 0); 1321 INIT_DELAYED_WORK(&info->restore_userptr_work, 1322 amdgpu_amdkfd_restore_userptr_worker); 1323 1324 *process_info = info; 1325 *ef = dma_fence_get(&info->eviction_fence->base); 1326 } 1327 1328 vm->process_info = *process_info; 1329 1330 /* Validate page directory and attach eviction fence */ 1331 ret = amdgpu_bo_reserve(vm->root.bo, true); 1332 if (ret) 1333 goto reserve_pd_fail; 1334 ret = vm_validate_pt_pd_bos(vm); 1335 if (ret) { 1336 pr_err("validate_pt_pd_bos() failed\n"); 1337 goto validate_pd_fail; 1338 } 1339 ret = amdgpu_bo_sync_wait(vm->root.bo, 1340 AMDGPU_FENCE_OWNER_KFD, false); 1341 if (ret) 1342 goto wait_pd_fail; 1343 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); 1344 if (ret) 1345 goto reserve_shared_fail; 1346 dma_resv_add_fence(vm->root.bo->tbo.base.resv, 1347 &vm->process_info->eviction_fence->base, 1348 DMA_RESV_USAGE_BOOKKEEP); 1349 amdgpu_bo_unreserve(vm->root.bo); 1350 1351 /* Update process info */ 1352 mutex_lock(&vm->process_info->lock); 1353 list_add_tail(&vm->vm_list_node, 1354 &(vm->process_info->vm_list_head)); 1355 vm->process_info->n_vms++; 1356 mutex_unlock(&vm->process_info->lock); 1357 1358 return 0; 1359 1360 reserve_shared_fail: 1361 wait_pd_fail: 1362 validate_pd_fail: 1363 amdgpu_bo_unreserve(vm->root.bo); 1364 reserve_pd_fail: 1365 vm->process_info = NULL; 1366 if (info) { 1367 /* Two fence references: one in info and one in *ef */ 1368 dma_fence_put(&info->eviction_fence->base); 1369 dma_fence_put(*ef); 1370 *ef = NULL; 1371 *process_info = NULL; 1372 put_pid(info->pid); 1373 create_evict_fence_fail: 1374 mutex_destroy(&info->lock); 1375 kfree(info); 1376 } 1377 return ret; 1378 } 1379 1380 /** 1381 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria 1382 * @bo: Handle of buffer object being pinned 1383 * @domain: Domain into which BO should be pinned 1384 * 1385 * - USERPTR BOs are UNPINNABLE and will return error 1386 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1387 * PIN count incremented. It is valid to PIN a BO multiple times 1388 * 1389 * Return: ZERO if successful in pinning, Non-Zero in case of error. 1390 */ 1391 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) 1392 { 1393 int ret = 0; 1394 1395 ret = amdgpu_bo_reserve(bo, false); 1396 if (unlikely(ret)) 1397 return ret; 1398 1399 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1400 if (ret) 1401 pr_err("Error in Pinning BO to domain: %d\n", domain); 1402 1403 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 1404 amdgpu_bo_unreserve(bo); 1405 1406 return ret; 1407 } 1408 1409 /** 1410 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria 1411 * @bo: Handle of buffer object being unpinned 1412 * 1413 * - Is a illegal request for USERPTR BOs and is ignored 1414 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1415 * PIN count decremented. Calls to UNPIN must balance calls to PIN 1416 */ 1417 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) 1418 { 1419 int ret = 0; 1420 1421 ret = amdgpu_bo_reserve(bo, false); 1422 if (unlikely(ret)) 1423 return; 1424 1425 amdgpu_bo_unpin(bo); 1426 amdgpu_bo_unreserve(bo); 1427 } 1428 1429 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 1430 struct file *filp, u32 pasid, 1431 void **process_info, 1432 struct dma_fence **ef) 1433 { 1434 struct amdgpu_fpriv *drv_priv; 1435 struct amdgpu_vm *avm; 1436 int ret; 1437 1438 ret = amdgpu_file_to_fpriv(filp, &drv_priv); 1439 if (ret) 1440 return ret; 1441 avm = &drv_priv->vm; 1442 1443 /* Already a compute VM? */ 1444 if (avm->process_info) 1445 return -EINVAL; 1446 1447 /* Free the original amdgpu allocated pasid, 1448 * will be replaced with kfd allocated pasid. 1449 */ 1450 if (avm->pasid) { 1451 amdgpu_pasid_free(avm->pasid); 1452 amdgpu_vm_set_pasid(adev, avm, 0); 1453 } 1454 1455 /* Convert VM into a compute VM */ 1456 ret = amdgpu_vm_make_compute(adev, avm); 1457 if (ret) 1458 return ret; 1459 1460 ret = amdgpu_vm_set_pasid(adev, avm, pasid); 1461 if (ret) 1462 return ret; 1463 /* Initialize KFD part of the VM and process info */ 1464 ret = init_kfd_vm(avm, process_info, ef); 1465 if (ret) 1466 return ret; 1467 1468 amdgpu_vm_set_task_info(avm); 1469 1470 return 0; 1471 } 1472 1473 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 1474 struct amdgpu_vm *vm) 1475 { 1476 struct amdkfd_process_info *process_info = vm->process_info; 1477 1478 if (!process_info) 1479 return; 1480 1481 /* Update process info */ 1482 mutex_lock(&process_info->lock); 1483 process_info->n_vms--; 1484 list_del(&vm->vm_list_node); 1485 mutex_unlock(&process_info->lock); 1486 1487 vm->process_info = NULL; 1488 1489 /* Release per-process resources when last compute VM is destroyed */ 1490 if (!process_info->n_vms) { 1491 WARN_ON(!list_empty(&process_info->kfd_bo_list)); 1492 WARN_ON(!list_empty(&process_info->userptr_valid_list)); 1493 WARN_ON(!list_empty(&process_info->userptr_inval_list)); 1494 1495 dma_fence_put(&process_info->eviction_fence->base); 1496 cancel_delayed_work_sync(&process_info->restore_userptr_work); 1497 put_pid(process_info->pid); 1498 mutex_destroy(&process_info->lock); 1499 kfree(process_info); 1500 } 1501 } 1502 1503 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 1504 void *drm_priv) 1505 { 1506 struct amdgpu_vm *avm; 1507 1508 if (WARN_ON(!adev || !drm_priv)) 1509 return; 1510 1511 avm = drm_priv_to_vm(drm_priv); 1512 1513 pr_debug("Releasing process vm %p\n", avm); 1514 1515 /* The original pasid of amdgpu vm has already been 1516 * released during making a amdgpu vm to a compute vm 1517 * The current pasid is managed by kfd and will be 1518 * released on kfd process destroy. Set amdgpu pasid 1519 * to 0 to avoid duplicate release. 1520 */ 1521 amdgpu_vm_release_compute(adev, avm); 1522 } 1523 1524 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv) 1525 { 1526 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1527 struct amdgpu_bo *pd = avm->root.bo; 1528 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 1529 1530 if (adev->asic_type < CHIP_VEGA10) 1531 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT; 1532 return avm->pd_phys_addr; 1533 } 1534 1535 void amdgpu_amdkfd_block_mmu_notifications(void *p) 1536 { 1537 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1538 1539 mutex_lock(&pinfo->lock); 1540 WRITE_ONCE(pinfo->block_mmu_notifications, true); 1541 mutex_unlock(&pinfo->lock); 1542 } 1543 1544 int amdgpu_amdkfd_criu_resume(void *p) 1545 { 1546 int ret = 0; 1547 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1548 1549 mutex_lock(&pinfo->lock); 1550 pr_debug("scheduling work\n"); 1551 atomic_inc(&pinfo->evicted_bos); 1552 if (!READ_ONCE(pinfo->block_mmu_notifications)) { 1553 ret = -EINVAL; 1554 goto out_unlock; 1555 } 1556 WRITE_ONCE(pinfo->block_mmu_notifications, false); 1557 schedule_delayed_work(&pinfo->restore_userptr_work, 0); 1558 1559 out_unlock: 1560 mutex_unlock(&pinfo->lock); 1561 return ret; 1562 } 1563 1564 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev) 1565 { 1566 uint64_t reserved_for_pt = 1567 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 1568 size_t available; 1569 1570 spin_lock(&kfd_mem_limit.mem_limit_lock); 1571 available = adev->gmc.real_vram_size 1572 - adev->kfd.vram_used_aligned 1573 - atomic64_read(&adev->vram_pin_size) 1574 - reserved_for_pt; 1575 spin_unlock(&kfd_mem_limit.mem_limit_lock); 1576 1577 return ALIGN_DOWN(available, VRAM_AVAILABLITY_ALIGN); 1578 } 1579 1580 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1581 struct amdgpu_device *adev, uint64_t va, uint64_t size, 1582 void *drm_priv, struct kgd_mem **mem, 1583 uint64_t *offset, uint32_t flags, bool criu_resume) 1584 { 1585 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1586 enum ttm_bo_type bo_type = ttm_bo_type_device; 1587 struct sg_table *sg = NULL; 1588 uint64_t user_addr = 0; 1589 struct amdgpu_bo *bo; 1590 struct drm_gem_object *gobj = NULL; 1591 u32 domain, alloc_domain; 1592 u64 alloc_flags; 1593 int ret; 1594 1595 /* 1596 * Check on which domain to allocate BO 1597 */ 1598 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1599 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; 1600 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 1601 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? 1602 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; 1603 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 1604 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1605 alloc_flags = 0; 1606 } else { 1607 domain = AMDGPU_GEM_DOMAIN_GTT; 1608 alloc_domain = AMDGPU_GEM_DOMAIN_CPU; 1609 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE; 1610 1611 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1612 if (!offset || !*offset) 1613 return -EINVAL; 1614 user_addr = untagged_addr(*offset); 1615 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1616 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1617 bo_type = ttm_bo_type_sg; 1618 if (size > UINT_MAX) 1619 return -EINVAL; 1620 sg = create_sg_table(*offset, size); 1621 if (!sg) 1622 return -ENOMEM; 1623 } else { 1624 return -EINVAL; 1625 } 1626 } 1627 1628 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT) 1629 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT; 1630 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) 1631 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; 1632 1633 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 1634 if (!*mem) { 1635 ret = -ENOMEM; 1636 goto err; 1637 } 1638 INIT_LIST_HEAD(&(*mem)->attachments); 1639 mutex_init(&(*mem)->lock); 1640 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM); 1641 1642 /* Workaround for AQL queue wraparound bug. Map the same 1643 * memory twice. That means we only actually allocate half 1644 * the memory. 1645 */ 1646 if ((*mem)->aql_queue) 1647 size = size >> 1; 1648 1649 (*mem)->alloc_flags = flags; 1650 1651 amdgpu_sync_create(&(*mem)->sync); 1652 1653 ret = amdgpu_amdkfd_reserve_mem_limit(adev, size, flags); 1654 if (ret) { 1655 pr_debug("Insufficient memory\n"); 1656 goto err_reserve_limit; 1657 } 1658 1659 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n", 1660 va, size, domain_string(alloc_domain)); 1661 1662 ret = amdgpu_gem_object_create(adev, size, 1, alloc_domain, alloc_flags, 1663 bo_type, NULL, &gobj); 1664 if (ret) { 1665 pr_debug("Failed to create BO on domain %s. ret %d\n", 1666 domain_string(alloc_domain), ret); 1667 goto err_bo_create; 1668 } 1669 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv); 1670 if (ret) { 1671 pr_debug("Failed to allow vma node access. ret %d\n", ret); 1672 goto err_node_allow; 1673 } 1674 bo = gem_to_amdgpu_bo(gobj); 1675 if (bo_type == ttm_bo_type_sg) { 1676 bo->tbo.sg = sg; 1677 bo->tbo.ttm->sg = sg; 1678 } 1679 bo->kfd_bo = *mem; 1680 (*mem)->bo = bo; 1681 if (user_addr) 1682 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO; 1683 1684 (*mem)->va = va; 1685 (*mem)->domain = domain; 1686 (*mem)->mapped_to_gpu_memory = 0; 1687 (*mem)->process_info = avm->process_info; 1688 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr); 1689 1690 if (user_addr) { 1691 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr); 1692 ret = init_user_pages(*mem, user_addr, criu_resume); 1693 if (ret) 1694 goto allocate_init_user_pages_failed; 1695 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1696 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1697 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); 1698 if (ret) { 1699 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); 1700 goto err_pin_bo; 1701 } 1702 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 1703 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 1704 } 1705 1706 if (offset) 1707 *offset = amdgpu_bo_mmap_offset(bo); 1708 1709 return 0; 1710 1711 allocate_init_user_pages_failed: 1712 err_pin_bo: 1713 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info); 1714 drm_vma_node_revoke(&gobj->vma_node, drm_priv); 1715 err_node_allow: 1716 /* Don't unreserve system mem limit twice */ 1717 goto err_reserve_limit; 1718 err_bo_create: 1719 amdgpu_amdkfd_unreserve_mem_limit(adev, size, flags); 1720 err_reserve_limit: 1721 mutex_destroy(&(*mem)->lock); 1722 if (gobj) 1723 drm_gem_object_put(gobj); 1724 else 1725 kfree(*mem); 1726 err: 1727 if (sg) { 1728 sg_free_table(sg); 1729 kfree(sg); 1730 } 1731 return ret; 1732 } 1733 1734 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 1735 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 1736 uint64_t *size) 1737 { 1738 struct amdkfd_process_info *process_info = mem->process_info; 1739 unsigned long bo_size = mem->bo->tbo.base.size; 1740 bool use_release_notifier = (mem->bo->kfd_bo == mem); 1741 struct kfd_mem_attachment *entry, *tmp; 1742 struct bo_vm_reservation_context ctx; 1743 struct ttm_validate_buffer *bo_list_entry; 1744 unsigned int mapped_to_gpu_memory; 1745 int ret; 1746 bool is_imported = false; 1747 1748 mutex_lock(&mem->lock); 1749 1750 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */ 1751 if (mem->alloc_flags & 1752 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1753 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1754 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo); 1755 } 1756 1757 mapped_to_gpu_memory = mem->mapped_to_gpu_memory; 1758 is_imported = mem->is_imported; 1759 mutex_unlock(&mem->lock); 1760 /* lock is not needed after this, since mem is unused and will 1761 * be freed anyway 1762 */ 1763 1764 if (mapped_to_gpu_memory > 0) { 1765 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n", 1766 mem->va, bo_size); 1767 return -EBUSY; 1768 } 1769 1770 /* Make sure restore workers don't access the BO any more */ 1771 bo_list_entry = &mem->validate_list; 1772 mutex_lock(&process_info->lock); 1773 list_del(&bo_list_entry->head); 1774 mutex_unlock(&process_info->lock); 1775 1776 /* No more MMU notifiers */ 1777 amdgpu_hmm_unregister(mem->bo); 1778 1779 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); 1780 if (unlikely(ret)) 1781 return ret; 1782 1783 /* The eviction fence should be removed by the last unmap. 1784 * TODO: Log an error condition if the bo still has the eviction fence 1785 * attached 1786 */ 1787 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 1788 process_info->eviction_fence); 1789 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va, 1790 mem->va + bo_size * (1 + mem->aql_queue)); 1791 1792 /* Remove from VM internal data structures */ 1793 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) 1794 kfd_mem_detach(entry); 1795 1796 ret = unreserve_bo_and_vms(&ctx, false, false); 1797 1798 /* Free the sync object */ 1799 amdgpu_sync_free(&mem->sync); 1800 1801 /* If the SG is not NULL, it's one we created for a doorbell or mmio 1802 * remap BO. We need to free it. 1803 */ 1804 if (mem->bo->tbo.sg) { 1805 sg_free_table(mem->bo->tbo.sg); 1806 kfree(mem->bo->tbo.sg); 1807 } 1808 1809 /* Update the size of the BO being freed if it was allocated from 1810 * VRAM and is not imported. 1811 */ 1812 if (size) { 1813 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) && 1814 (!is_imported)) 1815 *size = bo_size; 1816 else 1817 *size = 0; 1818 } 1819 1820 /* Free the BO*/ 1821 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); 1822 if (mem->dmabuf) 1823 dma_buf_put(mem->dmabuf); 1824 mutex_destroy(&mem->lock); 1825 1826 /* If this releases the last reference, it will end up calling 1827 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why 1828 * this needs to be the last call here. 1829 */ 1830 drm_gem_object_put(&mem->bo->tbo.base); 1831 1832 /* 1833 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(), 1834 * explicitly free it here. 1835 */ 1836 if (!use_release_notifier) 1837 kfree(mem); 1838 1839 return ret; 1840 } 1841 1842 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1843 struct amdgpu_device *adev, struct kgd_mem *mem, 1844 void *drm_priv) 1845 { 1846 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1847 int ret; 1848 struct amdgpu_bo *bo; 1849 uint32_t domain; 1850 struct kfd_mem_attachment *entry; 1851 struct bo_vm_reservation_context ctx; 1852 unsigned long bo_size; 1853 bool is_invalid_userptr = false; 1854 1855 bo = mem->bo; 1856 if (!bo) { 1857 pr_err("Invalid BO when mapping memory to GPU\n"); 1858 return -EINVAL; 1859 } 1860 1861 /* Make sure restore is not running concurrently. Since we 1862 * don't map invalid userptr BOs, we rely on the next restore 1863 * worker to do the mapping 1864 */ 1865 mutex_lock(&mem->process_info->lock); 1866 1867 mutex_lock(&mem->lock); 1868 1869 domain = mem->domain; 1870 bo_size = bo->tbo.base.size; 1871 1872 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n", 1873 mem->va, 1874 mem->va + bo_size * (1 + mem->aql_queue), 1875 avm, domain_string(domain)); 1876 1877 if (!kfd_mem_is_attached(avm, mem)) { 1878 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue); 1879 if (ret) 1880 goto out; 1881 } 1882 1883 ret = reserve_bo_and_vm(mem, avm, &ctx); 1884 if (unlikely(ret)) 1885 goto out; 1886 1887 /* Userptr can be marked as "not invalid", but not actually be 1888 * validated yet (still in the system domain). In that case 1889 * the queues are still stopped and we can leave mapping for 1890 * the next restore worker 1891 */ 1892 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && 1893 bo->tbo.resource->mem_type == TTM_PL_SYSTEM) 1894 is_invalid_userptr = true; 1895 1896 ret = vm_validate_pt_pd_bos(avm); 1897 if (unlikely(ret)) 1898 goto out_unreserve; 1899 1900 if (mem->mapped_to_gpu_memory == 0 && 1901 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 1902 /* Validate BO only once. The eviction fence gets added to BO 1903 * the first time it is mapped. Validate will wait for all 1904 * background evictions to complete. 1905 */ 1906 ret = amdgpu_amdkfd_bo_validate(bo, domain, true); 1907 if (ret) { 1908 pr_debug("Validate failed\n"); 1909 goto out_unreserve; 1910 } 1911 } 1912 1913 list_for_each_entry(entry, &mem->attachments, list) { 1914 if (entry->bo_va->base.vm != avm || entry->is_mapped) 1915 continue; 1916 1917 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n", 1918 entry->va, entry->va + bo_size, entry); 1919 1920 ret = map_bo_to_gpuvm(mem, entry, ctx.sync, 1921 is_invalid_userptr); 1922 if (ret) { 1923 pr_err("Failed to map bo to gpuvm\n"); 1924 goto out_unreserve; 1925 } 1926 1927 ret = vm_update_pds(avm, ctx.sync); 1928 if (ret) { 1929 pr_err("Failed to update page directories\n"); 1930 goto out_unreserve; 1931 } 1932 1933 entry->is_mapped = true; 1934 mem->mapped_to_gpu_memory++; 1935 pr_debug("\t INC mapping count %d\n", 1936 mem->mapped_to_gpu_memory); 1937 } 1938 1939 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count) 1940 dma_resv_add_fence(bo->tbo.base.resv, 1941 &avm->process_info->eviction_fence->base, 1942 DMA_RESV_USAGE_BOOKKEEP); 1943 ret = unreserve_bo_and_vms(&ctx, false, false); 1944 1945 goto out; 1946 1947 out_unreserve: 1948 unreserve_bo_and_vms(&ctx, false, false); 1949 out: 1950 mutex_unlock(&mem->process_info->lock); 1951 mutex_unlock(&mem->lock); 1952 return ret; 1953 } 1954 1955 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 1956 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv) 1957 { 1958 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1959 struct amdkfd_process_info *process_info = avm->process_info; 1960 unsigned long bo_size = mem->bo->tbo.base.size; 1961 struct kfd_mem_attachment *entry; 1962 struct bo_vm_reservation_context ctx; 1963 int ret; 1964 1965 mutex_lock(&mem->lock); 1966 1967 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx); 1968 if (unlikely(ret)) 1969 goto out; 1970 /* If no VMs were reserved, it means the BO wasn't actually mapped */ 1971 if (ctx.n_vms == 0) { 1972 ret = -EINVAL; 1973 goto unreserve_out; 1974 } 1975 1976 ret = vm_validate_pt_pd_bos(avm); 1977 if (unlikely(ret)) 1978 goto unreserve_out; 1979 1980 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n", 1981 mem->va, 1982 mem->va + bo_size * (1 + mem->aql_queue), 1983 avm); 1984 1985 list_for_each_entry(entry, &mem->attachments, list) { 1986 if (entry->bo_va->base.vm != avm || !entry->is_mapped) 1987 continue; 1988 1989 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n", 1990 entry->va, entry->va + bo_size, entry); 1991 1992 unmap_bo_from_gpuvm(mem, entry, ctx.sync); 1993 entry->is_mapped = false; 1994 1995 mem->mapped_to_gpu_memory--; 1996 pr_debug("\t DEC mapping count %d\n", 1997 mem->mapped_to_gpu_memory); 1998 } 1999 2000 /* If BO is unmapped from all VMs, unfence it. It can be evicted if 2001 * required. 2002 */ 2003 if (mem->mapped_to_gpu_memory == 0 && 2004 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && 2005 !mem->bo->tbo.pin_count) 2006 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 2007 process_info->eviction_fence); 2008 2009 unreserve_out: 2010 unreserve_bo_and_vms(&ctx, false, false); 2011 out: 2012 mutex_unlock(&mem->lock); 2013 return ret; 2014 } 2015 2016 int amdgpu_amdkfd_gpuvm_sync_memory( 2017 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr) 2018 { 2019 struct amdgpu_sync sync; 2020 int ret; 2021 2022 amdgpu_sync_create(&sync); 2023 2024 mutex_lock(&mem->lock); 2025 amdgpu_sync_clone(&mem->sync, &sync); 2026 mutex_unlock(&mem->lock); 2027 2028 ret = amdgpu_sync_wait(&sync, intr); 2029 amdgpu_sync_free(&sync); 2030 return ret; 2031 } 2032 2033 /** 2034 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count 2035 * @adev: Device to which allocated BO belongs 2036 * @bo: Buffer object to be mapped 2037 * 2038 * Before return, bo reference count is incremented. To release the reference and unpin/ 2039 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem. 2040 */ 2041 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo) 2042 { 2043 int ret; 2044 2045 ret = amdgpu_bo_reserve(bo, true); 2046 if (ret) { 2047 pr_err("Failed to reserve bo. ret %d\n", ret); 2048 goto err_reserve_bo_failed; 2049 } 2050 2051 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2052 if (ret) { 2053 pr_err("Failed to pin bo. ret %d\n", ret); 2054 goto err_pin_bo_failed; 2055 } 2056 2057 ret = amdgpu_ttm_alloc_gart(&bo->tbo); 2058 if (ret) { 2059 pr_err("Failed to bind bo to GART. ret %d\n", ret); 2060 goto err_map_bo_gart_failed; 2061 } 2062 2063 amdgpu_amdkfd_remove_eviction_fence( 2064 bo, bo->kfd_bo->process_info->eviction_fence); 2065 2066 amdgpu_bo_unreserve(bo); 2067 2068 bo = amdgpu_bo_ref(bo); 2069 2070 return 0; 2071 2072 err_map_bo_gart_failed: 2073 amdgpu_bo_unpin(bo); 2074 err_pin_bo_failed: 2075 amdgpu_bo_unreserve(bo); 2076 err_reserve_bo_failed: 2077 2078 return ret; 2079 } 2080 2081 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access 2082 * 2083 * @mem: Buffer object to be mapped for CPU access 2084 * @kptr[out]: pointer in kernel CPU address space 2085 * @size[out]: size of the buffer 2086 * 2087 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed 2088 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the 2089 * validate_list, so the GPU mapping can be restored after a page table was 2090 * evicted. 2091 * 2092 * Return: 0 on success, error code on failure 2093 */ 2094 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 2095 void **kptr, uint64_t *size) 2096 { 2097 int ret; 2098 struct amdgpu_bo *bo = mem->bo; 2099 2100 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 2101 pr_err("userptr can't be mapped to kernel\n"); 2102 return -EINVAL; 2103 } 2104 2105 mutex_lock(&mem->process_info->lock); 2106 2107 ret = amdgpu_bo_reserve(bo, true); 2108 if (ret) { 2109 pr_err("Failed to reserve bo. ret %d\n", ret); 2110 goto bo_reserve_failed; 2111 } 2112 2113 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2114 if (ret) { 2115 pr_err("Failed to pin bo. ret %d\n", ret); 2116 goto pin_failed; 2117 } 2118 2119 ret = amdgpu_bo_kmap(bo, kptr); 2120 if (ret) { 2121 pr_err("Failed to map bo to kernel. ret %d\n", ret); 2122 goto kmap_failed; 2123 } 2124 2125 amdgpu_amdkfd_remove_eviction_fence( 2126 bo, mem->process_info->eviction_fence); 2127 2128 if (size) 2129 *size = amdgpu_bo_size(bo); 2130 2131 amdgpu_bo_unreserve(bo); 2132 2133 mutex_unlock(&mem->process_info->lock); 2134 return 0; 2135 2136 kmap_failed: 2137 amdgpu_bo_unpin(bo); 2138 pin_failed: 2139 amdgpu_bo_unreserve(bo); 2140 bo_reserve_failed: 2141 mutex_unlock(&mem->process_info->lock); 2142 2143 return ret; 2144 } 2145 2146 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access 2147 * 2148 * @mem: Buffer object to be unmapped for CPU access 2149 * 2150 * Removes the kernel CPU mapping and unpins the BO. It does not restore the 2151 * eviction fence, so this function should only be used for cleanup before the 2152 * BO is destroyed. 2153 */ 2154 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem) 2155 { 2156 struct amdgpu_bo *bo = mem->bo; 2157 2158 amdgpu_bo_reserve(bo, true); 2159 amdgpu_bo_kunmap(bo); 2160 amdgpu_bo_unpin(bo); 2161 amdgpu_bo_unreserve(bo); 2162 } 2163 2164 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 2165 struct kfd_vm_fault_info *mem) 2166 { 2167 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { 2168 *mem = *adev->gmc.vm_fault_info; 2169 mb(); /* make sure read happened */ 2170 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 2171 } 2172 return 0; 2173 } 2174 2175 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 2176 struct dma_buf *dma_buf, 2177 uint64_t va, void *drm_priv, 2178 struct kgd_mem **mem, uint64_t *size, 2179 uint64_t *mmap_offset) 2180 { 2181 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2182 struct drm_gem_object *obj; 2183 struct amdgpu_bo *bo; 2184 int ret; 2185 2186 if (dma_buf->ops != &amdgpu_dmabuf_ops) 2187 /* Can't handle non-graphics buffers */ 2188 return -EINVAL; 2189 2190 obj = dma_buf->priv; 2191 if (drm_to_adev(obj->dev) != adev) 2192 /* Can't handle buffers from other devices */ 2193 return -EINVAL; 2194 2195 bo = gem_to_amdgpu_bo(obj); 2196 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 2197 AMDGPU_GEM_DOMAIN_GTT))) 2198 /* Only VRAM and GTT BOs are supported */ 2199 return -EINVAL; 2200 2201 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 2202 if (!*mem) 2203 return -ENOMEM; 2204 2205 ret = drm_vma_node_allow(&obj->vma_node, drm_priv); 2206 if (ret) { 2207 kfree(mem); 2208 return ret; 2209 } 2210 2211 if (size) 2212 *size = amdgpu_bo_size(bo); 2213 2214 if (mmap_offset) 2215 *mmap_offset = amdgpu_bo_mmap_offset(bo); 2216 2217 INIT_LIST_HEAD(&(*mem)->attachments); 2218 mutex_init(&(*mem)->lock); 2219 2220 (*mem)->alloc_flags = 2221 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 2222 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) 2223 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE 2224 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; 2225 2226 drm_gem_object_get(&bo->tbo.base); 2227 (*mem)->bo = bo; 2228 (*mem)->va = va; 2229 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 2230 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT; 2231 (*mem)->mapped_to_gpu_memory = 0; 2232 (*mem)->process_info = avm->process_info; 2233 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false); 2234 amdgpu_sync_create(&(*mem)->sync); 2235 (*mem)->is_imported = true; 2236 2237 return 0; 2238 } 2239 2240 /* Evict a userptr BO by stopping the queues if necessary 2241 * 2242 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it 2243 * cannot do any memory allocations, and cannot take any locks that 2244 * are held elsewhere while allocating memory. Therefore this is as 2245 * simple as possible, using atomic counters. 2246 * 2247 * It doesn't do anything to the BO itself. The real work happens in 2248 * restore, where we get updated page addresses. This function only 2249 * ensures that GPU access to the BO is stopped. 2250 */ 2251 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, 2252 struct mm_struct *mm) 2253 { 2254 struct amdkfd_process_info *process_info = mem->process_info; 2255 int evicted_bos; 2256 int r = 0; 2257 2258 /* Do not process MMU notifications until stage-4 IOCTL is received */ 2259 if (READ_ONCE(process_info->block_mmu_notifications)) 2260 return 0; 2261 2262 atomic_inc(&mem->invalid); 2263 evicted_bos = atomic_inc_return(&process_info->evicted_bos); 2264 if (evicted_bos == 1) { 2265 /* First eviction, stop the queues */ 2266 r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); 2267 if (r) 2268 pr_err("Failed to quiesce KFD\n"); 2269 schedule_delayed_work(&process_info->restore_userptr_work, 2270 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2271 } 2272 2273 return r; 2274 } 2275 2276 /* Update invalid userptr BOs 2277 * 2278 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to 2279 * userptr_inval_list and updates user pages for all BOs that have 2280 * been invalidated since their last update. 2281 */ 2282 static int update_invalid_user_pages(struct amdkfd_process_info *process_info, 2283 struct mm_struct *mm) 2284 { 2285 struct kgd_mem *mem, *tmp_mem; 2286 struct amdgpu_bo *bo; 2287 struct ttm_operation_ctx ctx = { false, false }; 2288 int invalid, ret; 2289 2290 /* Move all invalidated BOs to the userptr_inval_list and 2291 * release their user pages by migration to the CPU domain 2292 */ 2293 list_for_each_entry_safe(mem, tmp_mem, 2294 &process_info->userptr_valid_list, 2295 validate_list.head) { 2296 if (!atomic_read(&mem->invalid)) 2297 continue; /* BO is still valid */ 2298 2299 bo = mem->bo; 2300 2301 if (amdgpu_bo_reserve(bo, true)) 2302 return -EAGAIN; 2303 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 2304 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2305 amdgpu_bo_unreserve(bo); 2306 if (ret) { 2307 pr_err("%s: Failed to invalidate userptr BO\n", 2308 __func__); 2309 return -EAGAIN; 2310 } 2311 2312 list_move_tail(&mem->validate_list.head, 2313 &process_info->userptr_inval_list); 2314 } 2315 2316 if (list_empty(&process_info->userptr_inval_list)) 2317 return 0; /* All evicted userptr BOs were freed */ 2318 2319 /* Go through userptr_inval_list and update any invalid user_pages */ 2320 list_for_each_entry(mem, &process_info->userptr_inval_list, 2321 validate_list.head) { 2322 struct hmm_range *range; 2323 2324 invalid = atomic_read(&mem->invalid); 2325 if (!invalid) 2326 /* BO hasn't been invalidated since the last 2327 * revalidation attempt. Keep its BO list. 2328 */ 2329 continue; 2330 2331 bo = mem->bo; 2332 2333 /* Get updated user pages */ 2334 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 2335 &range); 2336 if (ret) { 2337 pr_debug("Failed %d to get user pages\n", ret); 2338 2339 /* Return -EFAULT bad address error as success. It will 2340 * fail later with a VM fault if the GPU tries to access 2341 * it. Better than hanging indefinitely with stalled 2342 * user mode queues. 2343 * 2344 * Return other error -EBUSY or -ENOMEM to retry restore 2345 */ 2346 if (ret != -EFAULT) 2347 return ret; 2348 } else { 2349 2350 /* 2351 * FIXME: Cannot ignore the return code, must hold 2352 * notifier_lock 2353 */ 2354 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 2355 } 2356 2357 /* Mark the BO as valid unless it was invalidated 2358 * again concurrently. 2359 */ 2360 if (atomic_cmpxchg(&mem->invalid, invalid, 0) != invalid) 2361 return -EAGAIN; 2362 } 2363 2364 return 0; 2365 } 2366 2367 /* Validate invalid userptr BOs 2368 * 2369 * Validates BOs on the userptr_inval_list, and moves them back to the 2370 * userptr_valid_list. Also updates GPUVM page tables with new page 2371 * addresses and waits for the page table updates to complete. 2372 */ 2373 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) 2374 { 2375 struct amdgpu_bo_list_entry *pd_bo_list_entries; 2376 struct list_head resv_list, duplicates; 2377 struct ww_acquire_ctx ticket; 2378 struct amdgpu_sync sync; 2379 2380 struct amdgpu_vm *peer_vm; 2381 struct kgd_mem *mem, *tmp_mem; 2382 struct amdgpu_bo *bo; 2383 struct ttm_operation_ctx ctx = { false, false }; 2384 int i, ret; 2385 2386 pd_bo_list_entries = kcalloc(process_info->n_vms, 2387 sizeof(struct amdgpu_bo_list_entry), 2388 GFP_KERNEL); 2389 if (!pd_bo_list_entries) { 2390 pr_err("%s: Failed to allocate PD BO list entries\n", __func__); 2391 ret = -ENOMEM; 2392 goto out_no_mem; 2393 } 2394 2395 INIT_LIST_HEAD(&resv_list); 2396 INIT_LIST_HEAD(&duplicates); 2397 2398 /* Get all the page directory BOs that need to be reserved */ 2399 i = 0; 2400 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2401 vm_list_node) 2402 amdgpu_vm_get_pd_bo(peer_vm, &resv_list, 2403 &pd_bo_list_entries[i++]); 2404 /* Add the userptr_inval_list entries to resv_list */ 2405 list_for_each_entry(mem, &process_info->userptr_inval_list, 2406 validate_list.head) { 2407 list_add_tail(&mem->resv_list.head, &resv_list); 2408 mem->resv_list.bo = mem->validate_list.bo; 2409 mem->resv_list.num_shared = mem->validate_list.num_shared; 2410 } 2411 2412 /* Reserve all BOs and page tables for validation */ 2413 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates); 2414 WARN(!list_empty(&duplicates), "Duplicates should be empty"); 2415 if (ret) 2416 goto out_free; 2417 2418 amdgpu_sync_create(&sync); 2419 2420 ret = process_validate_vms(process_info); 2421 if (ret) 2422 goto unreserve_out; 2423 2424 /* Validate BOs and update GPUVM page tables */ 2425 list_for_each_entry_safe(mem, tmp_mem, 2426 &process_info->userptr_inval_list, 2427 validate_list.head) { 2428 struct kfd_mem_attachment *attachment; 2429 2430 bo = mem->bo; 2431 2432 /* Validate the BO if we got user pages */ 2433 if (bo->tbo.ttm->pages[0]) { 2434 amdgpu_bo_placement_from_domain(bo, mem->domain); 2435 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2436 if (ret) { 2437 pr_err("%s: failed to validate BO\n", __func__); 2438 goto unreserve_out; 2439 } 2440 } 2441 2442 list_move_tail(&mem->validate_list.head, 2443 &process_info->userptr_valid_list); 2444 2445 /* Update mapping. If the BO was not validated 2446 * (because we couldn't get user pages), this will 2447 * clear the page table entries, which will result in 2448 * VM faults if the GPU tries to access the invalid 2449 * memory. 2450 */ 2451 list_for_each_entry(attachment, &mem->attachments, list) { 2452 if (!attachment->is_mapped) 2453 continue; 2454 2455 kfd_mem_dmaunmap_attachment(mem, attachment); 2456 ret = update_gpuvm_pte(mem, attachment, &sync); 2457 if (ret) { 2458 pr_err("%s: update PTE failed\n", __func__); 2459 /* make sure this gets validated again */ 2460 atomic_inc(&mem->invalid); 2461 goto unreserve_out; 2462 } 2463 } 2464 } 2465 2466 /* Update page directories */ 2467 ret = process_update_pds(process_info, &sync); 2468 2469 unreserve_out: 2470 ttm_eu_backoff_reservation(&ticket, &resv_list); 2471 amdgpu_sync_wait(&sync, false); 2472 amdgpu_sync_free(&sync); 2473 out_free: 2474 kfree(pd_bo_list_entries); 2475 out_no_mem: 2476 2477 return ret; 2478 } 2479 2480 /* Worker callback to restore evicted userptr BOs 2481 * 2482 * Tries to update and validate all userptr BOs. If successful and no 2483 * concurrent evictions happened, the queues are restarted. Otherwise, 2484 * reschedule for another attempt later. 2485 */ 2486 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work) 2487 { 2488 struct delayed_work *dwork = to_delayed_work(work); 2489 struct amdkfd_process_info *process_info = 2490 container_of(dwork, struct amdkfd_process_info, 2491 restore_userptr_work); 2492 struct task_struct *usertask; 2493 struct mm_struct *mm; 2494 int evicted_bos; 2495 2496 evicted_bos = atomic_read(&process_info->evicted_bos); 2497 if (!evicted_bos) 2498 return; 2499 2500 /* Reference task and mm in case of concurrent process termination */ 2501 usertask = get_pid_task(process_info->pid, PIDTYPE_PID); 2502 if (!usertask) 2503 return; 2504 mm = get_task_mm(usertask); 2505 if (!mm) { 2506 put_task_struct(usertask); 2507 return; 2508 } 2509 2510 mutex_lock(&process_info->lock); 2511 2512 if (update_invalid_user_pages(process_info, mm)) 2513 goto unlock_out; 2514 /* userptr_inval_list can be empty if all evicted userptr BOs 2515 * have been freed. In that case there is nothing to validate 2516 * and we can just restart the queues. 2517 */ 2518 if (!list_empty(&process_info->userptr_inval_list)) { 2519 if (atomic_read(&process_info->evicted_bos) != evicted_bos) 2520 goto unlock_out; /* Concurrent eviction, try again */ 2521 2522 if (validate_invalid_user_pages(process_info)) 2523 goto unlock_out; 2524 } 2525 /* Final check for concurrent evicton and atomic update. If 2526 * another eviction happens after successful update, it will 2527 * be a first eviction that calls quiesce_mm. The eviction 2528 * reference counting inside KFD will handle this case. 2529 */ 2530 if (atomic_cmpxchg(&process_info->evicted_bos, evicted_bos, 0) != 2531 evicted_bos) 2532 goto unlock_out; 2533 evicted_bos = 0; 2534 if (kgd2kfd_resume_mm(mm)) { 2535 pr_err("%s: Failed to resume KFD\n", __func__); 2536 /* No recovery from this failure. Probably the CP is 2537 * hanging. No point trying again. 2538 */ 2539 } 2540 2541 unlock_out: 2542 mutex_unlock(&process_info->lock); 2543 2544 /* If validation failed, reschedule another attempt */ 2545 if (evicted_bos) { 2546 schedule_delayed_work(&process_info->restore_userptr_work, 2547 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2548 2549 kfd_smi_event_queue_restore_rescheduled(mm); 2550 } 2551 mmput(mm); 2552 put_task_struct(usertask); 2553 } 2554 2555 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given 2556 * KFD process identified by process_info 2557 * 2558 * @process_info: amdkfd_process_info of the KFD process 2559 * 2560 * After memory eviction, restore thread calls this function. The function 2561 * should be called when the Process is still valid. BO restore involves - 2562 * 2563 * 1. Release old eviction fence and create new one 2564 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list. 2565 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of 2566 * BOs that need to be reserved. 2567 * 4. Reserve all the BOs 2568 * 5. Validate of PD and PT BOs. 2569 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence 2570 * 7. Add fence to all PD and PT BOs. 2571 * 8. Unreserve all BOs 2572 */ 2573 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) 2574 { 2575 struct amdgpu_bo_list_entry *pd_bo_list; 2576 struct amdkfd_process_info *process_info = info; 2577 struct amdgpu_vm *peer_vm; 2578 struct kgd_mem *mem; 2579 struct bo_vm_reservation_context ctx; 2580 struct amdgpu_amdkfd_fence *new_fence; 2581 int ret = 0, i; 2582 struct list_head duplicate_save; 2583 struct amdgpu_sync sync_obj; 2584 unsigned long failed_size = 0; 2585 unsigned long total_size = 0; 2586 2587 INIT_LIST_HEAD(&duplicate_save); 2588 INIT_LIST_HEAD(&ctx.list); 2589 INIT_LIST_HEAD(&ctx.duplicates); 2590 2591 pd_bo_list = kcalloc(process_info->n_vms, 2592 sizeof(struct amdgpu_bo_list_entry), 2593 GFP_KERNEL); 2594 if (!pd_bo_list) 2595 return -ENOMEM; 2596 2597 i = 0; 2598 mutex_lock(&process_info->lock); 2599 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2600 vm_list_node) 2601 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]); 2602 2603 /* Reserve all BOs and page tables/directory. Add all BOs from 2604 * kfd_bo_list to ctx.list 2605 */ 2606 list_for_each_entry(mem, &process_info->kfd_bo_list, 2607 validate_list.head) { 2608 2609 list_add_tail(&mem->resv_list.head, &ctx.list); 2610 mem->resv_list.bo = mem->validate_list.bo; 2611 mem->resv_list.num_shared = mem->validate_list.num_shared; 2612 } 2613 2614 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list, 2615 false, &duplicate_save); 2616 if (ret) { 2617 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n"); 2618 goto ttm_reserve_fail; 2619 } 2620 2621 amdgpu_sync_create(&sync_obj); 2622 2623 /* Validate PDs and PTs */ 2624 ret = process_validate_vms(process_info); 2625 if (ret) 2626 goto validate_map_fail; 2627 2628 ret = process_sync_pds_resv(process_info, &sync_obj); 2629 if (ret) { 2630 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n"); 2631 goto validate_map_fail; 2632 } 2633 2634 /* Validate BOs and map them to GPUVM (update VM page tables). */ 2635 list_for_each_entry(mem, &process_info->kfd_bo_list, 2636 validate_list.head) { 2637 2638 struct amdgpu_bo *bo = mem->bo; 2639 uint32_t domain = mem->domain; 2640 struct kfd_mem_attachment *attachment; 2641 struct dma_resv_iter cursor; 2642 struct dma_fence *fence; 2643 2644 total_size += amdgpu_bo_size(bo); 2645 2646 ret = amdgpu_amdkfd_bo_validate(bo, domain, false); 2647 if (ret) { 2648 pr_debug("Memory eviction: Validate BOs failed\n"); 2649 failed_size += amdgpu_bo_size(bo); 2650 ret = amdgpu_amdkfd_bo_validate(bo, 2651 AMDGPU_GEM_DOMAIN_GTT, false); 2652 if (ret) { 2653 pr_debug("Memory eviction: Try again\n"); 2654 goto validate_map_fail; 2655 } 2656 } 2657 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, 2658 DMA_RESV_USAGE_KERNEL, fence) { 2659 ret = amdgpu_sync_fence(&sync_obj, fence); 2660 if (ret) { 2661 pr_debug("Memory eviction: Sync BO fence failed. Try again\n"); 2662 goto validate_map_fail; 2663 } 2664 } 2665 list_for_each_entry(attachment, &mem->attachments, list) { 2666 if (!attachment->is_mapped) 2667 continue; 2668 2669 kfd_mem_dmaunmap_attachment(mem, attachment); 2670 ret = update_gpuvm_pte(mem, attachment, &sync_obj); 2671 if (ret) { 2672 pr_debug("Memory eviction: update PTE failed. Try again\n"); 2673 goto validate_map_fail; 2674 } 2675 } 2676 } 2677 2678 if (failed_size) 2679 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size); 2680 2681 /* Update page directories */ 2682 ret = process_update_pds(process_info, &sync_obj); 2683 if (ret) { 2684 pr_debug("Memory eviction: update PDs failed. Try again\n"); 2685 goto validate_map_fail; 2686 } 2687 2688 /* Wait for validate and PT updates to finish */ 2689 amdgpu_sync_wait(&sync_obj, false); 2690 2691 /* Release old eviction fence and create new one, because fence only 2692 * goes from unsignaled to signaled, fence cannot be reused. 2693 * Use context and mm from the old fence. 2694 */ 2695 new_fence = amdgpu_amdkfd_fence_create( 2696 process_info->eviction_fence->base.context, 2697 process_info->eviction_fence->mm, 2698 NULL); 2699 if (!new_fence) { 2700 pr_err("Failed to create eviction fence\n"); 2701 ret = -ENOMEM; 2702 goto validate_map_fail; 2703 } 2704 dma_fence_put(&process_info->eviction_fence->base); 2705 process_info->eviction_fence = new_fence; 2706 *ef = dma_fence_get(&new_fence->base); 2707 2708 /* Attach new eviction fence to all BOs except pinned ones */ 2709 list_for_each_entry(mem, &process_info->kfd_bo_list, 2710 validate_list.head) { 2711 if (mem->bo->tbo.pin_count) 2712 continue; 2713 2714 dma_resv_add_fence(mem->bo->tbo.base.resv, 2715 &process_info->eviction_fence->base, 2716 DMA_RESV_USAGE_BOOKKEEP); 2717 } 2718 /* Attach eviction fence to PD / PT BOs */ 2719 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2720 vm_list_node) { 2721 struct amdgpu_bo *bo = peer_vm->root.bo; 2722 2723 dma_resv_add_fence(bo->tbo.base.resv, 2724 &process_info->eviction_fence->base, 2725 DMA_RESV_USAGE_BOOKKEEP); 2726 } 2727 2728 validate_map_fail: 2729 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list); 2730 amdgpu_sync_free(&sync_obj); 2731 ttm_reserve_fail: 2732 mutex_unlock(&process_info->lock); 2733 kfree(pd_bo_list); 2734 return ret; 2735 } 2736 2737 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem) 2738 { 2739 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 2740 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws; 2741 int ret; 2742 2743 if (!info || !gws) 2744 return -EINVAL; 2745 2746 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 2747 if (!*mem) 2748 return -ENOMEM; 2749 2750 mutex_init(&(*mem)->lock); 2751 INIT_LIST_HEAD(&(*mem)->attachments); 2752 (*mem)->bo = amdgpu_bo_ref(gws_bo); 2753 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS; 2754 (*mem)->process_info = process_info; 2755 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false); 2756 amdgpu_sync_create(&(*mem)->sync); 2757 2758 2759 /* Validate gws bo the first time it is added to process */ 2760 mutex_lock(&(*mem)->process_info->lock); 2761 ret = amdgpu_bo_reserve(gws_bo, false); 2762 if (unlikely(ret)) { 2763 pr_err("Reserve gws bo failed %d\n", ret); 2764 goto bo_reservation_failure; 2765 } 2766 2767 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true); 2768 if (ret) { 2769 pr_err("GWS BO validate failed %d\n", ret); 2770 goto bo_validation_failure; 2771 } 2772 /* GWS resource is shared b/t amdgpu and amdkfd 2773 * Add process eviction fence to bo so they can 2774 * evict each other. 2775 */ 2776 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); 2777 if (ret) 2778 goto reserve_shared_fail; 2779 dma_resv_add_fence(gws_bo->tbo.base.resv, 2780 &process_info->eviction_fence->base, 2781 DMA_RESV_USAGE_BOOKKEEP); 2782 amdgpu_bo_unreserve(gws_bo); 2783 mutex_unlock(&(*mem)->process_info->lock); 2784 2785 return ret; 2786 2787 reserve_shared_fail: 2788 bo_validation_failure: 2789 amdgpu_bo_unreserve(gws_bo); 2790 bo_reservation_failure: 2791 mutex_unlock(&(*mem)->process_info->lock); 2792 amdgpu_sync_free(&(*mem)->sync); 2793 remove_kgd_mem_from_kfd_bo_list(*mem, process_info); 2794 amdgpu_bo_unref(&gws_bo); 2795 mutex_destroy(&(*mem)->lock); 2796 kfree(*mem); 2797 *mem = NULL; 2798 return ret; 2799 } 2800 2801 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) 2802 { 2803 int ret; 2804 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 2805 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 2806 struct amdgpu_bo *gws_bo = kgd_mem->bo; 2807 2808 /* Remove BO from process's validate list so restore worker won't touch 2809 * it anymore 2810 */ 2811 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info); 2812 2813 ret = amdgpu_bo_reserve(gws_bo, false); 2814 if (unlikely(ret)) { 2815 pr_err("Reserve gws bo failed %d\n", ret); 2816 //TODO add BO back to validate_list? 2817 return ret; 2818 } 2819 amdgpu_amdkfd_remove_eviction_fence(gws_bo, 2820 process_info->eviction_fence); 2821 amdgpu_bo_unreserve(gws_bo); 2822 amdgpu_sync_free(&kgd_mem->sync); 2823 amdgpu_bo_unref(&gws_bo); 2824 mutex_destroy(&kgd_mem->lock); 2825 kfree(mem); 2826 return 0; 2827 } 2828 2829 /* Returns GPU-specific tiling mode information */ 2830 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 2831 struct tile_config *config) 2832 { 2833 config->gb_addr_config = adev->gfx.config.gb_addr_config; 2834 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 2835 config->num_tile_configs = 2836 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 2837 config->macro_tile_config_ptr = 2838 adev->gfx.config.macrotile_mode_array; 2839 config->num_macro_tile_configs = 2840 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 2841 2842 /* Those values are not set from GFX9 onwards */ 2843 config->num_banks = adev->gfx.config.num_banks; 2844 config->num_ranks = adev->gfx.config.num_ranks; 2845 2846 return 0; 2847 } 2848 2849 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem) 2850 { 2851 struct kfd_mem_attachment *entry; 2852 2853 list_for_each_entry(entry, &mem->attachments, list) { 2854 if (entry->is_mapped && entry->adev == adev) 2855 return true; 2856 } 2857 return false; 2858 } 2859 2860 #if defined(CONFIG_DEBUG_FS) 2861 2862 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data) 2863 { 2864 2865 spin_lock(&kfd_mem_limit.mem_limit_lock); 2866 seq_printf(m, "System mem used %lldM out of %lluM\n", 2867 (kfd_mem_limit.system_mem_used >> 20), 2868 (kfd_mem_limit.max_system_mem_limit >> 20)); 2869 seq_printf(m, "TTM mem used %lldM out of %lluM\n", 2870 (kfd_mem_limit.ttm_mem_used >> 20), 2871 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 2872 spin_unlock(&kfd_mem_limit.mem_limit_lock); 2873 2874 return 0; 2875 } 2876 2877 #endif 2878