1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014-2018 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #include <linux/dma-buf.h> 24 #include <linux/list.h> 25 #include <linux/pagemap.h> 26 #include <linux/sched/mm.h> 27 #include <linux/sched/task.h> 28 #include <drm/ttm/ttm_tt.h> 29 30 #include "amdgpu_object.h" 31 #include "amdgpu_gem.h" 32 #include "amdgpu_vm.h" 33 #include "amdgpu_hmm.h" 34 #include "amdgpu_amdkfd.h" 35 #include "amdgpu_dma_buf.h" 36 #include <uapi/linux/kfd_ioctl.h> 37 #include "amdgpu_xgmi.h" 38 #include "kfd_smi_events.h" 39 #include <drm/ttm/ttm_tt.h> 40 41 /* Userptr restore delay, just long enough to allow consecutive VM 42 * changes to accumulate 43 */ 44 #define AMDGPU_USERPTR_RESTORE_DELAY_MS 1 45 46 /* 47 * Align VRAM availability to 2MB to avoid fragmentation caused by 4K allocations in the tail 2MB 48 * BO chunk 49 */ 50 #define VRAM_AVAILABLITY_ALIGN (1 << 21) 51 52 /* Impose limit on how much memory KFD can use */ 53 static struct { 54 uint64_t max_system_mem_limit; 55 uint64_t max_ttm_mem_limit; 56 int64_t system_mem_used; 57 int64_t ttm_mem_used; 58 spinlock_t mem_limit_lock; 59 } kfd_mem_limit; 60 61 static const char * const domain_bit_to_string[] = { 62 "CPU", 63 "GTT", 64 "VRAM", 65 "GDS", 66 "GWS", 67 "OA" 68 }; 69 70 #define domain_string(domain) domain_bit_to_string[ffs(domain)-1] 71 72 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work); 73 74 static bool kfd_mem_is_attached(struct amdgpu_vm *avm, 75 struct kgd_mem *mem) 76 { 77 struct kfd_mem_attachment *entry; 78 79 list_for_each_entry(entry, &mem->attachments, list) 80 if (entry->bo_va->base.vm == avm) 81 return true; 82 83 return false; 84 } 85 86 /** 87 * reuse_dmamap() - Check whether adev can share the original 88 * userptr BO 89 * 90 * If both adev and bo_adev are in direct mapping or 91 * in the same iommu group, they can share the original BO. 92 * 93 * @adev: Device to which can or cannot share the original BO 94 * @bo_adev: Device to which allocated BO belongs to 95 * 96 * Return: returns true if adev can share original userptr BO, 97 * false otherwise. 98 */ 99 static bool reuse_dmamap(struct amdgpu_device *adev, struct amdgpu_device *bo_adev) 100 { 101 return (adev->ram_is_direct_mapped && bo_adev->ram_is_direct_mapped) || 102 (adev->dev->iommu_group == bo_adev->dev->iommu_group); 103 } 104 105 /* Set memory usage limits. Current, limits are 106 * System (TTM + userptr) memory - 15/16th System RAM 107 * TTM memory - 3/8th System RAM 108 */ 109 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 110 { 111 struct sysinfo si; 112 uint64_t mem; 113 114 if (kfd_mem_limit.max_system_mem_limit) 115 return; 116 117 si_meminfo(&si); 118 mem = si.freeram - si.freehigh; 119 mem *= si.mem_unit; 120 121 spin_lock_init(&kfd_mem_limit.mem_limit_lock); 122 kfd_mem_limit.max_system_mem_limit = mem - (mem >> 4); 123 kfd_mem_limit.max_ttm_mem_limit = ttm_tt_pages_limit() << PAGE_SHIFT; 124 pr_debug("Kernel memory limit %lluM, TTM limit %lluM\n", 125 (kfd_mem_limit.max_system_mem_limit >> 20), 126 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 127 } 128 129 void amdgpu_amdkfd_reserve_system_mem(uint64_t size) 130 { 131 kfd_mem_limit.system_mem_used += size; 132 } 133 134 /* Estimate page table size needed to represent a given memory size 135 * 136 * With 4KB pages, we need one 8 byte PTE for each 4KB of memory 137 * (factor 512, >> 9). With 2MB pages, we need one 8 byte PTE for 2MB 138 * of memory (factor 256K, >> 18). ROCm user mode tries to optimize 139 * for 2MB pages for TLB efficiency. However, small allocations and 140 * fragmented system memory still need some 4KB pages. We choose a 141 * compromise that should work in most cases without reserving too 142 * much memory for page tables unnecessarily (factor 16K, >> 14). 143 */ 144 145 #define ESTIMATE_PT_SIZE(mem_size) max(((mem_size) >> 14), AMDGPU_VM_RESERVED_VRAM) 146 147 /** 148 * amdgpu_amdkfd_reserve_mem_limit() - Decrease available memory by size 149 * of buffer. 150 * 151 * @adev: Device to which allocated BO belongs to 152 * @size: Size of buffer, in bytes, encapsulated by B0. This should be 153 * equivalent to amdgpu_bo_size(BO) 154 * @alloc_flag: Flag used in allocating a BO as noted above 155 * 156 * Return: returns -ENOMEM in case of error, ZERO otherwise 157 */ 158 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 159 uint64_t size, u32 alloc_flag) 160 { 161 uint64_t reserved_for_pt = 162 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 163 size_t system_mem_needed, ttm_mem_needed, vram_needed; 164 int ret = 0; 165 166 system_mem_needed = 0; 167 ttm_mem_needed = 0; 168 vram_needed = 0; 169 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 170 system_mem_needed = size; 171 ttm_mem_needed = size; 172 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 173 /* 174 * Conservatively round up the allocation requirement to 2 MB 175 * to avoid fragmentation caused by 4K allocations in the tail 176 * 2M BO chunk. 177 */ 178 vram_needed = size; 179 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 180 system_mem_needed = size; 181 } else if (!(alloc_flag & 182 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 183 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 184 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 185 return -ENOMEM; 186 } 187 188 spin_lock(&kfd_mem_limit.mem_limit_lock); 189 190 if (kfd_mem_limit.system_mem_used + system_mem_needed > 191 kfd_mem_limit.max_system_mem_limit) 192 pr_debug("Set no_system_mem_limit=1 if using shared memory\n"); 193 194 if ((kfd_mem_limit.system_mem_used + system_mem_needed > 195 kfd_mem_limit.max_system_mem_limit && !no_system_mem_limit) || 196 (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > 197 kfd_mem_limit.max_ttm_mem_limit) || 198 (adev && adev->kfd.vram_used + vram_needed > 199 adev->gmc.real_vram_size - reserved_for_pt)) { 200 ret = -ENOMEM; 201 goto release; 202 } 203 204 /* Update memory accounting by decreasing available system 205 * memory, TTM memory and GPU memory as computed above 206 */ 207 WARN_ONCE(vram_needed && !adev, 208 "adev reference can't be null when vram is used"); 209 if (adev) { 210 adev->kfd.vram_used += vram_needed; 211 adev->kfd.vram_used_aligned += ALIGN(vram_needed, VRAM_AVAILABLITY_ALIGN); 212 } 213 kfd_mem_limit.system_mem_used += system_mem_needed; 214 kfd_mem_limit.ttm_mem_used += ttm_mem_needed; 215 216 release: 217 spin_unlock(&kfd_mem_limit.mem_limit_lock); 218 return ret; 219 } 220 221 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 222 uint64_t size, u32 alloc_flag) 223 { 224 spin_lock(&kfd_mem_limit.mem_limit_lock); 225 226 if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 227 kfd_mem_limit.system_mem_used -= size; 228 kfd_mem_limit.ttm_mem_used -= size; 229 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 230 WARN_ONCE(!adev, 231 "adev reference can't be null when alloc mem flags vram is set"); 232 if (adev) { 233 adev->kfd.vram_used -= size; 234 adev->kfd.vram_used_aligned -= ALIGN(size, VRAM_AVAILABLITY_ALIGN); 235 } 236 } else if (alloc_flag & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 237 kfd_mem_limit.system_mem_used -= size; 238 } else if (!(alloc_flag & 239 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 240 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 241 pr_err("%s: Invalid BO type %#x\n", __func__, alloc_flag); 242 goto release; 243 } 244 WARN_ONCE(adev && adev->kfd.vram_used < 0, 245 "KFD VRAM memory accounting unbalanced"); 246 WARN_ONCE(kfd_mem_limit.ttm_mem_used < 0, 247 "KFD TTM memory accounting unbalanced"); 248 WARN_ONCE(kfd_mem_limit.system_mem_used < 0, 249 "KFD system memory accounting unbalanced"); 250 251 release: 252 spin_unlock(&kfd_mem_limit.mem_limit_lock); 253 } 254 255 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 256 { 257 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); 258 u32 alloc_flags = bo->kfd_bo->alloc_flags; 259 u64 size = amdgpu_bo_size(bo); 260 261 amdgpu_amdkfd_unreserve_mem_limit(adev, size, alloc_flags); 262 263 kfree(bo->kfd_bo); 264 } 265 266 /** 267 * @create_dmamap_sg_bo: Creates a amdgpu_bo object to reflect information 268 * about USERPTR or DOOREBELL or MMIO BO. 269 * @adev: Device for which dmamap BO is being created 270 * @mem: BO of peer device that is being DMA mapped. Provides parameters 271 * in building the dmamap BO 272 * @bo_out: Output parameter updated with handle of dmamap BO 273 */ 274 static int 275 create_dmamap_sg_bo(struct amdgpu_device *adev, 276 struct kgd_mem *mem, struct amdgpu_bo **bo_out) 277 { 278 struct drm_gem_object *gem_obj; 279 int ret; 280 uint64_t flags = 0; 281 282 ret = amdgpu_bo_reserve(mem->bo, false); 283 if (ret) 284 return ret; 285 286 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) 287 flags |= mem->bo->flags & (AMDGPU_GEM_CREATE_COHERENT | 288 AMDGPU_GEM_CREATE_UNCACHED); 289 290 ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, 291 AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, 292 ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj); 293 294 amdgpu_bo_unreserve(mem->bo); 295 296 if (ret) { 297 pr_err("Error in creating DMA mappable SG BO on domain: %d\n", ret); 298 return -EINVAL; 299 } 300 301 *bo_out = gem_to_amdgpu_bo(gem_obj); 302 (*bo_out)->parent = amdgpu_bo_ref(mem->bo); 303 return ret; 304 } 305 306 /* amdgpu_amdkfd_remove_eviction_fence - Removes eviction fence from BO's 307 * reservation object. 308 * 309 * @bo: [IN] Remove eviction fence(s) from this BO 310 * @ef: [IN] This eviction fence is removed if it 311 * is present in the shared list. 312 * 313 * NOTE: Must be called with BO reserved i.e. bo->tbo.resv->lock held. 314 */ 315 static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, 316 struct amdgpu_amdkfd_fence *ef) 317 { 318 struct dma_fence *replacement; 319 320 if (!ef) 321 return -EINVAL; 322 323 /* TODO: Instead of block before we should use the fence of the page 324 * table update and TLB flush here directly. 325 */ 326 replacement = dma_fence_get_stub(); 327 dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, 328 replacement, DMA_RESV_USAGE_BOOKKEEP); 329 dma_fence_put(replacement); 330 return 0; 331 } 332 333 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 334 { 335 struct amdgpu_bo *root = bo; 336 struct amdgpu_vm_bo_base *vm_bo; 337 struct amdgpu_vm *vm; 338 struct amdkfd_process_info *info; 339 struct amdgpu_amdkfd_fence *ef; 340 int ret; 341 342 /* we can always get vm_bo from root PD bo.*/ 343 while (root->parent) 344 root = root->parent; 345 346 vm_bo = root->vm_bo; 347 if (!vm_bo) 348 return 0; 349 350 vm = vm_bo->vm; 351 if (!vm) 352 return 0; 353 354 info = vm->process_info; 355 if (!info || !info->eviction_fence) 356 return 0; 357 358 ef = container_of(dma_fence_get(&info->eviction_fence->base), 359 struct amdgpu_amdkfd_fence, base); 360 361 BUG_ON(!dma_resv_trylock(bo->tbo.base.resv)); 362 ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef); 363 dma_resv_unlock(bo->tbo.base.resv); 364 365 dma_fence_put(&ef->base); 366 return ret; 367 } 368 369 static int amdgpu_amdkfd_bo_validate(struct amdgpu_bo *bo, uint32_t domain, 370 bool wait) 371 { 372 struct ttm_operation_ctx ctx = { false, false }; 373 int ret; 374 375 if (WARN(amdgpu_ttm_tt_get_usermm(bo->tbo.ttm), 376 "Called with userptr BO")) 377 return -EINVAL; 378 379 amdgpu_bo_placement_from_domain(bo, domain); 380 381 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 382 if (ret) 383 goto validate_fail; 384 if (wait) 385 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 386 387 validate_fail: 388 return ret; 389 } 390 391 static int amdgpu_amdkfd_validate_vm_bo(void *_unused, struct amdgpu_bo *bo) 392 { 393 return amdgpu_amdkfd_bo_validate(bo, bo->allowed_domains, false); 394 } 395 396 /* vm_validate_pt_pd_bos - Validate page table and directory BOs 397 * 398 * Page directories are not updated here because huge page handling 399 * during page table updates can invalidate page directory entries 400 * again. Page directories are only updated after updating page 401 * tables. 402 */ 403 static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm) 404 { 405 struct amdgpu_bo *pd = vm->root.bo; 406 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 407 int ret; 408 409 ret = amdgpu_vm_validate_pt_bos(adev, vm, amdgpu_amdkfd_validate_vm_bo, NULL); 410 if (ret) { 411 pr_err("failed to validate PT BOs\n"); 412 return ret; 413 } 414 415 vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.bo); 416 417 return 0; 418 } 419 420 static int vm_update_pds(struct amdgpu_vm *vm, struct amdgpu_sync *sync) 421 { 422 struct amdgpu_bo *pd = vm->root.bo; 423 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 424 int ret; 425 426 ret = amdgpu_vm_update_pdes(adev, vm, false); 427 if (ret) 428 return ret; 429 430 return amdgpu_sync_fence(sync, vm->last_update); 431 } 432 433 static uint64_t get_pte_flags(struct amdgpu_device *adev, struct kgd_mem *mem) 434 { 435 uint32_t mapping_flags = AMDGPU_VM_PAGE_READABLE | 436 AMDGPU_VM_MTYPE_DEFAULT; 437 438 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE) 439 mapping_flags |= AMDGPU_VM_PAGE_WRITEABLE; 440 if (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE) 441 mapping_flags |= AMDGPU_VM_PAGE_EXECUTABLE; 442 443 return amdgpu_gem_va_map_flags(adev, mapping_flags); 444 } 445 446 /** 447 * create_sg_table() - Create an sg_table for a contiguous DMA addr range 448 * @addr: The starting address to point to 449 * @size: Size of memory area in bytes being pointed to 450 * 451 * Allocates an instance of sg_table and initializes it to point to memory 452 * area specified by input parameters. The address used to build is assumed 453 * to be DMA mapped, if needed. 454 * 455 * DOORBELL or MMIO BOs use only one scatterlist node in their sg_table 456 * because they are physically contiguous. 457 * 458 * Return: Initialized instance of SG Table or NULL 459 */ 460 static struct sg_table *create_sg_table(uint64_t addr, uint32_t size) 461 { 462 struct sg_table *sg = kmalloc(sizeof(*sg), GFP_KERNEL); 463 464 if (!sg) 465 return NULL; 466 if (sg_alloc_table(sg, 1, GFP_KERNEL)) { 467 kfree(sg); 468 return NULL; 469 } 470 sg_dma_address(sg->sgl) = addr; 471 sg->sgl->length = size; 472 #ifdef CONFIG_NEED_SG_DMA_LENGTH 473 sg->sgl->dma_length = size; 474 #endif 475 return sg; 476 } 477 478 static int 479 kfd_mem_dmamap_userptr(struct kgd_mem *mem, 480 struct kfd_mem_attachment *attachment) 481 { 482 enum dma_data_direction direction = 483 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 484 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 485 struct ttm_operation_ctx ctx = {.interruptible = true}; 486 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 487 struct amdgpu_device *adev = attachment->adev; 488 struct ttm_tt *src_ttm = mem->bo->tbo.ttm; 489 struct ttm_tt *ttm = bo->tbo.ttm; 490 int ret; 491 492 if (WARN_ON(ttm->num_pages != src_ttm->num_pages)) 493 return -EINVAL; 494 495 ttm->sg = kmalloc(sizeof(*ttm->sg), GFP_KERNEL); 496 if (unlikely(!ttm->sg)) 497 return -ENOMEM; 498 499 /* Same sequence as in amdgpu_ttm_tt_pin_userptr */ 500 ret = sg_alloc_table_from_pages(ttm->sg, src_ttm->pages, 501 ttm->num_pages, 0, 502 (u64)ttm->num_pages << PAGE_SHIFT, 503 GFP_KERNEL); 504 if (unlikely(ret)) 505 goto free_sg; 506 507 ret = dma_map_sgtable(adev->dev, ttm->sg, direction, 0); 508 if (unlikely(ret)) 509 goto release_sg; 510 511 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 512 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 513 if (ret) 514 goto unmap_sg; 515 516 return 0; 517 518 unmap_sg: 519 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 520 release_sg: 521 pr_err("DMA map userptr failed: %d\n", ret); 522 sg_free_table(ttm->sg); 523 free_sg: 524 kfree(ttm->sg); 525 ttm->sg = NULL; 526 return ret; 527 } 528 529 static int 530 kfd_mem_dmamap_dmabuf(struct kfd_mem_attachment *attachment) 531 { 532 struct ttm_operation_ctx ctx = {.interruptible = true}; 533 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 534 int ret; 535 536 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 537 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 538 if (ret) 539 return ret; 540 541 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 542 return ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 543 } 544 545 /** 546 * kfd_mem_dmamap_sg_bo() - Create DMA mapped sg_table to access DOORBELL or MMIO BO 547 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 548 * @attachment: Virtual address attachment of the BO on accessing device 549 * 550 * An access request from the device that owns DOORBELL does not require DMA mapping. 551 * This is because the request doesn't go through PCIe root complex i.e. it instead 552 * loops back. The need to DMA map arises only when accessing peer device's DOORBELL 553 * 554 * In contrast, all access requests for MMIO need to be DMA mapped without regard to 555 * device ownership. This is because access requests for MMIO go through PCIe root 556 * complex. 557 * 558 * This is accomplished in two steps: 559 * - Obtain DMA mapped address of DOORBELL or MMIO memory that could be used 560 * in updating requesting device's page table 561 * - Signal TTM to mark memory pointed to by requesting device's BO as GPU 562 * accessible. This allows an update of requesting device's page table 563 * with entries associated with DOOREBELL or MMIO memory 564 * 565 * This method is invoked in the following contexts: 566 * - Mapping of DOORBELL or MMIO BO of same or peer device 567 * - Validating an evicted DOOREBELL or MMIO BO on device seeking access 568 * 569 * Return: ZERO if successful, NON-ZERO otherwise 570 */ 571 static int 572 kfd_mem_dmamap_sg_bo(struct kgd_mem *mem, 573 struct kfd_mem_attachment *attachment) 574 { 575 struct ttm_operation_ctx ctx = {.interruptible = true}; 576 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 577 struct amdgpu_device *adev = attachment->adev; 578 struct ttm_tt *ttm = bo->tbo.ttm; 579 enum dma_data_direction dir; 580 dma_addr_t dma_addr; 581 bool mmio; 582 int ret; 583 584 /* Expect SG Table of dmapmap BO to be NULL */ 585 mmio = (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); 586 if (unlikely(ttm->sg)) { 587 pr_err("SG Table of %d BO for peer device is UNEXPECTEDLY NON-NULL", mmio); 588 return -EINVAL; 589 } 590 591 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 592 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 593 dma_addr = mem->bo->tbo.sg->sgl->dma_address; 594 pr_debug("%d BO size: %d\n", mmio, mem->bo->tbo.sg->sgl->length); 595 pr_debug("%d BO address before DMA mapping: %llx\n", mmio, dma_addr); 596 dma_addr = dma_map_resource(adev->dev, dma_addr, 597 mem->bo->tbo.sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 598 ret = dma_mapping_error(adev->dev, dma_addr); 599 if (unlikely(ret)) 600 return ret; 601 pr_debug("%d BO address after DMA mapping: %llx\n", mmio, dma_addr); 602 603 ttm->sg = create_sg_table(dma_addr, mem->bo->tbo.sg->sgl->length); 604 if (unlikely(!ttm->sg)) { 605 ret = -ENOMEM; 606 goto unmap_sg; 607 } 608 609 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 610 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 611 if (unlikely(ret)) 612 goto free_sg; 613 614 return ret; 615 616 free_sg: 617 sg_free_table(ttm->sg); 618 kfree(ttm->sg); 619 ttm->sg = NULL; 620 unmap_sg: 621 dma_unmap_resource(adev->dev, dma_addr, mem->bo->tbo.sg->sgl->length, 622 dir, DMA_ATTR_SKIP_CPU_SYNC); 623 return ret; 624 } 625 626 static int 627 kfd_mem_dmamap_attachment(struct kgd_mem *mem, 628 struct kfd_mem_attachment *attachment) 629 { 630 switch (attachment->type) { 631 case KFD_MEM_ATT_SHARED: 632 return 0; 633 case KFD_MEM_ATT_USERPTR: 634 return kfd_mem_dmamap_userptr(mem, attachment); 635 case KFD_MEM_ATT_DMABUF: 636 return kfd_mem_dmamap_dmabuf(attachment); 637 case KFD_MEM_ATT_SG: 638 return kfd_mem_dmamap_sg_bo(mem, attachment); 639 default: 640 WARN_ON_ONCE(1); 641 } 642 return -EINVAL; 643 } 644 645 static void 646 kfd_mem_dmaunmap_userptr(struct kgd_mem *mem, 647 struct kfd_mem_attachment *attachment) 648 { 649 enum dma_data_direction direction = 650 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 651 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 652 struct ttm_operation_ctx ctx = {.interruptible = false}; 653 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 654 struct amdgpu_device *adev = attachment->adev; 655 struct ttm_tt *ttm = bo->tbo.ttm; 656 657 if (unlikely(!ttm->sg)) 658 return; 659 660 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 661 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 662 663 dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); 664 sg_free_table(ttm->sg); 665 kfree(ttm->sg); 666 ttm->sg = NULL; 667 } 668 669 static void 670 kfd_mem_dmaunmap_dmabuf(struct kfd_mem_attachment *attachment) 671 { 672 /* This is a no-op. We don't want to trigger eviction fences when 673 * unmapping DMABufs. Therefore the invalidation (moving to system 674 * domain) is done in kfd_mem_dmamap_dmabuf. 675 */ 676 } 677 678 /** 679 * kfd_mem_dmaunmap_sg_bo() - Free DMA mapped sg_table of DOORBELL or MMIO BO 680 * @mem: SG BO of the DOORBELL or MMIO resource on the owning device 681 * @attachment: Virtual address attachment of the BO on accessing device 682 * 683 * The method performs following steps: 684 * - Signal TTM to mark memory pointed to by BO as GPU inaccessible 685 * - Free SG Table that is used to encapsulate DMA mapped memory of 686 * peer device's DOORBELL or MMIO memory 687 * 688 * This method is invoked in the following contexts: 689 * UNMapping of DOORBELL or MMIO BO on a device having access to its memory 690 * Eviction of DOOREBELL or MMIO BO on device having access to its memory 691 * 692 * Return: void 693 */ 694 static void 695 kfd_mem_dmaunmap_sg_bo(struct kgd_mem *mem, 696 struct kfd_mem_attachment *attachment) 697 { 698 struct ttm_operation_ctx ctx = {.interruptible = true}; 699 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 700 struct amdgpu_device *adev = attachment->adev; 701 struct ttm_tt *ttm = bo->tbo.ttm; 702 enum dma_data_direction dir; 703 704 if (unlikely(!ttm->sg)) { 705 pr_err("SG Table of BO is UNEXPECTEDLY NULL"); 706 return; 707 } 708 709 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 710 ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 711 712 dir = mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 713 DMA_BIDIRECTIONAL : DMA_TO_DEVICE; 714 dma_unmap_resource(adev->dev, ttm->sg->sgl->dma_address, 715 ttm->sg->sgl->length, dir, DMA_ATTR_SKIP_CPU_SYNC); 716 sg_free_table(ttm->sg); 717 kfree(ttm->sg); 718 ttm->sg = NULL; 719 bo->tbo.sg = NULL; 720 } 721 722 static void 723 kfd_mem_dmaunmap_attachment(struct kgd_mem *mem, 724 struct kfd_mem_attachment *attachment) 725 { 726 switch (attachment->type) { 727 case KFD_MEM_ATT_SHARED: 728 break; 729 case KFD_MEM_ATT_USERPTR: 730 kfd_mem_dmaunmap_userptr(mem, attachment); 731 break; 732 case KFD_MEM_ATT_DMABUF: 733 kfd_mem_dmaunmap_dmabuf(attachment); 734 break; 735 case KFD_MEM_ATT_SG: 736 kfd_mem_dmaunmap_sg_bo(mem, attachment); 737 break; 738 default: 739 WARN_ON_ONCE(1); 740 } 741 } 742 743 static int kfd_mem_export_dmabuf(struct kgd_mem *mem) 744 { 745 if (!mem->dmabuf) { 746 struct dma_buf *ret = amdgpu_gem_prime_export( 747 &mem->bo->tbo.base, 748 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? 749 DRM_RDWR : 0); 750 if (IS_ERR(ret)) 751 return PTR_ERR(ret); 752 mem->dmabuf = ret; 753 } 754 755 return 0; 756 } 757 758 static int 759 kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, 760 struct amdgpu_bo **bo) 761 { 762 struct drm_gem_object *gobj; 763 int ret; 764 765 ret = kfd_mem_export_dmabuf(mem); 766 if (ret) 767 return ret; 768 769 gobj = amdgpu_gem_prime_import(adev_to_drm(adev), mem->dmabuf); 770 if (IS_ERR(gobj)) 771 return PTR_ERR(gobj); 772 773 *bo = gem_to_amdgpu_bo(gobj); 774 (*bo)->flags |= AMDGPU_GEM_CREATE_PREEMPTIBLE; 775 776 return 0; 777 } 778 779 /* kfd_mem_attach - Add a BO to a VM 780 * 781 * Everything that needs to bo done only once when a BO is first added 782 * to a VM. It can later be mapped and unmapped many times without 783 * repeating these steps. 784 * 785 * 0. Create BO for DMA mapping, if needed 786 * 1. Allocate and initialize BO VA entry data structure 787 * 2. Add BO to the VM 788 * 3. Determine ASIC-specific PTE flags 789 * 4. Alloc page tables and directories if needed 790 * 4a. Validate new page tables and directories 791 */ 792 static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, 793 struct amdgpu_vm *vm, bool is_aql) 794 { 795 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); 796 unsigned long bo_size = mem->bo->tbo.base.size; 797 uint64_t va = mem->va; 798 struct kfd_mem_attachment *attachment[2] = {NULL, NULL}; 799 struct amdgpu_bo *bo[2] = {NULL, NULL}; 800 bool same_hive = false; 801 int i, ret; 802 803 if (!va) { 804 pr_err("Invalid VA when adding BO to VM\n"); 805 return -EINVAL; 806 } 807 808 /* Determine access to VRAM, MMIO and DOORBELL BOs of peer devices 809 * 810 * The access path of MMIO and DOORBELL BOs of is always over PCIe. 811 * In contrast the access path of VRAM BOs depens upon the type of 812 * link that connects the peer device. Access over PCIe is allowed 813 * if peer device has large BAR. In contrast, access over xGMI is 814 * allowed for both small and large BAR configurations of peer device 815 */ 816 if ((adev != bo_adev) && 817 ((mem->domain == AMDGPU_GEM_DOMAIN_VRAM) || 818 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || 819 (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { 820 if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) 821 same_hive = amdgpu_xgmi_same_hive(adev, bo_adev); 822 if (!same_hive && !amdgpu_device_is_peer_accessible(bo_adev, adev)) 823 return -EINVAL; 824 } 825 826 for (i = 0; i <= is_aql; i++) { 827 attachment[i] = kzalloc(sizeof(*attachment[i]), GFP_KERNEL); 828 if (unlikely(!attachment[i])) { 829 ret = -ENOMEM; 830 goto unwind; 831 } 832 833 pr_debug("\t add VA 0x%llx - 0x%llx to vm %p\n", va, 834 va + bo_size, vm); 835 836 if ((adev == bo_adev && !(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) || 837 (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && reuse_dmamap(adev, bo_adev)) || 838 same_hive) { 839 /* Mappings on the local GPU, or VRAM mappings in the 840 * local hive, or userptr mapping can reuse dma map 841 * address space share the original BO 842 */ 843 attachment[i]->type = KFD_MEM_ATT_SHARED; 844 bo[i] = mem->bo; 845 drm_gem_object_get(&bo[i]->tbo.base); 846 } else if (i > 0) { 847 /* Multiple mappings on the same GPU share the BO */ 848 attachment[i]->type = KFD_MEM_ATT_SHARED; 849 bo[i] = bo[0]; 850 drm_gem_object_get(&bo[i]->tbo.base); 851 } else if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 852 /* Create an SG BO to DMA-map userptrs on other GPUs */ 853 attachment[i]->type = KFD_MEM_ATT_USERPTR; 854 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 855 if (ret) 856 goto unwind; 857 /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ 858 } else if (mem->bo->tbo.type == ttm_bo_type_sg) { 859 WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || 860 mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), 861 "Handing invalid SG BO in ATTACH request"); 862 attachment[i]->type = KFD_MEM_ATT_SG; 863 ret = create_dmamap_sg_bo(adev, mem, &bo[i]); 864 if (ret) 865 goto unwind; 866 /* Enable acces to GTT and VRAM BOs of peer devices */ 867 } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || 868 mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { 869 attachment[i]->type = KFD_MEM_ATT_DMABUF; 870 ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); 871 if (ret) 872 goto unwind; 873 pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); 874 } else { 875 WARN_ONCE(true, "Handling invalid ATTACH request"); 876 ret = -EINVAL; 877 goto unwind; 878 } 879 880 /* Add BO to VM internal data structures */ 881 ret = amdgpu_bo_reserve(bo[i], false); 882 if (ret) { 883 pr_debug("Unable to reserve BO during memory attach"); 884 goto unwind; 885 } 886 attachment[i]->bo_va = amdgpu_vm_bo_add(adev, vm, bo[i]); 887 amdgpu_bo_unreserve(bo[i]); 888 if (unlikely(!attachment[i]->bo_va)) { 889 ret = -ENOMEM; 890 pr_err("Failed to add BO object to VM. ret == %d\n", 891 ret); 892 goto unwind; 893 } 894 attachment[i]->va = va; 895 attachment[i]->pte_flags = get_pte_flags(adev, mem); 896 attachment[i]->adev = adev; 897 list_add(&attachment[i]->list, &mem->attachments); 898 899 va += bo_size; 900 } 901 902 return 0; 903 904 unwind: 905 for (; i >= 0; i--) { 906 if (!attachment[i]) 907 continue; 908 if (attachment[i]->bo_va) { 909 amdgpu_bo_reserve(bo[i], true); 910 amdgpu_vm_bo_del(adev, attachment[i]->bo_va); 911 amdgpu_bo_unreserve(bo[i]); 912 list_del(&attachment[i]->list); 913 } 914 if (bo[i]) 915 drm_gem_object_put(&bo[i]->tbo.base); 916 kfree(attachment[i]); 917 } 918 return ret; 919 } 920 921 static void kfd_mem_detach(struct kfd_mem_attachment *attachment) 922 { 923 struct amdgpu_bo *bo = attachment->bo_va->base.bo; 924 925 pr_debug("\t remove VA 0x%llx in entry %p\n", 926 attachment->va, attachment); 927 amdgpu_vm_bo_del(attachment->adev, attachment->bo_va); 928 drm_gem_object_put(&bo->tbo.base); 929 list_del(&attachment->list); 930 kfree(attachment); 931 } 932 933 static void add_kgd_mem_to_kfd_bo_list(struct kgd_mem *mem, 934 struct amdkfd_process_info *process_info, 935 bool userptr) 936 { 937 struct ttm_validate_buffer *entry = &mem->validate_list; 938 struct amdgpu_bo *bo = mem->bo; 939 940 INIT_LIST_HEAD(&entry->head); 941 entry->num_shared = 1; 942 entry->bo = &bo->tbo; 943 mutex_lock(&process_info->lock); 944 if (userptr) 945 list_add_tail(&entry->head, &process_info->userptr_valid_list); 946 else 947 list_add_tail(&entry->head, &process_info->kfd_bo_list); 948 mutex_unlock(&process_info->lock); 949 } 950 951 static void remove_kgd_mem_from_kfd_bo_list(struct kgd_mem *mem, 952 struct amdkfd_process_info *process_info) 953 { 954 struct ttm_validate_buffer *bo_list_entry; 955 956 bo_list_entry = &mem->validate_list; 957 mutex_lock(&process_info->lock); 958 list_del(&bo_list_entry->head); 959 mutex_unlock(&process_info->lock); 960 } 961 962 /* Initializes user pages. It registers the MMU notifier and validates 963 * the userptr BO in the GTT domain. 964 * 965 * The BO must already be on the userptr_valid_list. Otherwise an 966 * eviction and restore may happen that leaves the new BO unmapped 967 * with the user mode queues running. 968 * 969 * Takes the process_info->lock to protect against concurrent restore 970 * workers. 971 * 972 * Returns 0 for success, negative errno for errors. 973 */ 974 static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, 975 bool criu_resume) 976 { 977 struct amdkfd_process_info *process_info = mem->process_info; 978 struct amdgpu_bo *bo = mem->bo; 979 struct ttm_operation_ctx ctx = { true, false }; 980 struct hmm_range *range; 981 int ret = 0; 982 983 mutex_lock(&process_info->lock); 984 985 ret = amdgpu_ttm_tt_set_userptr(&bo->tbo, user_addr, 0); 986 if (ret) { 987 pr_err("%s: Failed to set userptr: %d\n", __func__, ret); 988 goto out; 989 } 990 991 ret = amdgpu_hmm_register(bo, user_addr); 992 if (ret) { 993 pr_err("%s: Failed to register MMU notifier: %d\n", 994 __func__, ret); 995 goto out; 996 } 997 998 if (criu_resume) { 999 /* 1000 * During a CRIU restore operation, the userptr buffer objects 1001 * will be validated in the restore_userptr_work worker at a 1002 * later stage when it is scheduled by another ioctl called by 1003 * CRIU master process for the target pid for restore. 1004 */ 1005 mutex_lock(&process_info->notifier_lock); 1006 mem->invalid++; 1007 mutex_unlock(&process_info->notifier_lock); 1008 mutex_unlock(&process_info->lock); 1009 return 0; 1010 } 1011 1012 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); 1013 if (ret) { 1014 pr_err("%s: Failed to get user pages: %d\n", __func__, ret); 1015 goto unregister_out; 1016 } 1017 1018 ret = amdgpu_bo_reserve(bo, true); 1019 if (ret) { 1020 pr_err("%s: Failed to reserve BO\n", __func__); 1021 goto release_out; 1022 } 1023 amdgpu_bo_placement_from_domain(bo, mem->domain); 1024 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1025 if (ret) 1026 pr_err("%s: failed to validate BO\n", __func__); 1027 amdgpu_bo_unreserve(bo); 1028 1029 release_out: 1030 amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); 1031 unregister_out: 1032 if (ret) 1033 amdgpu_hmm_unregister(bo); 1034 out: 1035 mutex_unlock(&process_info->lock); 1036 return ret; 1037 } 1038 1039 /* Reserving a BO and its page table BOs must happen atomically to 1040 * avoid deadlocks. Some operations update multiple VMs at once. Track 1041 * all the reservation info in a context structure. Optionally a sync 1042 * object can track VM updates. 1043 */ 1044 struct bo_vm_reservation_context { 1045 struct amdgpu_bo_list_entry kfd_bo; /* BO list entry for the KFD BO */ 1046 unsigned int n_vms; /* Number of VMs reserved */ 1047 struct amdgpu_bo_list_entry *vm_pd; /* Array of VM BO list entries */ 1048 struct ww_acquire_ctx ticket; /* Reservation ticket */ 1049 struct list_head list, duplicates; /* BO lists */ 1050 struct amdgpu_sync *sync; /* Pointer to sync object */ 1051 bool reserved; /* Whether BOs are reserved */ 1052 }; 1053 1054 enum bo_vm_match { 1055 BO_VM_NOT_MAPPED = 0, /* Match VMs where a BO is not mapped */ 1056 BO_VM_MAPPED, /* Match VMs where a BO is mapped */ 1057 BO_VM_ALL, /* Match all VMs a BO was added to */ 1058 }; 1059 1060 /** 1061 * reserve_bo_and_vm - reserve a BO and a VM unconditionally. 1062 * @mem: KFD BO structure. 1063 * @vm: the VM to reserve. 1064 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1065 */ 1066 static int reserve_bo_and_vm(struct kgd_mem *mem, 1067 struct amdgpu_vm *vm, 1068 struct bo_vm_reservation_context *ctx) 1069 { 1070 struct amdgpu_bo *bo = mem->bo; 1071 int ret; 1072 1073 WARN_ON(!vm); 1074 1075 ctx->reserved = false; 1076 ctx->n_vms = 1; 1077 ctx->sync = &mem->sync; 1078 1079 INIT_LIST_HEAD(&ctx->list); 1080 INIT_LIST_HEAD(&ctx->duplicates); 1081 1082 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), GFP_KERNEL); 1083 if (!ctx->vm_pd) 1084 return -ENOMEM; 1085 1086 ctx->kfd_bo.priority = 0; 1087 ctx->kfd_bo.tv.bo = &bo->tbo; 1088 ctx->kfd_bo.tv.num_shared = 1; 1089 list_add(&ctx->kfd_bo.tv.head, &ctx->list); 1090 1091 amdgpu_vm_get_pd_bo(vm, &ctx->list, &ctx->vm_pd[0]); 1092 1093 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list, 1094 false, &ctx->duplicates); 1095 if (ret) { 1096 pr_err("Failed to reserve buffers in ttm.\n"); 1097 kfree(ctx->vm_pd); 1098 ctx->vm_pd = NULL; 1099 return ret; 1100 } 1101 1102 ctx->reserved = true; 1103 return 0; 1104 } 1105 1106 /** 1107 * reserve_bo_and_cond_vms - reserve a BO and some VMs conditionally 1108 * @mem: KFD BO structure. 1109 * @vm: the VM to reserve. If NULL, then all VMs associated with the BO 1110 * is used. Otherwise, a single VM associated with the BO. 1111 * @map_type: the mapping status that will be used to filter the VMs. 1112 * @ctx: the struct that will be used in unreserve_bo_and_vms(). 1113 * 1114 * Returns 0 for success, negative for failure. 1115 */ 1116 static int reserve_bo_and_cond_vms(struct kgd_mem *mem, 1117 struct amdgpu_vm *vm, enum bo_vm_match map_type, 1118 struct bo_vm_reservation_context *ctx) 1119 { 1120 struct amdgpu_bo *bo = mem->bo; 1121 struct kfd_mem_attachment *entry; 1122 unsigned int i; 1123 int ret; 1124 1125 ctx->reserved = false; 1126 ctx->n_vms = 0; 1127 ctx->vm_pd = NULL; 1128 ctx->sync = &mem->sync; 1129 1130 INIT_LIST_HEAD(&ctx->list); 1131 INIT_LIST_HEAD(&ctx->duplicates); 1132 1133 list_for_each_entry(entry, &mem->attachments, list) { 1134 if ((vm && vm != entry->bo_va->base.vm) || 1135 (entry->is_mapped != map_type 1136 && map_type != BO_VM_ALL)) 1137 continue; 1138 1139 ctx->n_vms++; 1140 } 1141 1142 if (ctx->n_vms != 0) { 1143 ctx->vm_pd = kcalloc(ctx->n_vms, sizeof(*ctx->vm_pd), 1144 GFP_KERNEL); 1145 if (!ctx->vm_pd) 1146 return -ENOMEM; 1147 } 1148 1149 ctx->kfd_bo.priority = 0; 1150 ctx->kfd_bo.tv.bo = &bo->tbo; 1151 ctx->kfd_bo.tv.num_shared = 1; 1152 list_add(&ctx->kfd_bo.tv.head, &ctx->list); 1153 1154 i = 0; 1155 list_for_each_entry(entry, &mem->attachments, list) { 1156 if ((vm && vm != entry->bo_va->base.vm) || 1157 (entry->is_mapped != map_type 1158 && map_type != BO_VM_ALL)) 1159 continue; 1160 1161 amdgpu_vm_get_pd_bo(entry->bo_va->base.vm, &ctx->list, 1162 &ctx->vm_pd[i]); 1163 i++; 1164 } 1165 1166 ret = ttm_eu_reserve_buffers(&ctx->ticket, &ctx->list, 1167 false, &ctx->duplicates); 1168 if (ret) { 1169 pr_err("Failed to reserve buffers in ttm.\n"); 1170 kfree(ctx->vm_pd); 1171 ctx->vm_pd = NULL; 1172 return ret; 1173 } 1174 1175 ctx->reserved = true; 1176 return 0; 1177 } 1178 1179 /** 1180 * unreserve_bo_and_vms - Unreserve BO and VMs from a reservation context 1181 * @ctx: Reservation context to unreserve 1182 * @wait: Optionally wait for a sync object representing pending VM updates 1183 * @intr: Whether the wait is interruptible 1184 * 1185 * Also frees any resources allocated in 1186 * reserve_bo_and_(cond_)vm(s). Returns the status from 1187 * amdgpu_sync_wait. 1188 */ 1189 static int unreserve_bo_and_vms(struct bo_vm_reservation_context *ctx, 1190 bool wait, bool intr) 1191 { 1192 int ret = 0; 1193 1194 if (wait) 1195 ret = amdgpu_sync_wait(ctx->sync, intr); 1196 1197 if (ctx->reserved) 1198 ttm_eu_backoff_reservation(&ctx->ticket, &ctx->list); 1199 kfree(ctx->vm_pd); 1200 1201 ctx->sync = NULL; 1202 1203 ctx->reserved = false; 1204 ctx->vm_pd = NULL; 1205 1206 return ret; 1207 } 1208 1209 static void unmap_bo_from_gpuvm(struct kgd_mem *mem, 1210 struct kfd_mem_attachment *entry, 1211 struct amdgpu_sync *sync) 1212 { 1213 struct amdgpu_bo_va *bo_va = entry->bo_va; 1214 struct amdgpu_device *adev = entry->adev; 1215 struct amdgpu_vm *vm = bo_va->base.vm; 1216 1217 amdgpu_vm_bo_unmap(adev, bo_va, entry->va); 1218 1219 amdgpu_vm_clear_freed(adev, vm, &bo_va->last_pt_update); 1220 1221 amdgpu_sync_fence(sync, bo_va->last_pt_update); 1222 1223 kfd_mem_dmaunmap_attachment(mem, entry); 1224 } 1225 1226 static int update_gpuvm_pte(struct kgd_mem *mem, 1227 struct kfd_mem_attachment *entry, 1228 struct amdgpu_sync *sync) 1229 { 1230 struct amdgpu_bo_va *bo_va = entry->bo_va; 1231 struct amdgpu_device *adev = entry->adev; 1232 int ret; 1233 1234 ret = kfd_mem_dmamap_attachment(mem, entry); 1235 if (ret) 1236 return ret; 1237 1238 /* Update the page tables */ 1239 ret = amdgpu_vm_bo_update(adev, bo_va, false); 1240 if (ret) { 1241 pr_err("amdgpu_vm_bo_update failed\n"); 1242 return ret; 1243 } 1244 1245 return amdgpu_sync_fence(sync, bo_va->last_pt_update); 1246 } 1247 1248 static int map_bo_to_gpuvm(struct kgd_mem *mem, 1249 struct kfd_mem_attachment *entry, 1250 struct amdgpu_sync *sync, 1251 bool no_update_pte) 1252 { 1253 int ret; 1254 1255 /* Set virtual address for the allocation */ 1256 ret = amdgpu_vm_bo_map(entry->adev, entry->bo_va, entry->va, 0, 1257 amdgpu_bo_size(entry->bo_va->base.bo), 1258 entry->pte_flags); 1259 if (ret) { 1260 pr_err("Failed to map VA 0x%llx in vm. ret %d\n", 1261 entry->va, ret); 1262 return ret; 1263 } 1264 1265 if (no_update_pte) 1266 return 0; 1267 1268 ret = update_gpuvm_pte(mem, entry, sync); 1269 if (ret) { 1270 pr_err("update_gpuvm_pte() failed\n"); 1271 goto update_gpuvm_pte_failed; 1272 } 1273 1274 return 0; 1275 1276 update_gpuvm_pte_failed: 1277 unmap_bo_from_gpuvm(mem, entry, sync); 1278 return ret; 1279 } 1280 1281 static int process_validate_vms(struct amdkfd_process_info *process_info) 1282 { 1283 struct amdgpu_vm *peer_vm; 1284 int ret; 1285 1286 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1287 vm_list_node) { 1288 ret = vm_validate_pt_pd_bos(peer_vm); 1289 if (ret) 1290 return ret; 1291 } 1292 1293 return 0; 1294 } 1295 1296 static int process_sync_pds_resv(struct amdkfd_process_info *process_info, 1297 struct amdgpu_sync *sync) 1298 { 1299 struct amdgpu_vm *peer_vm; 1300 int ret; 1301 1302 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1303 vm_list_node) { 1304 struct amdgpu_bo *pd = peer_vm->root.bo; 1305 1306 ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, 1307 AMDGPU_SYNC_NE_OWNER, 1308 AMDGPU_FENCE_OWNER_KFD); 1309 if (ret) 1310 return ret; 1311 } 1312 1313 return 0; 1314 } 1315 1316 static int process_update_pds(struct amdkfd_process_info *process_info, 1317 struct amdgpu_sync *sync) 1318 { 1319 struct amdgpu_vm *peer_vm; 1320 int ret; 1321 1322 list_for_each_entry(peer_vm, &process_info->vm_list_head, 1323 vm_list_node) { 1324 ret = vm_update_pds(peer_vm, sync); 1325 if (ret) 1326 return ret; 1327 } 1328 1329 return 0; 1330 } 1331 1332 static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, 1333 struct dma_fence **ef) 1334 { 1335 struct amdkfd_process_info *info = NULL; 1336 int ret; 1337 1338 if (!*process_info) { 1339 info = kzalloc(sizeof(*info), GFP_KERNEL); 1340 if (!info) 1341 return -ENOMEM; 1342 1343 mutex_init(&info->lock); 1344 mutex_init(&info->notifier_lock); 1345 INIT_LIST_HEAD(&info->vm_list_head); 1346 INIT_LIST_HEAD(&info->kfd_bo_list); 1347 INIT_LIST_HEAD(&info->userptr_valid_list); 1348 INIT_LIST_HEAD(&info->userptr_inval_list); 1349 1350 info->eviction_fence = 1351 amdgpu_amdkfd_fence_create(dma_fence_context_alloc(1), 1352 current->mm, 1353 NULL); 1354 if (!info->eviction_fence) { 1355 pr_err("Failed to create eviction fence\n"); 1356 ret = -ENOMEM; 1357 goto create_evict_fence_fail; 1358 } 1359 1360 info->pid = get_task_pid(current->group_leader, PIDTYPE_PID); 1361 INIT_DELAYED_WORK(&info->restore_userptr_work, 1362 amdgpu_amdkfd_restore_userptr_worker); 1363 1364 *process_info = info; 1365 *ef = dma_fence_get(&info->eviction_fence->base); 1366 } 1367 1368 vm->process_info = *process_info; 1369 1370 /* Validate page directory and attach eviction fence */ 1371 ret = amdgpu_bo_reserve(vm->root.bo, true); 1372 if (ret) 1373 goto reserve_pd_fail; 1374 ret = vm_validate_pt_pd_bos(vm); 1375 if (ret) { 1376 pr_err("validate_pt_pd_bos() failed\n"); 1377 goto validate_pd_fail; 1378 } 1379 ret = amdgpu_bo_sync_wait(vm->root.bo, 1380 AMDGPU_FENCE_OWNER_KFD, false); 1381 if (ret) 1382 goto wait_pd_fail; 1383 ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); 1384 if (ret) 1385 goto reserve_shared_fail; 1386 dma_resv_add_fence(vm->root.bo->tbo.base.resv, 1387 &vm->process_info->eviction_fence->base, 1388 DMA_RESV_USAGE_BOOKKEEP); 1389 amdgpu_bo_unreserve(vm->root.bo); 1390 1391 /* Update process info */ 1392 mutex_lock(&vm->process_info->lock); 1393 list_add_tail(&vm->vm_list_node, 1394 &(vm->process_info->vm_list_head)); 1395 vm->process_info->n_vms++; 1396 mutex_unlock(&vm->process_info->lock); 1397 1398 return 0; 1399 1400 reserve_shared_fail: 1401 wait_pd_fail: 1402 validate_pd_fail: 1403 amdgpu_bo_unreserve(vm->root.bo); 1404 reserve_pd_fail: 1405 vm->process_info = NULL; 1406 if (info) { 1407 /* Two fence references: one in info and one in *ef */ 1408 dma_fence_put(&info->eviction_fence->base); 1409 dma_fence_put(*ef); 1410 *ef = NULL; 1411 *process_info = NULL; 1412 put_pid(info->pid); 1413 create_evict_fence_fail: 1414 mutex_destroy(&info->lock); 1415 mutex_destroy(&info->notifier_lock); 1416 kfree(info); 1417 } 1418 return ret; 1419 } 1420 1421 /** 1422 * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria 1423 * @bo: Handle of buffer object being pinned 1424 * @domain: Domain into which BO should be pinned 1425 * 1426 * - USERPTR BOs are UNPINNABLE and will return error 1427 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1428 * PIN count incremented. It is valid to PIN a BO multiple times 1429 * 1430 * Return: ZERO if successful in pinning, Non-Zero in case of error. 1431 */ 1432 static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) 1433 { 1434 int ret = 0; 1435 1436 ret = amdgpu_bo_reserve(bo, false); 1437 if (unlikely(ret)) 1438 return ret; 1439 1440 ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0); 1441 if (ret) 1442 pr_err("Error in Pinning BO to domain: %d\n", domain); 1443 1444 amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); 1445 amdgpu_bo_unreserve(bo); 1446 1447 return ret; 1448 } 1449 1450 /** 1451 * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria 1452 * @bo: Handle of buffer object being unpinned 1453 * 1454 * - Is a illegal request for USERPTR BOs and is ignored 1455 * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their 1456 * PIN count decremented. Calls to UNPIN must balance calls to PIN 1457 */ 1458 static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) 1459 { 1460 int ret = 0; 1461 1462 ret = amdgpu_bo_reserve(bo, false); 1463 if (unlikely(ret)) 1464 return; 1465 1466 amdgpu_bo_unpin(bo); 1467 amdgpu_bo_unreserve(bo); 1468 } 1469 1470 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev, 1471 struct amdgpu_vm *avm, u32 pasid) 1472 1473 { 1474 int ret; 1475 1476 /* Free the original amdgpu allocated pasid, 1477 * will be replaced with kfd allocated pasid. 1478 */ 1479 if (avm->pasid) { 1480 amdgpu_pasid_free(avm->pasid); 1481 amdgpu_vm_set_pasid(adev, avm, 0); 1482 } 1483 1484 ret = amdgpu_vm_set_pasid(adev, avm, pasid); 1485 if (ret) 1486 return ret; 1487 1488 return 0; 1489 } 1490 1491 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 1492 struct amdgpu_vm *avm, 1493 void **process_info, 1494 struct dma_fence **ef) 1495 { 1496 int ret; 1497 1498 /* Already a compute VM? */ 1499 if (avm->process_info) 1500 return -EINVAL; 1501 1502 /* Convert VM into a compute VM */ 1503 ret = amdgpu_vm_make_compute(adev, avm); 1504 if (ret) 1505 return ret; 1506 1507 /* Initialize KFD part of the VM and process info */ 1508 ret = init_kfd_vm(avm, process_info, ef); 1509 if (ret) 1510 return ret; 1511 1512 amdgpu_vm_set_task_info(avm); 1513 1514 return 0; 1515 } 1516 1517 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 1518 struct amdgpu_vm *vm) 1519 { 1520 struct amdkfd_process_info *process_info = vm->process_info; 1521 1522 if (!process_info) 1523 return; 1524 1525 /* Update process info */ 1526 mutex_lock(&process_info->lock); 1527 process_info->n_vms--; 1528 list_del(&vm->vm_list_node); 1529 mutex_unlock(&process_info->lock); 1530 1531 vm->process_info = NULL; 1532 1533 /* Release per-process resources when last compute VM is destroyed */ 1534 if (!process_info->n_vms) { 1535 WARN_ON(!list_empty(&process_info->kfd_bo_list)); 1536 WARN_ON(!list_empty(&process_info->userptr_valid_list)); 1537 WARN_ON(!list_empty(&process_info->userptr_inval_list)); 1538 1539 dma_fence_put(&process_info->eviction_fence->base); 1540 cancel_delayed_work_sync(&process_info->restore_userptr_work); 1541 put_pid(process_info->pid); 1542 mutex_destroy(&process_info->lock); 1543 mutex_destroy(&process_info->notifier_lock); 1544 kfree(process_info); 1545 } 1546 } 1547 1548 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 1549 void *drm_priv) 1550 { 1551 struct amdgpu_vm *avm; 1552 1553 if (WARN_ON(!adev || !drm_priv)) 1554 return; 1555 1556 avm = drm_priv_to_vm(drm_priv); 1557 1558 pr_debug("Releasing process vm %p\n", avm); 1559 1560 /* The original pasid of amdgpu vm has already been 1561 * released during making a amdgpu vm to a compute vm 1562 * The current pasid is managed by kfd and will be 1563 * released on kfd process destroy. Set amdgpu pasid 1564 * to 0 to avoid duplicate release. 1565 */ 1566 amdgpu_vm_release_compute(adev, avm); 1567 } 1568 1569 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv) 1570 { 1571 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1572 struct amdgpu_bo *pd = avm->root.bo; 1573 struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev); 1574 1575 if (adev->asic_type < CHIP_VEGA10) 1576 return avm->pd_phys_addr >> AMDGPU_GPU_PAGE_SHIFT; 1577 return avm->pd_phys_addr; 1578 } 1579 1580 void amdgpu_amdkfd_block_mmu_notifications(void *p) 1581 { 1582 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1583 1584 mutex_lock(&pinfo->lock); 1585 WRITE_ONCE(pinfo->block_mmu_notifications, true); 1586 mutex_unlock(&pinfo->lock); 1587 } 1588 1589 int amdgpu_amdkfd_criu_resume(void *p) 1590 { 1591 int ret = 0; 1592 struct amdkfd_process_info *pinfo = (struct amdkfd_process_info *)p; 1593 1594 mutex_lock(&pinfo->lock); 1595 pr_debug("scheduling work\n"); 1596 mutex_lock(&pinfo->notifier_lock); 1597 pinfo->evicted_bos++; 1598 mutex_unlock(&pinfo->notifier_lock); 1599 if (!READ_ONCE(pinfo->block_mmu_notifications)) { 1600 ret = -EINVAL; 1601 goto out_unlock; 1602 } 1603 WRITE_ONCE(pinfo->block_mmu_notifications, false); 1604 schedule_delayed_work(&pinfo->restore_userptr_work, 0); 1605 1606 out_unlock: 1607 mutex_unlock(&pinfo->lock); 1608 return ret; 1609 } 1610 1611 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev) 1612 { 1613 uint64_t reserved_for_pt = 1614 ESTIMATE_PT_SIZE(amdgpu_amdkfd_total_mem_size); 1615 ssize_t available; 1616 1617 spin_lock(&kfd_mem_limit.mem_limit_lock); 1618 available = adev->gmc.real_vram_size 1619 - adev->kfd.vram_used_aligned 1620 - atomic64_read(&adev->vram_pin_size) 1621 - reserved_for_pt; 1622 spin_unlock(&kfd_mem_limit.mem_limit_lock); 1623 1624 if (available < 0) 1625 available = 0; 1626 1627 return ALIGN_DOWN(available, VRAM_AVAILABLITY_ALIGN); 1628 } 1629 1630 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 1631 struct amdgpu_device *adev, uint64_t va, uint64_t size, 1632 void *drm_priv, struct kgd_mem **mem, 1633 uint64_t *offset, uint32_t flags, bool criu_resume) 1634 { 1635 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1636 enum ttm_bo_type bo_type = ttm_bo_type_device; 1637 struct sg_table *sg = NULL; 1638 uint64_t user_addr = 0; 1639 struct amdgpu_bo *bo; 1640 struct drm_gem_object *gobj = NULL; 1641 u32 domain, alloc_domain; 1642 uint64_t aligned_size; 1643 u64 alloc_flags; 1644 int ret; 1645 1646 /* 1647 * Check on which domain to allocate BO 1648 */ 1649 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { 1650 domain = alloc_domain = AMDGPU_GEM_DOMAIN_VRAM; 1651 alloc_flags = AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; 1652 alloc_flags |= (flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) ? 1653 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED : 0; 1654 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) { 1655 domain = alloc_domain = AMDGPU_GEM_DOMAIN_GTT; 1656 alloc_flags = 0; 1657 } else { 1658 domain = AMDGPU_GEM_DOMAIN_GTT; 1659 alloc_domain = AMDGPU_GEM_DOMAIN_CPU; 1660 alloc_flags = AMDGPU_GEM_CREATE_PREEMPTIBLE; 1661 1662 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { 1663 if (!offset || !*offset) 1664 return -EINVAL; 1665 user_addr = untagged_addr(*offset); 1666 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1667 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1668 bo_type = ttm_bo_type_sg; 1669 if (size > UINT_MAX) 1670 return -EINVAL; 1671 sg = create_sg_table(*offset, size); 1672 if (!sg) 1673 return -ENOMEM; 1674 } else { 1675 return -EINVAL; 1676 } 1677 } 1678 1679 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_COHERENT) 1680 alloc_flags |= AMDGPU_GEM_CREATE_COHERENT; 1681 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) 1682 alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; 1683 1684 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 1685 if (!*mem) { 1686 ret = -ENOMEM; 1687 goto err; 1688 } 1689 INIT_LIST_HEAD(&(*mem)->attachments); 1690 mutex_init(&(*mem)->lock); 1691 (*mem)->aql_queue = !!(flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM); 1692 1693 /* Workaround for AQL queue wraparound bug. Map the same 1694 * memory twice. That means we only actually allocate half 1695 * the memory. 1696 */ 1697 if ((*mem)->aql_queue) 1698 size >>= 1; 1699 aligned_size = PAGE_ALIGN(size); 1700 1701 (*mem)->alloc_flags = flags; 1702 1703 amdgpu_sync_create(&(*mem)->sync); 1704 1705 ret = amdgpu_amdkfd_reserve_mem_limit(adev, aligned_size, flags); 1706 if (ret) { 1707 pr_debug("Insufficient memory\n"); 1708 goto err_reserve_limit; 1709 } 1710 1711 pr_debug("\tcreate BO VA 0x%llx size 0x%llx domain %s\n", 1712 va, (*mem)->aql_queue ? size << 1 : size, domain_string(alloc_domain)); 1713 1714 ret = amdgpu_gem_object_create(adev, aligned_size, 1, alloc_domain, alloc_flags, 1715 bo_type, NULL, &gobj); 1716 if (ret) { 1717 pr_debug("Failed to create BO on domain %s. ret %d\n", 1718 domain_string(alloc_domain), ret); 1719 goto err_bo_create; 1720 } 1721 ret = drm_vma_node_allow(&gobj->vma_node, drm_priv); 1722 if (ret) { 1723 pr_debug("Failed to allow vma node access. ret %d\n", ret); 1724 goto err_node_allow; 1725 } 1726 bo = gem_to_amdgpu_bo(gobj); 1727 if (bo_type == ttm_bo_type_sg) { 1728 bo->tbo.sg = sg; 1729 bo->tbo.ttm->sg = sg; 1730 } 1731 bo->kfd_bo = *mem; 1732 (*mem)->bo = bo; 1733 if (user_addr) 1734 bo->flags |= AMDGPU_AMDKFD_CREATE_USERPTR_BO; 1735 1736 (*mem)->va = va; 1737 (*mem)->domain = domain; 1738 (*mem)->mapped_to_gpu_memory = 0; 1739 (*mem)->process_info = avm->process_info; 1740 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr); 1741 1742 if (user_addr) { 1743 pr_debug("creating userptr BO for user_addr = %llx\n", user_addr); 1744 ret = init_user_pages(*mem, user_addr, criu_resume); 1745 if (ret) 1746 goto allocate_init_user_pages_failed; 1747 } else if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1748 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1749 ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); 1750 if (ret) { 1751 pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); 1752 goto err_pin_bo; 1753 } 1754 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; 1755 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; 1756 } 1757 1758 if (offset) 1759 *offset = amdgpu_bo_mmap_offset(bo); 1760 1761 return 0; 1762 1763 allocate_init_user_pages_failed: 1764 err_pin_bo: 1765 remove_kgd_mem_from_kfd_bo_list(*mem, avm->process_info); 1766 drm_vma_node_revoke(&gobj->vma_node, drm_priv); 1767 err_node_allow: 1768 /* Don't unreserve system mem limit twice */ 1769 goto err_reserve_limit; 1770 err_bo_create: 1771 amdgpu_amdkfd_unreserve_mem_limit(adev, aligned_size, flags); 1772 err_reserve_limit: 1773 mutex_destroy(&(*mem)->lock); 1774 if (gobj) 1775 drm_gem_object_put(gobj); 1776 else 1777 kfree(*mem); 1778 err: 1779 if (sg) { 1780 sg_free_table(sg); 1781 kfree(sg); 1782 } 1783 return ret; 1784 } 1785 1786 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 1787 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 1788 uint64_t *size) 1789 { 1790 struct amdkfd_process_info *process_info = mem->process_info; 1791 unsigned long bo_size = mem->bo->tbo.base.size; 1792 bool use_release_notifier = (mem->bo->kfd_bo == mem); 1793 struct kfd_mem_attachment *entry, *tmp; 1794 struct bo_vm_reservation_context ctx; 1795 struct ttm_validate_buffer *bo_list_entry; 1796 unsigned int mapped_to_gpu_memory; 1797 int ret; 1798 bool is_imported = false; 1799 1800 mutex_lock(&mem->lock); 1801 1802 /* Unpin MMIO/DOORBELL BO's that were pinned during allocation */ 1803 if (mem->alloc_flags & 1804 (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | 1805 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { 1806 amdgpu_amdkfd_gpuvm_unpin_bo(mem->bo); 1807 } 1808 1809 mapped_to_gpu_memory = mem->mapped_to_gpu_memory; 1810 is_imported = mem->is_imported; 1811 mutex_unlock(&mem->lock); 1812 /* lock is not needed after this, since mem is unused and will 1813 * be freed anyway 1814 */ 1815 1816 if (mapped_to_gpu_memory > 0) { 1817 pr_debug("BO VA 0x%llx size 0x%lx is still mapped.\n", 1818 mem->va, bo_size); 1819 return -EBUSY; 1820 } 1821 1822 /* Make sure restore workers don't access the BO any more */ 1823 bo_list_entry = &mem->validate_list; 1824 mutex_lock(&process_info->lock); 1825 list_del(&bo_list_entry->head); 1826 mutex_unlock(&process_info->lock); 1827 1828 /* Cleanup user pages and MMU notifiers */ 1829 if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { 1830 amdgpu_hmm_unregister(mem->bo); 1831 mutex_lock(&process_info->notifier_lock); 1832 amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); 1833 mutex_unlock(&process_info->notifier_lock); 1834 } 1835 1836 ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); 1837 if (unlikely(ret)) 1838 return ret; 1839 1840 /* The eviction fence should be removed by the last unmap. 1841 * TODO: Log an error condition if the bo still has the eviction fence 1842 * attached 1843 */ 1844 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 1845 process_info->eviction_fence); 1846 pr_debug("Release VA 0x%llx - 0x%llx\n", mem->va, 1847 mem->va + bo_size * (1 + mem->aql_queue)); 1848 1849 /* Remove from VM internal data structures */ 1850 list_for_each_entry_safe(entry, tmp, &mem->attachments, list) 1851 kfd_mem_detach(entry); 1852 1853 ret = unreserve_bo_and_vms(&ctx, false, false); 1854 1855 /* Free the sync object */ 1856 amdgpu_sync_free(&mem->sync); 1857 1858 /* If the SG is not NULL, it's one we created for a doorbell or mmio 1859 * remap BO. We need to free it. 1860 */ 1861 if (mem->bo->tbo.sg) { 1862 sg_free_table(mem->bo->tbo.sg); 1863 kfree(mem->bo->tbo.sg); 1864 } 1865 1866 /* Update the size of the BO being freed if it was allocated from 1867 * VRAM and is not imported. 1868 */ 1869 if (size) { 1870 if ((mem->bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) && 1871 (!is_imported)) 1872 *size = bo_size; 1873 else 1874 *size = 0; 1875 } 1876 1877 /* Free the BO*/ 1878 drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); 1879 if (mem->dmabuf) 1880 dma_buf_put(mem->dmabuf); 1881 mutex_destroy(&mem->lock); 1882 1883 /* If this releases the last reference, it will end up calling 1884 * amdgpu_amdkfd_release_notify and kfree the mem struct. That's why 1885 * this needs to be the last call here. 1886 */ 1887 drm_gem_object_put(&mem->bo->tbo.base); 1888 1889 /* 1890 * For kgd_mem allocated in amdgpu_amdkfd_gpuvm_import_dmabuf(), 1891 * explicitly free it here. 1892 */ 1893 if (!use_release_notifier) 1894 kfree(mem); 1895 1896 return ret; 1897 } 1898 1899 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 1900 struct amdgpu_device *adev, struct kgd_mem *mem, 1901 void *drm_priv) 1902 { 1903 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 1904 int ret; 1905 struct amdgpu_bo *bo; 1906 uint32_t domain; 1907 struct kfd_mem_attachment *entry; 1908 struct bo_vm_reservation_context ctx; 1909 unsigned long bo_size; 1910 bool is_invalid_userptr = false; 1911 1912 bo = mem->bo; 1913 if (!bo) { 1914 pr_err("Invalid BO when mapping memory to GPU\n"); 1915 return -EINVAL; 1916 } 1917 1918 /* Make sure restore is not running concurrently. Since we 1919 * don't map invalid userptr BOs, we rely on the next restore 1920 * worker to do the mapping 1921 */ 1922 mutex_lock(&mem->process_info->lock); 1923 1924 /* Lock notifier lock. If we find an invalid userptr BO, we can be 1925 * sure that the MMU notifier is no longer running 1926 * concurrently and the queues are actually stopped 1927 */ 1928 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 1929 mutex_lock(&mem->process_info->notifier_lock); 1930 is_invalid_userptr = !!mem->invalid; 1931 mutex_unlock(&mem->process_info->notifier_lock); 1932 } 1933 1934 mutex_lock(&mem->lock); 1935 1936 domain = mem->domain; 1937 bo_size = bo->tbo.base.size; 1938 1939 pr_debug("Map VA 0x%llx - 0x%llx to vm %p domain %s\n", 1940 mem->va, 1941 mem->va + bo_size * (1 + mem->aql_queue), 1942 avm, domain_string(domain)); 1943 1944 if (!kfd_mem_is_attached(avm, mem)) { 1945 ret = kfd_mem_attach(adev, mem, avm, mem->aql_queue); 1946 if (ret) 1947 goto out; 1948 } 1949 1950 ret = reserve_bo_and_vm(mem, avm, &ctx); 1951 if (unlikely(ret)) 1952 goto out; 1953 1954 /* Userptr can be marked as "not invalid", but not actually be 1955 * validated yet (still in the system domain). In that case 1956 * the queues are still stopped and we can leave mapping for 1957 * the next restore worker 1958 */ 1959 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && 1960 bo->tbo.resource->mem_type == TTM_PL_SYSTEM) 1961 is_invalid_userptr = true; 1962 1963 ret = vm_validate_pt_pd_bos(avm); 1964 if (unlikely(ret)) 1965 goto out_unreserve; 1966 1967 if (mem->mapped_to_gpu_memory == 0 && 1968 !amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 1969 /* Validate BO only once. The eviction fence gets added to BO 1970 * the first time it is mapped. Validate will wait for all 1971 * background evictions to complete. 1972 */ 1973 ret = amdgpu_amdkfd_bo_validate(bo, domain, true); 1974 if (ret) { 1975 pr_debug("Validate failed\n"); 1976 goto out_unreserve; 1977 } 1978 } 1979 1980 list_for_each_entry(entry, &mem->attachments, list) { 1981 if (entry->bo_va->base.vm != avm || entry->is_mapped) 1982 continue; 1983 1984 pr_debug("\t map VA 0x%llx - 0x%llx in entry %p\n", 1985 entry->va, entry->va + bo_size, entry); 1986 1987 ret = map_bo_to_gpuvm(mem, entry, ctx.sync, 1988 is_invalid_userptr); 1989 if (ret) { 1990 pr_err("Failed to map bo to gpuvm\n"); 1991 goto out_unreserve; 1992 } 1993 1994 ret = vm_update_pds(avm, ctx.sync); 1995 if (ret) { 1996 pr_err("Failed to update page directories\n"); 1997 goto out_unreserve; 1998 } 1999 2000 entry->is_mapped = true; 2001 mem->mapped_to_gpu_memory++; 2002 pr_debug("\t INC mapping count %d\n", 2003 mem->mapped_to_gpu_memory); 2004 } 2005 2006 if (!amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) && !bo->tbo.pin_count) 2007 dma_resv_add_fence(bo->tbo.base.resv, 2008 &avm->process_info->eviction_fence->base, 2009 DMA_RESV_USAGE_BOOKKEEP); 2010 ret = unreserve_bo_and_vms(&ctx, false, false); 2011 2012 goto out; 2013 2014 out_unreserve: 2015 unreserve_bo_and_vms(&ctx, false, false); 2016 out: 2017 mutex_unlock(&mem->process_info->lock); 2018 mutex_unlock(&mem->lock); 2019 return ret; 2020 } 2021 2022 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 2023 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv) 2024 { 2025 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2026 struct amdkfd_process_info *process_info = avm->process_info; 2027 unsigned long bo_size = mem->bo->tbo.base.size; 2028 struct kfd_mem_attachment *entry; 2029 struct bo_vm_reservation_context ctx; 2030 int ret; 2031 2032 mutex_lock(&mem->lock); 2033 2034 ret = reserve_bo_and_cond_vms(mem, avm, BO_VM_MAPPED, &ctx); 2035 if (unlikely(ret)) 2036 goto out; 2037 /* If no VMs were reserved, it means the BO wasn't actually mapped */ 2038 if (ctx.n_vms == 0) { 2039 ret = -EINVAL; 2040 goto unreserve_out; 2041 } 2042 2043 ret = vm_validate_pt_pd_bos(avm); 2044 if (unlikely(ret)) 2045 goto unreserve_out; 2046 2047 pr_debug("Unmap VA 0x%llx - 0x%llx from vm %p\n", 2048 mem->va, 2049 mem->va + bo_size * (1 + mem->aql_queue), 2050 avm); 2051 2052 list_for_each_entry(entry, &mem->attachments, list) { 2053 if (entry->bo_va->base.vm != avm || !entry->is_mapped) 2054 continue; 2055 2056 pr_debug("\t unmap VA 0x%llx - 0x%llx from entry %p\n", 2057 entry->va, entry->va + bo_size, entry); 2058 2059 unmap_bo_from_gpuvm(mem, entry, ctx.sync); 2060 entry->is_mapped = false; 2061 2062 mem->mapped_to_gpu_memory--; 2063 pr_debug("\t DEC mapping count %d\n", 2064 mem->mapped_to_gpu_memory); 2065 } 2066 2067 /* If BO is unmapped from all VMs, unfence it. It can be evicted if 2068 * required. 2069 */ 2070 if (mem->mapped_to_gpu_memory == 0 && 2071 !amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm) && 2072 !mem->bo->tbo.pin_count) 2073 amdgpu_amdkfd_remove_eviction_fence(mem->bo, 2074 process_info->eviction_fence); 2075 2076 unreserve_out: 2077 unreserve_bo_and_vms(&ctx, false, false); 2078 out: 2079 mutex_unlock(&mem->lock); 2080 return ret; 2081 } 2082 2083 int amdgpu_amdkfd_gpuvm_sync_memory( 2084 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr) 2085 { 2086 struct amdgpu_sync sync; 2087 int ret; 2088 2089 amdgpu_sync_create(&sync); 2090 2091 mutex_lock(&mem->lock); 2092 amdgpu_sync_clone(&mem->sync, &sync); 2093 mutex_unlock(&mem->lock); 2094 2095 ret = amdgpu_sync_wait(&sync, intr); 2096 amdgpu_sync_free(&sync); 2097 return ret; 2098 } 2099 2100 /** 2101 * amdgpu_amdkfd_map_gtt_bo_to_gart - Map BO to GART and increment reference count 2102 * @adev: Device to which allocated BO belongs 2103 * @bo: Buffer object to be mapped 2104 * 2105 * Before return, bo reference count is incremented. To release the reference and unpin/ 2106 * unmap the BO, call amdgpu_amdkfd_free_gtt_mem. 2107 */ 2108 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo) 2109 { 2110 int ret; 2111 2112 ret = amdgpu_bo_reserve(bo, true); 2113 if (ret) { 2114 pr_err("Failed to reserve bo. ret %d\n", ret); 2115 goto err_reserve_bo_failed; 2116 } 2117 2118 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2119 if (ret) { 2120 pr_err("Failed to pin bo. ret %d\n", ret); 2121 goto err_pin_bo_failed; 2122 } 2123 2124 ret = amdgpu_ttm_alloc_gart(&bo->tbo); 2125 if (ret) { 2126 pr_err("Failed to bind bo to GART. ret %d\n", ret); 2127 goto err_map_bo_gart_failed; 2128 } 2129 2130 amdgpu_amdkfd_remove_eviction_fence( 2131 bo, bo->vm_bo->vm->process_info->eviction_fence); 2132 2133 amdgpu_bo_unreserve(bo); 2134 2135 bo = amdgpu_bo_ref(bo); 2136 2137 return 0; 2138 2139 err_map_bo_gart_failed: 2140 amdgpu_bo_unpin(bo); 2141 err_pin_bo_failed: 2142 amdgpu_bo_unreserve(bo); 2143 err_reserve_bo_failed: 2144 2145 return ret; 2146 } 2147 2148 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Map a GTT BO for kernel CPU access 2149 * 2150 * @mem: Buffer object to be mapped for CPU access 2151 * @kptr[out]: pointer in kernel CPU address space 2152 * @size[out]: size of the buffer 2153 * 2154 * Pins the BO and maps it for kernel CPU access. The eviction fence is removed 2155 * from the BO, since pinned BOs cannot be evicted. The bo must remain on the 2156 * validate_list, so the GPU mapping can be restored after a page table was 2157 * evicted. 2158 * 2159 * Return: 0 on success, error code on failure 2160 */ 2161 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 2162 void **kptr, uint64_t *size) 2163 { 2164 int ret; 2165 struct amdgpu_bo *bo = mem->bo; 2166 2167 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) { 2168 pr_err("userptr can't be mapped to kernel\n"); 2169 return -EINVAL; 2170 } 2171 2172 mutex_lock(&mem->process_info->lock); 2173 2174 ret = amdgpu_bo_reserve(bo, true); 2175 if (ret) { 2176 pr_err("Failed to reserve bo. ret %d\n", ret); 2177 goto bo_reserve_failed; 2178 } 2179 2180 ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 2181 if (ret) { 2182 pr_err("Failed to pin bo. ret %d\n", ret); 2183 goto pin_failed; 2184 } 2185 2186 ret = amdgpu_bo_kmap(bo, kptr); 2187 if (ret) { 2188 pr_err("Failed to map bo to kernel. ret %d\n", ret); 2189 goto kmap_failed; 2190 } 2191 2192 amdgpu_amdkfd_remove_eviction_fence( 2193 bo, mem->process_info->eviction_fence); 2194 2195 if (size) 2196 *size = amdgpu_bo_size(bo); 2197 2198 amdgpu_bo_unreserve(bo); 2199 2200 mutex_unlock(&mem->process_info->lock); 2201 return 0; 2202 2203 kmap_failed: 2204 amdgpu_bo_unpin(bo); 2205 pin_failed: 2206 amdgpu_bo_unreserve(bo); 2207 bo_reserve_failed: 2208 mutex_unlock(&mem->process_info->lock); 2209 2210 return ret; 2211 } 2212 2213 /** amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel() - Unmap a GTT BO for kernel CPU access 2214 * 2215 * @mem: Buffer object to be unmapped for CPU access 2216 * 2217 * Removes the kernel CPU mapping and unpins the BO. It does not restore the 2218 * eviction fence, so this function should only be used for cleanup before the 2219 * BO is destroyed. 2220 */ 2221 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem) 2222 { 2223 struct amdgpu_bo *bo = mem->bo; 2224 2225 amdgpu_bo_reserve(bo, true); 2226 amdgpu_bo_kunmap(bo); 2227 amdgpu_bo_unpin(bo); 2228 amdgpu_bo_unreserve(bo); 2229 } 2230 2231 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 2232 struct kfd_vm_fault_info *mem) 2233 { 2234 if (atomic_read(&adev->gmc.vm_fault_info_updated) == 1) { 2235 *mem = *adev->gmc.vm_fault_info; 2236 mb(); /* make sure read happened */ 2237 atomic_set(&adev->gmc.vm_fault_info_updated, 0); 2238 } 2239 return 0; 2240 } 2241 2242 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 2243 struct dma_buf *dma_buf, 2244 uint64_t va, void *drm_priv, 2245 struct kgd_mem **mem, uint64_t *size, 2246 uint64_t *mmap_offset) 2247 { 2248 struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); 2249 struct drm_gem_object *obj; 2250 struct amdgpu_bo *bo; 2251 int ret; 2252 2253 obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); 2254 if (IS_ERR(obj)) 2255 return PTR_ERR(obj); 2256 2257 bo = gem_to_amdgpu_bo(obj); 2258 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 2259 AMDGPU_GEM_DOMAIN_GTT))) { 2260 /* Only VRAM and GTT BOs are supported */ 2261 ret = -EINVAL; 2262 goto err_put_obj; 2263 } 2264 2265 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 2266 if (!*mem) { 2267 ret = -ENOMEM; 2268 goto err_put_obj; 2269 } 2270 2271 ret = drm_vma_node_allow(&obj->vma_node, drm_priv); 2272 if (ret) 2273 goto err_free_mem; 2274 2275 if (size) 2276 *size = amdgpu_bo_size(bo); 2277 2278 if (mmap_offset) 2279 *mmap_offset = amdgpu_bo_mmap_offset(bo); 2280 2281 INIT_LIST_HEAD(&(*mem)->attachments); 2282 mutex_init(&(*mem)->lock); 2283 2284 (*mem)->alloc_flags = 2285 ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 2286 KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) 2287 | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE 2288 | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; 2289 2290 get_dma_buf(dma_buf); 2291 (*mem)->dmabuf = dma_buf; 2292 (*mem)->bo = bo; 2293 (*mem)->va = va; 2294 (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 2295 AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT; 2296 (*mem)->mapped_to_gpu_memory = 0; 2297 (*mem)->process_info = avm->process_info; 2298 add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, false); 2299 amdgpu_sync_create(&(*mem)->sync); 2300 (*mem)->is_imported = true; 2301 2302 return 0; 2303 2304 err_free_mem: 2305 kfree(*mem); 2306 err_put_obj: 2307 drm_gem_object_put(obj); 2308 return ret; 2309 } 2310 2311 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 2312 struct dma_buf **dma_buf) 2313 { 2314 int ret; 2315 2316 mutex_lock(&mem->lock); 2317 ret = kfd_mem_export_dmabuf(mem); 2318 if (ret) 2319 goto out; 2320 2321 get_dma_buf(mem->dmabuf); 2322 *dma_buf = mem->dmabuf; 2323 out: 2324 mutex_unlock(&mem->lock); 2325 return ret; 2326 } 2327 2328 /* Evict a userptr BO by stopping the queues if necessary 2329 * 2330 * Runs in MMU notifier, may be in RECLAIM_FS context. This means it 2331 * cannot do any memory allocations, and cannot take any locks that 2332 * are held elsewhere while allocating memory. 2333 * 2334 * It doesn't do anything to the BO itself. The real work happens in 2335 * restore, where we get updated page addresses. This function only 2336 * ensures that GPU access to the BO is stopped. 2337 */ 2338 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 2339 unsigned long cur_seq, struct kgd_mem *mem) 2340 { 2341 struct amdkfd_process_info *process_info = mem->process_info; 2342 int r = 0; 2343 2344 /* Do not process MMU notifications during CRIU restore until 2345 * KFD_CRIU_OP_RESUME IOCTL is received 2346 */ 2347 if (READ_ONCE(process_info->block_mmu_notifications)) 2348 return 0; 2349 2350 mutex_lock(&process_info->notifier_lock); 2351 mmu_interval_set_seq(mni, cur_seq); 2352 2353 mem->invalid++; 2354 if (++process_info->evicted_bos == 1) { 2355 /* First eviction, stop the queues */ 2356 r = kgd2kfd_quiesce_mm(mni->mm, 2357 KFD_QUEUE_EVICTION_TRIGGER_USERPTR); 2358 if (r) 2359 pr_err("Failed to quiesce KFD\n"); 2360 schedule_delayed_work(&process_info->restore_userptr_work, 2361 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2362 } 2363 mutex_unlock(&process_info->notifier_lock); 2364 2365 return r; 2366 } 2367 2368 /* Update invalid userptr BOs 2369 * 2370 * Moves invalidated (evicted) userptr BOs from userptr_valid_list to 2371 * userptr_inval_list and updates user pages for all BOs that have 2372 * been invalidated since their last update. 2373 */ 2374 static int update_invalid_user_pages(struct amdkfd_process_info *process_info, 2375 struct mm_struct *mm) 2376 { 2377 struct kgd_mem *mem, *tmp_mem; 2378 struct amdgpu_bo *bo; 2379 struct ttm_operation_ctx ctx = { false, false }; 2380 uint32_t invalid; 2381 int ret = 0; 2382 2383 mutex_lock(&process_info->notifier_lock); 2384 2385 /* Move all invalidated BOs to the userptr_inval_list */ 2386 list_for_each_entry_safe(mem, tmp_mem, 2387 &process_info->userptr_valid_list, 2388 validate_list.head) 2389 if (mem->invalid) 2390 list_move_tail(&mem->validate_list.head, 2391 &process_info->userptr_inval_list); 2392 2393 /* Go through userptr_inval_list and update any invalid user_pages */ 2394 list_for_each_entry(mem, &process_info->userptr_inval_list, 2395 validate_list.head) { 2396 invalid = mem->invalid; 2397 if (!invalid) 2398 /* BO hasn't been invalidated since the last 2399 * revalidation attempt. Keep its page list. 2400 */ 2401 continue; 2402 2403 bo = mem->bo; 2404 2405 amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); 2406 mem->range = NULL; 2407 2408 /* BO reservations and getting user pages (hmm_range_fault) 2409 * must happen outside the notifier lock 2410 */ 2411 mutex_unlock(&process_info->notifier_lock); 2412 2413 /* Move the BO to system (CPU) domain if necessary to unmap 2414 * and free the SG table 2415 */ 2416 if (bo->tbo.resource->mem_type != TTM_PL_SYSTEM) { 2417 if (amdgpu_bo_reserve(bo, true)) 2418 return -EAGAIN; 2419 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU); 2420 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2421 amdgpu_bo_unreserve(bo); 2422 if (ret) { 2423 pr_err("%s: Failed to invalidate userptr BO\n", 2424 __func__); 2425 return -EAGAIN; 2426 } 2427 } 2428 2429 /* Get updated user pages */ 2430 ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, 2431 &mem->range); 2432 if (ret) { 2433 pr_debug("Failed %d to get user pages\n", ret); 2434 2435 /* Return -EFAULT bad address error as success. It will 2436 * fail later with a VM fault if the GPU tries to access 2437 * it. Better than hanging indefinitely with stalled 2438 * user mode queues. 2439 * 2440 * Return other error -EBUSY or -ENOMEM to retry restore 2441 */ 2442 if (ret != -EFAULT) 2443 return ret; 2444 2445 ret = 0; 2446 } 2447 2448 mutex_lock(&process_info->notifier_lock); 2449 2450 /* Mark the BO as valid unless it was invalidated 2451 * again concurrently. 2452 */ 2453 if (mem->invalid != invalid) { 2454 ret = -EAGAIN; 2455 goto unlock_out; 2456 } 2457 /* set mem valid if mem has hmm range associated */ 2458 if (mem->range) 2459 mem->invalid = 0; 2460 } 2461 2462 unlock_out: 2463 mutex_unlock(&process_info->notifier_lock); 2464 2465 return ret; 2466 } 2467 2468 /* Validate invalid userptr BOs 2469 * 2470 * Validates BOs on the userptr_inval_list. Also updates GPUVM page tables 2471 * with new page addresses and waits for the page table updates to complete. 2472 */ 2473 static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) 2474 { 2475 struct amdgpu_bo_list_entry *pd_bo_list_entries; 2476 struct list_head resv_list, duplicates; 2477 struct ww_acquire_ctx ticket; 2478 struct amdgpu_sync sync; 2479 2480 struct amdgpu_vm *peer_vm; 2481 struct kgd_mem *mem, *tmp_mem; 2482 struct amdgpu_bo *bo; 2483 struct ttm_operation_ctx ctx = { false, false }; 2484 int i, ret; 2485 2486 pd_bo_list_entries = kcalloc(process_info->n_vms, 2487 sizeof(struct amdgpu_bo_list_entry), 2488 GFP_KERNEL); 2489 if (!pd_bo_list_entries) { 2490 pr_err("%s: Failed to allocate PD BO list entries\n", __func__); 2491 ret = -ENOMEM; 2492 goto out_no_mem; 2493 } 2494 2495 INIT_LIST_HEAD(&resv_list); 2496 INIT_LIST_HEAD(&duplicates); 2497 2498 /* Get all the page directory BOs that need to be reserved */ 2499 i = 0; 2500 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2501 vm_list_node) 2502 amdgpu_vm_get_pd_bo(peer_vm, &resv_list, 2503 &pd_bo_list_entries[i++]); 2504 /* Add the userptr_inval_list entries to resv_list */ 2505 list_for_each_entry(mem, &process_info->userptr_inval_list, 2506 validate_list.head) { 2507 list_add_tail(&mem->resv_list.head, &resv_list); 2508 mem->resv_list.bo = mem->validate_list.bo; 2509 mem->resv_list.num_shared = mem->validate_list.num_shared; 2510 } 2511 2512 /* Reserve all BOs and page tables for validation */ 2513 ret = ttm_eu_reserve_buffers(&ticket, &resv_list, false, &duplicates); 2514 WARN(!list_empty(&duplicates), "Duplicates should be empty"); 2515 if (ret) 2516 goto out_free; 2517 2518 amdgpu_sync_create(&sync); 2519 2520 ret = process_validate_vms(process_info); 2521 if (ret) 2522 goto unreserve_out; 2523 2524 /* Validate BOs and update GPUVM page tables */ 2525 list_for_each_entry_safe(mem, tmp_mem, 2526 &process_info->userptr_inval_list, 2527 validate_list.head) { 2528 struct kfd_mem_attachment *attachment; 2529 2530 bo = mem->bo; 2531 2532 /* Validate the BO if we got user pages */ 2533 if (bo->tbo.ttm->pages[0]) { 2534 amdgpu_bo_placement_from_domain(bo, mem->domain); 2535 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 2536 if (ret) { 2537 pr_err("%s: failed to validate BO\n", __func__); 2538 goto unreserve_out; 2539 } 2540 } 2541 2542 /* Update mapping. If the BO was not validated 2543 * (because we couldn't get user pages), this will 2544 * clear the page table entries, which will result in 2545 * VM faults if the GPU tries to access the invalid 2546 * memory. 2547 */ 2548 list_for_each_entry(attachment, &mem->attachments, list) { 2549 if (!attachment->is_mapped) 2550 continue; 2551 2552 kfd_mem_dmaunmap_attachment(mem, attachment); 2553 ret = update_gpuvm_pte(mem, attachment, &sync); 2554 if (ret) { 2555 pr_err("%s: update PTE failed\n", __func__); 2556 /* make sure this gets validated again */ 2557 mutex_lock(&process_info->notifier_lock); 2558 mem->invalid++; 2559 mutex_unlock(&process_info->notifier_lock); 2560 goto unreserve_out; 2561 } 2562 } 2563 } 2564 2565 /* Update page directories */ 2566 ret = process_update_pds(process_info, &sync); 2567 2568 unreserve_out: 2569 ttm_eu_backoff_reservation(&ticket, &resv_list); 2570 amdgpu_sync_wait(&sync, false); 2571 amdgpu_sync_free(&sync); 2572 out_free: 2573 kfree(pd_bo_list_entries); 2574 out_no_mem: 2575 2576 return ret; 2577 } 2578 2579 /* Confirm that all user pages are valid while holding the notifier lock 2580 * 2581 * Moves valid BOs from the userptr_inval_list back to userptr_val_list. 2582 */ 2583 static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_info) 2584 { 2585 struct kgd_mem *mem, *tmp_mem; 2586 int ret = 0; 2587 2588 list_for_each_entry_safe(mem, tmp_mem, 2589 &process_info->userptr_inval_list, 2590 validate_list.head) { 2591 bool valid; 2592 2593 /* keep mem without hmm range at userptr_inval_list */ 2594 if (!mem->range) 2595 continue; 2596 2597 /* Only check mem with hmm range associated */ 2598 valid = amdgpu_ttm_tt_get_user_pages_done( 2599 mem->bo->tbo.ttm, mem->range); 2600 2601 mem->range = NULL; 2602 if (!valid) { 2603 WARN(!mem->invalid, "Invalid BO not marked invalid"); 2604 ret = -EAGAIN; 2605 continue; 2606 } 2607 2608 if (mem->invalid) { 2609 WARN(1, "Valid BO is marked invalid"); 2610 ret = -EAGAIN; 2611 continue; 2612 } 2613 2614 list_move_tail(&mem->validate_list.head, 2615 &process_info->userptr_valid_list); 2616 } 2617 2618 return ret; 2619 } 2620 2621 /* Worker callback to restore evicted userptr BOs 2622 * 2623 * Tries to update and validate all userptr BOs. If successful and no 2624 * concurrent evictions happened, the queues are restarted. Otherwise, 2625 * reschedule for another attempt later. 2626 */ 2627 static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work) 2628 { 2629 struct delayed_work *dwork = to_delayed_work(work); 2630 struct amdkfd_process_info *process_info = 2631 container_of(dwork, struct amdkfd_process_info, 2632 restore_userptr_work); 2633 struct task_struct *usertask; 2634 struct mm_struct *mm; 2635 uint32_t evicted_bos; 2636 2637 mutex_lock(&process_info->notifier_lock); 2638 evicted_bos = process_info->evicted_bos; 2639 mutex_unlock(&process_info->notifier_lock); 2640 if (!evicted_bos) 2641 return; 2642 2643 /* Reference task and mm in case of concurrent process termination */ 2644 usertask = get_pid_task(process_info->pid, PIDTYPE_PID); 2645 if (!usertask) 2646 return; 2647 mm = get_task_mm(usertask); 2648 if (!mm) { 2649 put_task_struct(usertask); 2650 return; 2651 } 2652 2653 mutex_lock(&process_info->lock); 2654 2655 if (update_invalid_user_pages(process_info, mm)) 2656 goto unlock_out; 2657 /* userptr_inval_list can be empty if all evicted userptr BOs 2658 * have been freed. In that case there is nothing to validate 2659 * and we can just restart the queues. 2660 */ 2661 if (!list_empty(&process_info->userptr_inval_list)) { 2662 if (validate_invalid_user_pages(process_info)) 2663 goto unlock_out; 2664 } 2665 /* Final check for concurrent evicton and atomic update. If 2666 * another eviction happens after successful update, it will 2667 * be a first eviction that calls quiesce_mm. The eviction 2668 * reference counting inside KFD will handle this case. 2669 */ 2670 mutex_lock(&process_info->notifier_lock); 2671 if (process_info->evicted_bos != evicted_bos) 2672 goto unlock_notifier_out; 2673 2674 if (confirm_valid_user_pages_locked(process_info)) { 2675 WARN(1, "User pages unexpectedly invalid"); 2676 goto unlock_notifier_out; 2677 } 2678 2679 process_info->evicted_bos = evicted_bos = 0; 2680 2681 if (kgd2kfd_resume_mm(mm)) { 2682 pr_err("%s: Failed to resume KFD\n", __func__); 2683 /* No recovery from this failure. Probably the CP is 2684 * hanging. No point trying again. 2685 */ 2686 } 2687 2688 unlock_notifier_out: 2689 mutex_unlock(&process_info->notifier_lock); 2690 unlock_out: 2691 mutex_unlock(&process_info->lock); 2692 2693 /* If validation failed, reschedule another attempt */ 2694 if (evicted_bos) { 2695 schedule_delayed_work(&process_info->restore_userptr_work, 2696 msecs_to_jiffies(AMDGPU_USERPTR_RESTORE_DELAY_MS)); 2697 2698 kfd_smi_event_queue_restore_rescheduled(mm); 2699 } 2700 mmput(mm); 2701 put_task_struct(usertask); 2702 } 2703 2704 /** amdgpu_amdkfd_gpuvm_restore_process_bos - Restore all BOs for the given 2705 * KFD process identified by process_info 2706 * 2707 * @process_info: amdkfd_process_info of the KFD process 2708 * 2709 * After memory eviction, restore thread calls this function. The function 2710 * should be called when the Process is still valid. BO restore involves - 2711 * 2712 * 1. Release old eviction fence and create new one 2713 * 2. Get two copies of PD BO list from all the VMs. Keep one copy as pd_list. 2714 * 3 Use the second PD list and kfd_bo_list to create a list (ctx.list) of 2715 * BOs that need to be reserved. 2716 * 4. Reserve all the BOs 2717 * 5. Validate of PD and PT BOs. 2718 * 6. Validate all KFD BOs using kfd_bo_list and Map them and add new fence 2719 * 7. Add fence to all PD and PT BOs. 2720 * 8. Unreserve all BOs 2721 */ 2722 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) 2723 { 2724 struct amdgpu_bo_list_entry *pd_bo_list; 2725 struct amdkfd_process_info *process_info = info; 2726 struct amdgpu_vm *peer_vm; 2727 struct kgd_mem *mem; 2728 struct bo_vm_reservation_context ctx; 2729 struct amdgpu_amdkfd_fence *new_fence; 2730 int ret = 0, i; 2731 struct list_head duplicate_save; 2732 struct amdgpu_sync sync_obj; 2733 unsigned long failed_size = 0; 2734 unsigned long total_size = 0; 2735 2736 INIT_LIST_HEAD(&duplicate_save); 2737 INIT_LIST_HEAD(&ctx.list); 2738 INIT_LIST_HEAD(&ctx.duplicates); 2739 2740 pd_bo_list = kcalloc(process_info->n_vms, 2741 sizeof(struct amdgpu_bo_list_entry), 2742 GFP_KERNEL); 2743 if (!pd_bo_list) 2744 return -ENOMEM; 2745 2746 i = 0; 2747 mutex_lock(&process_info->lock); 2748 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2749 vm_list_node) 2750 amdgpu_vm_get_pd_bo(peer_vm, &ctx.list, &pd_bo_list[i++]); 2751 2752 /* Reserve all BOs and page tables/directory. Add all BOs from 2753 * kfd_bo_list to ctx.list 2754 */ 2755 list_for_each_entry(mem, &process_info->kfd_bo_list, 2756 validate_list.head) { 2757 2758 list_add_tail(&mem->resv_list.head, &ctx.list); 2759 mem->resv_list.bo = mem->validate_list.bo; 2760 mem->resv_list.num_shared = mem->validate_list.num_shared; 2761 } 2762 2763 ret = ttm_eu_reserve_buffers(&ctx.ticket, &ctx.list, 2764 false, &duplicate_save); 2765 if (ret) { 2766 pr_debug("Memory eviction: TTM Reserve Failed. Try again\n"); 2767 goto ttm_reserve_fail; 2768 } 2769 2770 amdgpu_sync_create(&sync_obj); 2771 2772 /* Validate PDs and PTs */ 2773 ret = process_validate_vms(process_info); 2774 if (ret) 2775 goto validate_map_fail; 2776 2777 ret = process_sync_pds_resv(process_info, &sync_obj); 2778 if (ret) { 2779 pr_debug("Memory eviction: Failed to sync to PD BO moving fence. Try again\n"); 2780 goto validate_map_fail; 2781 } 2782 2783 /* Validate BOs and map them to GPUVM (update VM page tables). */ 2784 list_for_each_entry(mem, &process_info->kfd_bo_list, 2785 validate_list.head) { 2786 2787 struct amdgpu_bo *bo = mem->bo; 2788 uint32_t domain = mem->domain; 2789 struct kfd_mem_attachment *attachment; 2790 struct dma_resv_iter cursor; 2791 struct dma_fence *fence; 2792 2793 total_size += amdgpu_bo_size(bo); 2794 2795 ret = amdgpu_amdkfd_bo_validate(bo, domain, false); 2796 if (ret) { 2797 pr_debug("Memory eviction: Validate BOs failed\n"); 2798 failed_size += amdgpu_bo_size(bo); 2799 ret = amdgpu_amdkfd_bo_validate(bo, 2800 AMDGPU_GEM_DOMAIN_GTT, false); 2801 if (ret) { 2802 pr_debug("Memory eviction: Try again\n"); 2803 goto validate_map_fail; 2804 } 2805 } 2806 dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, 2807 DMA_RESV_USAGE_KERNEL, fence) { 2808 ret = amdgpu_sync_fence(&sync_obj, fence); 2809 if (ret) { 2810 pr_debug("Memory eviction: Sync BO fence failed. Try again\n"); 2811 goto validate_map_fail; 2812 } 2813 } 2814 list_for_each_entry(attachment, &mem->attachments, list) { 2815 if (!attachment->is_mapped) 2816 continue; 2817 2818 kfd_mem_dmaunmap_attachment(mem, attachment); 2819 ret = update_gpuvm_pte(mem, attachment, &sync_obj); 2820 if (ret) { 2821 pr_debug("Memory eviction: update PTE failed. Try again\n"); 2822 goto validate_map_fail; 2823 } 2824 } 2825 } 2826 2827 if (failed_size) 2828 pr_debug("0x%lx/0x%lx in system\n", failed_size, total_size); 2829 2830 /* Update page directories */ 2831 ret = process_update_pds(process_info, &sync_obj); 2832 if (ret) { 2833 pr_debug("Memory eviction: update PDs failed. Try again\n"); 2834 goto validate_map_fail; 2835 } 2836 2837 /* Wait for validate and PT updates to finish */ 2838 amdgpu_sync_wait(&sync_obj, false); 2839 2840 /* Release old eviction fence and create new one, because fence only 2841 * goes from unsignaled to signaled, fence cannot be reused. 2842 * Use context and mm from the old fence. 2843 */ 2844 new_fence = amdgpu_amdkfd_fence_create( 2845 process_info->eviction_fence->base.context, 2846 process_info->eviction_fence->mm, 2847 NULL); 2848 if (!new_fence) { 2849 pr_err("Failed to create eviction fence\n"); 2850 ret = -ENOMEM; 2851 goto validate_map_fail; 2852 } 2853 dma_fence_put(&process_info->eviction_fence->base); 2854 process_info->eviction_fence = new_fence; 2855 *ef = dma_fence_get(&new_fence->base); 2856 2857 /* Attach new eviction fence to all BOs except pinned ones */ 2858 list_for_each_entry(mem, &process_info->kfd_bo_list, 2859 validate_list.head) { 2860 if (mem->bo->tbo.pin_count) 2861 continue; 2862 2863 dma_resv_add_fence(mem->bo->tbo.base.resv, 2864 &process_info->eviction_fence->base, 2865 DMA_RESV_USAGE_BOOKKEEP); 2866 } 2867 /* Attach eviction fence to PD / PT BOs */ 2868 list_for_each_entry(peer_vm, &process_info->vm_list_head, 2869 vm_list_node) { 2870 struct amdgpu_bo *bo = peer_vm->root.bo; 2871 2872 dma_resv_add_fence(bo->tbo.base.resv, 2873 &process_info->eviction_fence->base, 2874 DMA_RESV_USAGE_BOOKKEEP); 2875 } 2876 2877 validate_map_fail: 2878 ttm_eu_backoff_reservation(&ctx.ticket, &ctx.list); 2879 amdgpu_sync_free(&sync_obj); 2880 ttm_reserve_fail: 2881 mutex_unlock(&process_info->lock); 2882 kfree(pd_bo_list); 2883 return ret; 2884 } 2885 2886 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem) 2887 { 2888 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 2889 struct amdgpu_bo *gws_bo = (struct amdgpu_bo *)gws; 2890 int ret; 2891 2892 if (!info || !gws) 2893 return -EINVAL; 2894 2895 *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); 2896 if (!*mem) 2897 return -ENOMEM; 2898 2899 mutex_init(&(*mem)->lock); 2900 INIT_LIST_HEAD(&(*mem)->attachments); 2901 (*mem)->bo = amdgpu_bo_ref(gws_bo); 2902 (*mem)->domain = AMDGPU_GEM_DOMAIN_GWS; 2903 (*mem)->process_info = process_info; 2904 add_kgd_mem_to_kfd_bo_list(*mem, process_info, false); 2905 amdgpu_sync_create(&(*mem)->sync); 2906 2907 2908 /* Validate gws bo the first time it is added to process */ 2909 mutex_lock(&(*mem)->process_info->lock); 2910 ret = amdgpu_bo_reserve(gws_bo, false); 2911 if (unlikely(ret)) { 2912 pr_err("Reserve gws bo failed %d\n", ret); 2913 goto bo_reservation_failure; 2914 } 2915 2916 ret = amdgpu_amdkfd_bo_validate(gws_bo, AMDGPU_GEM_DOMAIN_GWS, true); 2917 if (ret) { 2918 pr_err("GWS BO validate failed %d\n", ret); 2919 goto bo_validation_failure; 2920 } 2921 /* GWS resource is shared b/t amdgpu and amdkfd 2922 * Add process eviction fence to bo so they can 2923 * evict each other. 2924 */ 2925 ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); 2926 if (ret) 2927 goto reserve_shared_fail; 2928 dma_resv_add_fence(gws_bo->tbo.base.resv, 2929 &process_info->eviction_fence->base, 2930 DMA_RESV_USAGE_BOOKKEEP); 2931 amdgpu_bo_unreserve(gws_bo); 2932 mutex_unlock(&(*mem)->process_info->lock); 2933 2934 return ret; 2935 2936 reserve_shared_fail: 2937 bo_validation_failure: 2938 amdgpu_bo_unreserve(gws_bo); 2939 bo_reservation_failure: 2940 mutex_unlock(&(*mem)->process_info->lock); 2941 amdgpu_sync_free(&(*mem)->sync); 2942 remove_kgd_mem_from_kfd_bo_list(*mem, process_info); 2943 amdgpu_bo_unref(&gws_bo); 2944 mutex_destroy(&(*mem)->lock); 2945 kfree(*mem); 2946 *mem = NULL; 2947 return ret; 2948 } 2949 2950 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) 2951 { 2952 int ret; 2953 struct amdkfd_process_info *process_info = (struct amdkfd_process_info *)info; 2954 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; 2955 struct amdgpu_bo *gws_bo = kgd_mem->bo; 2956 2957 /* Remove BO from process's validate list so restore worker won't touch 2958 * it anymore 2959 */ 2960 remove_kgd_mem_from_kfd_bo_list(kgd_mem, process_info); 2961 2962 ret = amdgpu_bo_reserve(gws_bo, false); 2963 if (unlikely(ret)) { 2964 pr_err("Reserve gws bo failed %d\n", ret); 2965 //TODO add BO back to validate_list? 2966 return ret; 2967 } 2968 amdgpu_amdkfd_remove_eviction_fence(gws_bo, 2969 process_info->eviction_fence); 2970 amdgpu_bo_unreserve(gws_bo); 2971 amdgpu_sync_free(&kgd_mem->sync); 2972 amdgpu_bo_unref(&gws_bo); 2973 mutex_destroy(&kgd_mem->lock); 2974 kfree(mem); 2975 return 0; 2976 } 2977 2978 /* Returns GPU-specific tiling mode information */ 2979 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 2980 struct tile_config *config) 2981 { 2982 config->gb_addr_config = adev->gfx.config.gb_addr_config; 2983 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 2984 config->num_tile_configs = 2985 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 2986 config->macro_tile_config_ptr = 2987 adev->gfx.config.macrotile_mode_array; 2988 config->num_macro_tile_configs = 2989 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 2990 2991 /* Those values are not set from GFX9 onwards */ 2992 config->num_banks = adev->gfx.config.num_banks; 2993 config->num_ranks = adev->gfx.config.num_ranks; 2994 2995 return 0; 2996 } 2997 2998 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem) 2999 { 3000 struct kfd_mem_attachment *entry; 3001 3002 list_for_each_entry(entry, &mem->attachments, list) { 3003 if (entry->is_mapped && entry->adev == adev) 3004 return true; 3005 } 3006 return false; 3007 } 3008 3009 #if defined(CONFIG_DEBUG_FS) 3010 3011 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data) 3012 { 3013 3014 spin_lock(&kfd_mem_limit.mem_limit_lock); 3015 seq_printf(m, "System mem used %lldM out of %lluM\n", 3016 (kfd_mem_limit.system_mem_used >> 20), 3017 (kfd_mem_limit.max_system_mem_limit >> 20)); 3018 seq_printf(m, "TTM mem used %lldM out of %lluM\n", 3019 (kfd_mem_limit.ttm_mem_used >> 20), 3020 (kfd_mem_limit.max_ttm_mem_limit >> 20)); 3021 spin_unlock(&kfd_mem_limit.mem_limit_lock); 3022 3023 return 0; 3024 } 3025 3026 #endif 3027