1 /* 2 * Copyright 2014-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define pr_fmt(fmt) "kfd2kgd: " fmt 24 25 #include <linux/mmu_context.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_amdkfd.h" 29 #include "gc/gc_9_0_offset.h" 30 #include "gc/gc_9_0_sh_mask.h" 31 #include "vega10_enum.h" 32 #include "sdma0/sdma0_4_0_offset.h" 33 #include "sdma0/sdma0_4_0_sh_mask.h" 34 #include "sdma1/sdma1_4_0_offset.h" 35 #include "sdma1/sdma1_4_0_sh_mask.h" 36 #include "athub/athub_1_0_offset.h" 37 #include "athub/athub_1_0_sh_mask.h" 38 #include "oss/osssys_4_0_offset.h" 39 #include "oss/osssys_4_0_sh_mask.h" 40 #include "soc15_common.h" 41 #include "v9_structs.h" 42 #include "soc15.h" 43 #include "soc15d.h" 44 #include "mmhub_v1_0.h" 45 #include "gfxhub_v1_0.h" 46 #include "gmc_v9_0.h" 47 48 49 enum hqd_dequeue_request_type { 50 NO_ACTION = 0, 51 DRAIN_PIPE, 52 RESET_WAVES 53 }; 54 55 56 /* Because of REG_GET_FIELD() being used, we put this function in the 57 * asic specific file. 58 */ 59 int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd, 60 struct tile_config *config) 61 { 62 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 63 64 config->gb_addr_config = adev->gfx.config.gb_addr_config; 65 66 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 67 config->num_tile_configs = 68 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 69 config->macro_tile_config_ptr = 70 adev->gfx.config.macrotile_mode_array; 71 config->num_macro_tile_configs = 72 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 73 74 return 0; 75 } 76 77 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 78 { 79 return (struct amdgpu_device *)kgd; 80 } 81 82 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 83 uint32_t queue, uint32_t vmid) 84 { 85 struct amdgpu_device *adev = get_amdgpu_device(kgd); 86 87 mutex_lock(&adev->srbm_mutex); 88 soc15_grbm_select(adev, mec, pipe, queue, vmid); 89 } 90 91 static void unlock_srbm(struct kgd_dev *kgd) 92 { 93 struct amdgpu_device *adev = get_amdgpu_device(kgd); 94 95 soc15_grbm_select(adev, 0, 0, 0, 0); 96 mutex_unlock(&adev->srbm_mutex); 97 } 98 99 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 100 uint32_t queue_id) 101 { 102 struct amdgpu_device *adev = get_amdgpu_device(kgd); 103 104 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 105 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 106 107 lock_srbm(kgd, mec, pipe, queue_id, 0); 108 } 109 110 static uint32_t get_queue_mask(struct amdgpu_device *adev, 111 uint32_t pipe_id, uint32_t queue_id) 112 { 113 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 114 queue_id) & 31; 115 116 return ((uint32_t)1) << bit; 117 } 118 119 static void release_queue(struct kgd_dev *kgd) 120 { 121 unlock_srbm(kgd); 122 } 123 124 void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 125 uint32_t sh_mem_config, 126 uint32_t sh_mem_ape1_base, 127 uint32_t sh_mem_ape1_limit, 128 uint32_t sh_mem_bases) 129 { 130 struct amdgpu_device *adev = get_amdgpu_device(kgd); 131 132 lock_srbm(kgd, 0, 0, 0, vmid); 133 134 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 135 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 136 /* APE1 no longer exists on GFX9 */ 137 138 unlock_srbm(kgd); 139 } 140 141 int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 142 unsigned int vmid) 143 { 144 struct amdgpu_device *adev = get_amdgpu_device(kgd); 145 146 /* 147 * We have to assume that there is no outstanding mapping. 148 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 149 * a mapping is in progress or because a mapping finished 150 * and the SW cleared it. 151 * So the protocol is to always wait & clear. 152 */ 153 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 154 ATC_VMID0_PASID_MAPPING__VALID_MASK; 155 156 /* 157 * need to do this twice, once for gfx and once for mmhub 158 * for ATC add 16 to VMID for mmhub, for IH different registers. 159 * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 160 */ 161 162 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 163 pasid_mapping); 164 165 while (!(RREG32(SOC15_REG_OFFSET( 166 ATHUB, 0, 167 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 168 (1U << vmid))) 169 cpu_relax(); 170 171 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 172 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 173 1U << vmid); 174 175 /* Mapping vmid to pasid also for IH block */ 176 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 177 pasid_mapping); 178 179 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 180 pasid_mapping); 181 182 while (!(RREG32(SOC15_REG_OFFSET( 183 ATHUB, 0, 184 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 185 (1U << (vmid + 16)))) 186 cpu_relax(); 187 188 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 189 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 190 1U << (vmid + 16)); 191 192 /* Mapping vmid to pasid also for IH block */ 193 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 194 pasid_mapping); 195 return 0; 196 } 197 198 /* TODO - RING0 form of field is obsolete, seems to date back to SI 199 * but still works 200 */ 201 202 int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 203 { 204 struct amdgpu_device *adev = get_amdgpu_device(kgd); 205 uint32_t mec; 206 uint32_t pipe; 207 208 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 209 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 210 211 lock_srbm(kgd, mec, pipe, 0, 0); 212 213 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 214 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 215 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 216 217 unlock_srbm(kgd); 218 219 return 0; 220 } 221 222 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 223 unsigned int engine_id, 224 unsigned int queue_id) 225 { 226 uint32_t sdma_engine_reg_base[2] = { 227 SOC15_REG_OFFSET(SDMA0, 0, 228 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 229 SOC15_REG_OFFSET(SDMA1, 0, 230 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 231 }; 232 uint32_t retval = sdma_engine_reg_base[engine_id] 233 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 234 235 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 236 queue_id, retval); 237 238 return retval; 239 } 240 241 static inline struct v9_mqd *get_mqd(void *mqd) 242 { 243 return (struct v9_mqd *)mqd; 244 } 245 246 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 247 { 248 return (struct v9_sdma_mqd *)mqd; 249 } 250 251 int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 252 uint32_t queue_id, uint32_t __user *wptr, 253 uint32_t wptr_shift, uint32_t wptr_mask, 254 struct mm_struct *mm) 255 { 256 struct amdgpu_device *adev = get_amdgpu_device(kgd); 257 struct v9_mqd *m; 258 uint32_t *mqd_hqd; 259 uint32_t reg, hqd_base, data; 260 261 m = get_mqd(mqd); 262 263 acquire_queue(kgd, pipe_id, queue_id); 264 265 /* HIQ is set during driver init period with vmid set to 0*/ 266 if (m->cp_hqd_vmid == 0) { 267 uint32_t value, mec, pipe; 268 269 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 270 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 271 272 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 273 mec, pipe, queue_id); 274 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 275 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 276 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 277 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 278 } 279 280 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 281 mqd_hqd = &m->cp_mqd_base_addr_lo; 282 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 283 284 for (reg = hqd_base; 285 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 286 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 287 288 289 /* Activate doorbell logic before triggering WPTR poll. */ 290 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 291 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 292 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 293 294 if (wptr) { 295 /* Don't read wptr with get_user because the user 296 * context may not be accessible (if this function 297 * runs in a work queue). Instead trigger a one-shot 298 * polling read from memory in the CP. This assumes 299 * that wptr is GPU-accessible in the queue's VMID via 300 * ATC or SVM. WPTR==RPTR before starting the poll so 301 * the CP starts fetching new commands from the right 302 * place. 303 * 304 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 305 * tricky. Assume that the queue didn't overflow. The 306 * number of valid bits in the 32-bit RPTR depends on 307 * the queue size. The remaining bits are taken from 308 * the saved 64-bit WPTR. If the WPTR wrapped, add the 309 * queue size. 310 */ 311 uint32_t queue_size = 312 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 313 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 314 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 315 316 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 317 guessed_wptr += queue_size; 318 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 319 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 320 321 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 322 lower_32_bits(guessed_wptr)); 323 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 324 upper_32_bits(guessed_wptr)); 325 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 326 lower_32_bits((uintptr_t)wptr)); 327 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 328 upper_32_bits((uintptr_t)wptr)); 329 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 330 get_queue_mask(adev, pipe_id, queue_id)); 331 } 332 333 /* Start the EOP fetcher */ 334 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 335 REG_SET_FIELD(m->cp_hqd_eop_rptr, 336 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 337 338 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 339 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 340 341 release_queue(kgd); 342 343 return 0; 344 } 345 346 int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd, 347 uint32_t pipe_id, uint32_t queue_id, 348 uint32_t (**dump)[2], uint32_t *n_regs) 349 { 350 struct amdgpu_device *adev = get_amdgpu_device(kgd); 351 uint32_t i = 0, reg; 352 #define HQD_N_REGS 56 353 #define DUMP_REG(addr) do { \ 354 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 355 break; \ 356 (*dump)[i][0] = (addr) << 2; \ 357 (*dump)[i++][1] = RREG32(addr); \ 358 } while (0) 359 360 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 361 if (*dump == NULL) 362 return -ENOMEM; 363 364 acquire_queue(kgd, pipe_id, queue_id); 365 366 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 367 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 368 DUMP_REG(reg); 369 370 release_queue(kgd); 371 372 WARN_ON_ONCE(i != HQD_N_REGS); 373 *n_regs = i; 374 375 return 0; 376 } 377 378 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 379 uint32_t __user *wptr, struct mm_struct *mm) 380 { 381 struct amdgpu_device *adev = get_amdgpu_device(kgd); 382 struct v9_sdma_mqd *m; 383 uint32_t sdma_rlc_reg_offset; 384 unsigned long end_jiffies; 385 uint32_t data; 386 uint64_t data64; 387 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 388 389 m = get_sdma_mqd(mqd); 390 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 391 m->sdma_queue_id); 392 393 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 394 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 395 396 end_jiffies = msecs_to_jiffies(2000) + jiffies; 397 while (true) { 398 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 399 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 400 break; 401 if (time_after(jiffies, end_jiffies)) { 402 pr_err("SDMA RLC not idle in %s\n", __func__); 403 return -ETIME; 404 } 405 usleep_range(500, 1000); 406 } 407 408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 409 m->sdmax_rlcx_doorbell_offset); 410 411 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 412 ENABLE, 1); 413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 414 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 415 m->sdmax_rlcx_rb_rptr); 416 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 417 m->sdmax_rlcx_rb_rptr_hi); 418 419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 420 if (read_user_wptr(mm, wptr64, data64)) { 421 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 422 lower_32_bits(data64)); 423 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 424 upper_32_bits(data64)); 425 } else { 426 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 427 m->sdmax_rlcx_rb_rptr); 428 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 429 m->sdmax_rlcx_rb_rptr_hi); 430 } 431 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 432 433 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 434 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 435 m->sdmax_rlcx_rb_base_hi); 436 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 437 m->sdmax_rlcx_rb_rptr_addr_lo); 438 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 439 m->sdmax_rlcx_rb_rptr_addr_hi); 440 441 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 442 RB_ENABLE, 1); 443 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 444 445 return 0; 446 } 447 448 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 449 uint32_t engine_id, uint32_t queue_id, 450 uint32_t (**dump)[2], uint32_t *n_regs) 451 { 452 struct amdgpu_device *adev = get_amdgpu_device(kgd); 453 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 454 engine_id, queue_id); 455 uint32_t i = 0, reg; 456 #undef HQD_N_REGS 457 #define HQD_N_REGS (19+6+7+10) 458 459 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 460 if (*dump == NULL) 461 return -ENOMEM; 462 463 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 464 DUMP_REG(sdma_rlc_reg_offset + reg); 465 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 466 DUMP_REG(sdma_rlc_reg_offset + reg); 467 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 468 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 469 DUMP_REG(sdma_rlc_reg_offset + reg); 470 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 471 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 472 DUMP_REG(sdma_rlc_reg_offset + reg); 473 474 WARN_ON_ONCE(i != HQD_N_REGS); 475 *n_regs = i; 476 477 return 0; 478 } 479 480 bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 481 uint32_t pipe_id, uint32_t queue_id) 482 { 483 struct amdgpu_device *adev = get_amdgpu_device(kgd); 484 uint32_t act; 485 bool retval = false; 486 uint32_t low, high; 487 488 acquire_queue(kgd, pipe_id, queue_id); 489 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 490 if (act) { 491 low = lower_32_bits(queue_address >> 8); 492 high = upper_32_bits(queue_address >> 8); 493 494 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 495 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 496 retval = true; 497 } 498 release_queue(kgd); 499 return retval; 500 } 501 502 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 503 { 504 struct amdgpu_device *adev = get_amdgpu_device(kgd); 505 struct v9_sdma_mqd *m; 506 uint32_t sdma_rlc_reg_offset; 507 uint32_t sdma_rlc_rb_cntl; 508 509 m = get_sdma_mqd(mqd); 510 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 511 m->sdma_queue_id); 512 513 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 514 515 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 516 return true; 517 518 return false; 519 } 520 521 int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd, 522 enum kfd_preempt_type reset_type, 523 unsigned int utimeout, uint32_t pipe_id, 524 uint32_t queue_id) 525 { 526 struct amdgpu_device *adev = get_amdgpu_device(kgd); 527 enum hqd_dequeue_request_type type; 528 unsigned long end_jiffies; 529 uint32_t temp; 530 struct v9_mqd *m = get_mqd(mqd); 531 532 if (adev->in_gpu_reset) 533 return -EIO; 534 535 acquire_queue(kgd, pipe_id, queue_id); 536 537 if (m->cp_hqd_vmid == 0) 538 WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 539 540 switch (reset_type) { 541 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 542 type = DRAIN_PIPE; 543 break; 544 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 545 type = RESET_WAVES; 546 break; 547 default: 548 type = DRAIN_PIPE; 549 break; 550 } 551 552 WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 553 554 end_jiffies = (utimeout * HZ / 1000) + jiffies; 555 while (true) { 556 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 557 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 558 break; 559 if (time_after(jiffies, end_jiffies)) { 560 pr_err("cp queue preemption time out.\n"); 561 release_queue(kgd); 562 return -ETIME; 563 } 564 usleep_range(500, 1000); 565 } 566 567 release_queue(kgd); 568 return 0; 569 } 570 571 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 572 unsigned int utimeout) 573 { 574 struct amdgpu_device *adev = get_amdgpu_device(kgd); 575 struct v9_sdma_mqd *m; 576 uint32_t sdma_rlc_reg_offset; 577 uint32_t temp; 578 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 579 580 m = get_sdma_mqd(mqd); 581 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 582 m->sdma_queue_id); 583 584 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 585 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 586 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 587 588 while (true) { 589 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 590 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 591 break; 592 if (time_after(jiffies, end_jiffies)) { 593 pr_err("SDMA RLC not idle in %s\n", __func__); 594 return -ETIME; 595 } 596 usleep_range(500, 1000); 597 } 598 599 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 600 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 601 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 602 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 603 604 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 605 m->sdmax_rlcx_rb_rptr_hi = 606 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 607 608 return 0; 609 } 610 611 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 612 uint8_t vmid, uint16_t *p_pasid) 613 { 614 uint32_t value; 615 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 616 617 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 618 + vmid); 619 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 620 621 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 622 } 623 624 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid, 625 uint32_t flush_type) 626 { 627 signed long r; 628 uint32_t seq; 629 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 630 631 spin_lock(&adev->gfx.kiq.ring_lock); 632 amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 633 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 634 amdgpu_ring_write(ring, 635 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 636 PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 637 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 638 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 639 amdgpu_fence_emit_polling(ring, &seq); 640 amdgpu_ring_commit(ring); 641 spin_unlock(&adev->gfx.kiq.ring_lock); 642 643 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 644 if (r < 1) { 645 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 646 return -ETIME; 647 } 648 649 return 0; 650 } 651 652 int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 653 { 654 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 655 int vmid, i; 656 uint16_t queried_pasid; 657 bool ret; 658 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 659 uint32_t flush_type = 0; 660 661 if (adev->in_gpu_reset) 662 return -EIO; 663 if (adev->gmc.xgmi.num_physical_nodes && 664 adev->asic_type == CHIP_VEGA20) 665 flush_type = 2; 666 667 if (ring->sched.ready) 668 return invalidate_tlbs_with_kiq(adev, pasid, flush_type); 669 670 for (vmid = 0; vmid < 16; vmid++) { 671 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 672 continue; 673 674 ret = kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(kgd, vmid, 675 &queried_pasid); 676 if (ret && queried_pasid == pasid) { 677 for (i = 0; i < adev->num_vmhubs; i++) 678 amdgpu_gmc_flush_gpu_tlb(adev, vmid, 679 i, flush_type); 680 break; 681 } 682 } 683 684 return 0; 685 } 686 687 int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 688 { 689 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 690 int i; 691 692 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 693 pr_err("non kfd vmid %d\n", vmid); 694 return 0; 695 } 696 697 /* Use legacy mode tlb invalidation. 698 * 699 * Currently on Raven the code below is broken for anything but 700 * legacy mode due to a MMHUB power gating problem. A workaround 701 * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 702 * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 703 * bit. 704 * 705 * TODO 1: agree on the right set of invalidation registers for 706 * KFD use. Use the last one for now. Invalidate both GC and 707 * MMHUB. 708 * 709 * TODO 2: support range-based invalidation, requires kfg2kgd 710 * interface change 711 */ 712 for (i = 0; i < adev->num_vmhubs; i++) 713 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 714 715 return 0; 716 } 717 718 int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd) 719 { 720 return 0; 721 } 722 723 int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd, 724 unsigned int watch_point_id, 725 uint32_t cntl_val, 726 uint32_t addr_hi, 727 uint32_t addr_lo) 728 { 729 return 0; 730 } 731 732 int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd, 733 uint32_t gfx_index_val, 734 uint32_t sq_cmd) 735 { 736 struct amdgpu_device *adev = get_amdgpu_device(kgd); 737 uint32_t data = 0; 738 739 mutex_lock(&adev->grbm_idx_mutex); 740 741 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); 742 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 743 744 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 745 INSTANCE_BROADCAST_WRITES, 1); 746 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 747 SH_BROADCAST_WRITES, 1); 748 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 749 SE_BROADCAST_WRITES, 1); 750 751 WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 752 mutex_unlock(&adev->grbm_idx_mutex); 753 754 return 0; 755 } 756 757 uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, 758 unsigned int watch_point_id, 759 unsigned int reg_offset) 760 { 761 return 0; 762 } 763 764 void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 765 uint64_t page_table_base) 766 { 767 struct amdgpu_device *adev = get_amdgpu_device(kgd); 768 769 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 770 pr_err("trying to set page table base for wrong VMID %u\n", 771 vmid); 772 return; 773 } 774 775 /* TODO: take advantage of per-process address space size. For 776 * now, all processes share the same address space size, like 777 * on GFX8 and older. 778 */ 779 if (adev->asic_type == CHIP_ARCTURUS) { 780 /* Two MMHUBs */ 781 mmhub_v9_4_setup_vm_pt_regs(adev, 0, vmid, page_table_base); 782 mmhub_v9_4_setup_vm_pt_regs(adev, 1, vmid, page_table_base); 783 } else 784 mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 785 786 gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 787 } 788 789 const struct kfd2kgd_calls gfx_v9_kfd2kgd = { 790 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 791 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 792 .init_interrupts = kgd_gfx_v9_init_interrupts, 793 .hqd_load = kgd_gfx_v9_hqd_load, 794 .hqd_sdma_load = kgd_hqd_sdma_load, 795 .hqd_dump = kgd_gfx_v9_hqd_dump, 796 .hqd_sdma_dump = kgd_hqd_sdma_dump, 797 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 798 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 799 .hqd_destroy = kgd_gfx_v9_hqd_destroy, 800 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 801 .address_watch_disable = kgd_gfx_v9_address_watch_disable, 802 .address_watch_execute = kgd_gfx_v9_address_watch_execute, 803 .wave_control_execute = kgd_gfx_v9_wave_control_execute, 804 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, 805 .get_atc_vmid_pasid_mapping_info = 806 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, 807 .get_tile_config = kgd_gfx_v9_get_tile_config, 808 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 809 .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, 810 .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, 811 .get_hive_id = amdgpu_amdkfd_get_hive_id, 812 }; 813