1 /* 2 * Copyright 2014-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "amdgpu.h" 23 #include "amdgpu_amdkfd.h" 24 #include "gc/gc_9_0_offset.h" 25 #include "gc/gc_9_0_sh_mask.h" 26 #include "vega10_enum.h" 27 #include "sdma0/sdma0_4_0_offset.h" 28 #include "sdma0/sdma0_4_0_sh_mask.h" 29 #include "sdma1/sdma1_4_0_offset.h" 30 #include "sdma1/sdma1_4_0_sh_mask.h" 31 #include "athub/athub_1_0_offset.h" 32 #include "athub/athub_1_0_sh_mask.h" 33 #include "oss/osssys_4_0_offset.h" 34 #include "oss/osssys_4_0_sh_mask.h" 35 #include "soc15_common.h" 36 #include "v9_structs.h" 37 #include "soc15.h" 38 #include "soc15d.h" 39 #include "gfx_v9_0.h" 40 #include "amdgpu_amdkfd_gfx_v9.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES, 46 SAVE_WAVES 47 }; 48 49 static void kgd_gfx_v9_lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, 50 uint32_t queue, uint32_t vmid, uint32_t inst) 51 { 52 mutex_lock(&adev->srbm_mutex); 53 soc15_grbm_select(adev, mec, pipe, queue, vmid, GET_INST(GC, inst)); 54 } 55 56 static void kgd_gfx_v9_unlock_srbm(struct amdgpu_device *adev, uint32_t inst) 57 { 58 soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); 59 mutex_unlock(&adev->srbm_mutex); 60 } 61 62 void kgd_gfx_v9_acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, 63 uint32_t queue_id, uint32_t inst) 64 { 65 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 66 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 67 68 kgd_gfx_v9_lock_srbm(adev, mec, pipe, queue_id, 0, inst); 69 } 70 71 uint64_t kgd_gfx_v9_get_queue_mask(struct amdgpu_device *adev, 72 uint32_t pipe_id, uint32_t queue_id) 73 { 74 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + 75 queue_id; 76 77 return 1ull << bit; 78 } 79 80 void kgd_gfx_v9_release_queue(struct amdgpu_device *adev, uint32_t inst) 81 { 82 kgd_gfx_v9_unlock_srbm(adev, inst); 83 } 84 85 void kgd_gfx_v9_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, 86 uint32_t sh_mem_config, 87 uint32_t sh_mem_ape1_base, 88 uint32_t sh_mem_ape1_limit, 89 uint32_t sh_mem_bases, uint32_t inst) 90 { 91 kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst); 92 93 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_CONFIG), sh_mem_config); 94 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSH_MEM_BASES), sh_mem_bases); 95 /* APE1 no longer exists on GFX9 */ 96 97 kgd_gfx_v9_unlock_srbm(adev, inst); 98 } 99 100 int kgd_gfx_v9_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, 101 unsigned int vmid, uint32_t inst) 102 { 103 /* 104 * We have to assume that there is no outstanding mapping. 105 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 106 * a mapping is in progress or because a mapping finished 107 * and the SW cleared it. 108 * So the protocol is to always wait & clear. 109 */ 110 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 111 ATC_VMID0_PASID_MAPPING__VALID_MASK; 112 113 /* 114 * need to do this twice, once for gfx and once for mmhub 115 * for ATC add 16 to VMID for mmhub, for IH different registers. 116 * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 117 */ 118 119 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 120 pasid_mapping); 121 122 while (!(RREG32(SOC15_REG_OFFSET( 123 ATHUB, 0, 124 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 125 (1U << vmid))) 126 cpu_relax(); 127 128 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 129 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 130 1U << vmid); 131 132 /* Mapping vmid to pasid also for IH block */ 133 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 134 pasid_mapping); 135 136 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 137 pasid_mapping); 138 139 while (!(RREG32(SOC15_REG_OFFSET( 140 ATHUB, 0, 141 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 142 (1U << (vmid + 16)))) 143 cpu_relax(); 144 145 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 146 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 147 1U << (vmid + 16)); 148 149 /* Mapping vmid to pasid also for IH block */ 150 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 151 pasid_mapping); 152 return 0; 153 } 154 155 /* TODO - RING0 form of field is obsolete, seems to date back to SI 156 * but still works 157 */ 158 159 int kgd_gfx_v9_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id, 160 uint32_t inst) 161 { 162 uint32_t mec; 163 uint32_t pipe; 164 165 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 166 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 167 168 kgd_gfx_v9_lock_srbm(adev, mec, pipe, 0, 0, inst); 169 170 WREG32_SOC15(GC, GET_INST(GC, inst), mmCPC_INT_CNTL, 171 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 172 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 173 174 kgd_gfx_v9_unlock_srbm(adev, inst); 175 176 return 0; 177 } 178 179 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 180 unsigned int engine_id, 181 unsigned int queue_id) 182 { 183 uint32_t sdma_engine_reg_base = 0; 184 uint32_t sdma_rlc_reg_offset; 185 186 switch (engine_id) { 187 default: 188 dev_warn(adev->dev, 189 "Invalid sdma engine id (%d), using engine id 0\n", 190 engine_id); 191 fallthrough; 192 case 0: 193 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, 194 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL; 195 break; 196 case 1: 197 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0, 198 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL; 199 break; 200 } 201 202 sdma_rlc_reg_offset = sdma_engine_reg_base 203 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 204 205 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 206 queue_id, sdma_rlc_reg_offset); 207 208 return sdma_rlc_reg_offset; 209 } 210 211 static inline struct v9_mqd *get_mqd(void *mqd) 212 { 213 return (struct v9_mqd *)mqd; 214 } 215 216 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 217 { 218 return (struct v9_sdma_mqd *)mqd; 219 } 220 221 int kgd_gfx_v9_hqd_load(struct amdgpu_device *adev, void *mqd, 222 uint32_t pipe_id, uint32_t queue_id, 223 uint32_t __user *wptr, uint32_t wptr_shift, 224 uint32_t wptr_mask, struct mm_struct *mm, 225 uint32_t inst) 226 { 227 struct v9_mqd *m; 228 uint32_t *mqd_hqd; 229 uint32_t reg, hqd_base, data; 230 231 m = get_mqd(mqd); 232 233 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); 234 235 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 236 mqd_hqd = &m->cp_mqd_base_addr_lo; 237 hqd_base = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); 238 239 for (reg = hqd_base; 240 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) 241 WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 242 243 244 /* Activate doorbell logic before triggering WPTR poll. */ 245 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 246 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 247 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL), 248 data); 249 250 if (wptr) { 251 /* Don't read wptr with get_user because the user 252 * context may not be accessible (if this function 253 * runs in a work queue). Instead trigger a one-shot 254 * polling read from memory in the CP. This assumes 255 * that wptr is GPU-accessible in the queue's VMID via 256 * ATC or SVM. WPTR==RPTR before starting the poll so 257 * the CP starts fetching new commands from the right 258 * place. 259 * 260 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 261 * tricky. Assume that the queue didn't overflow. The 262 * number of valid bits in the 32-bit RPTR depends on 263 * the queue size. The remaining bits are taken from 264 * the saved 64-bit WPTR. If the WPTR wrapped, add the 265 * queue size. 266 */ 267 uint32_t queue_size = 268 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 269 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 270 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 271 272 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 273 guessed_wptr += queue_size; 274 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 275 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 276 277 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_LO), 278 lower_32_bits(guessed_wptr)); 279 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI), 280 upper_32_bits(guessed_wptr)); 281 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR), 282 lower_32_bits((uintptr_t)wptr)); 283 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 284 upper_32_bits((uintptr_t)wptr)); 285 WREG32_SOC15(GC, GET_INST(GC, inst), mmCP_PQ_WPTR_POLL_CNTL1, 286 (uint32_t)kgd_gfx_v9_get_queue_mask(adev, pipe_id, queue_id)); 287 } 288 289 /* Start the EOP fetcher */ 290 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_EOP_RPTR), 291 REG_SET_FIELD(m->cp_hqd_eop_rptr, 292 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 293 294 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 295 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE), data); 296 297 kgd_gfx_v9_release_queue(adev, inst); 298 299 return 0; 300 } 301 302 int kgd_gfx_v9_hiq_mqd_load(struct amdgpu_device *adev, void *mqd, 303 uint32_t pipe_id, uint32_t queue_id, 304 uint32_t doorbell_off, uint32_t inst) 305 { 306 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[inst].ring; 307 struct v9_mqd *m; 308 uint32_t mec, pipe; 309 int r; 310 311 m = get_mqd(mqd); 312 313 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); 314 315 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 316 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 317 318 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 319 mec, pipe, queue_id); 320 321 spin_lock(&adev->gfx.kiq[inst].ring_lock); 322 r = amdgpu_ring_alloc(kiq_ring, 7); 323 if (r) { 324 pr_err("Failed to alloc KIQ (%d).\n", r); 325 goto out_unlock; 326 } 327 328 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 329 amdgpu_ring_write(kiq_ring, 330 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 331 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */ 332 PACKET3_MAP_QUEUES_QUEUE(queue_id) | 333 PACKET3_MAP_QUEUES_PIPE(pipe) | 334 PACKET3_MAP_QUEUES_ME((mec - 1)) | 335 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 336 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 337 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */ 338 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 339 amdgpu_ring_write(kiq_ring, 340 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off)); 341 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); 342 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); 343 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); 344 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); 345 amdgpu_ring_commit(kiq_ring); 346 347 out_unlock: 348 spin_unlock(&adev->gfx.kiq[inst].ring_lock); 349 kgd_gfx_v9_release_queue(adev, inst); 350 351 return r; 352 } 353 354 int kgd_gfx_v9_hqd_dump(struct amdgpu_device *adev, 355 uint32_t pipe_id, uint32_t queue_id, 356 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) 357 { 358 uint32_t i = 0, reg; 359 #define HQD_N_REGS 56 360 #define DUMP_REG(addr) do { \ 361 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 362 break; \ 363 (*dump)[i][0] = (addr) << 2; \ 364 (*dump)[i++][1] = RREG32(addr); \ 365 } while (0) 366 367 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 368 if (*dump == NULL) 369 return -ENOMEM; 370 371 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); 372 373 for (reg = SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_MQD_BASE_ADDR); 374 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) 375 DUMP_REG(reg); 376 377 kgd_gfx_v9_release_queue(adev, inst); 378 379 WARN_ON_ONCE(i != HQD_N_REGS); 380 *n_regs = i; 381 382 return 0; 383 } 384 385 static int kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, 386 uint32_t __user *wptr, struct mm_struct *mm) 387 { 388 struct v9_sdma_mqd *m; 389 uint32_t sdma_rlc_reg_offset; 390 unsigned long end_jiffies; 391 uint32_t data; 392 uint64_t data64; 393 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 394 395 m = get_sdma_mqd(mqd); 396 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 397 m->sdma_queue_id); 398 399 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 400 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 401 402 end_jiffies = msecs_to_jiffies(2000) + jiffies; 403 while (true) { 404 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 405 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 406 break; 407 if (time_after(jiffies, end_jiffies)) { 408 pr_err("SDMA RLC not idle in %s\n", __func__); 409 return -ETIME; 410 } 411 usleep_range(500, 1000); 412 } 413 414 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 415 m->sdmax_rlcx_doorbell_offset); 416 417 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 418 ENABLE, 1); 419 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 421 m->sdmax_rlcx_rb_rptr); 422 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 423 m->sdmax_rlcx_rb_rptr_hi); 424 425 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 426 if (read_user_wptr(mm, wptr64, data64)) { 427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 428 lower_32_bits(data64)); 429 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 430 upper_32_bits(data64)); 431 } else { 432 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 433 m->sdmax_rlcx_rb_rptr); 434 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 435 m->sdmax_rlcx_rb_rptr_hi); 436 } 437 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 438 439 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 440 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 441 m->sdmax_rlcx_rb_base_hi); 442 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 443 m->sdmax_rlcx_rb_rptr_addr_lo); 444 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 445 m->sdmax_rlcx_rb_rptr_addr_hi); 446 447 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 448 RB_ENABLE, 1); 449 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 450 451 return 0; 452 } 453 454 static int kgd_hqd_sdma_dump(struct amdgpu_device *adev, 455 uint32_t engine_id, uint32_t queue_id, 456 uint32_t (**dump)[2], uint32_t *n_regs) 457 { 458 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 459 engine_id, queue_id); 460 uint32_t i = 0, reg; 461 #undef HQD_N_REGS 462 #define HQD_N_REGS (19+6+7+10) 463 464 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 465 if (*dump == NULL) 466 return -ENOMEM; 467 468 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 469 DUMP_REG(sdma_rlc_reg_offset + reg); 470 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 471 DUMP_REG(sdma_rlc_reg_offset + reg); 472 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 473 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 474 DUMP_REG(sdma_rlc_reg_offset + reg); 475 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 476 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 477 DUMP_REG(sdma_rlc_reg_offset + reg); 478 479 WARN_ON_ONCE(i != HQD_N_REGS); 480 *n_regs = i; 481 482 return 0; 483 } 484 485 bool kgd_gfx_v9_hqd_is_occupied(struct amdgpu_device *adev, 486 uint64_t queue_address, uint32_t pipe_id, 487 uint32_t queue_id, uint32_t inst) 488 { 489 uint32_t act; 490 bool retval = false; 491 uint32_t low, high; 492 493 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); 494 act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); 495 if (act) { 496 low = lower_32_bits(queue_address >> 8); 497 high = upper_32_bits(queue_address >> 8); 498 499 if (low == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE) && 500 high == RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_BASE_HI)) 501 retval = true; 502 } 503 kgd_gfx_v9_release_queue(adev, inst); 504 return retval; 505 } 506 507 static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd) 508 { 509 struct v9_sdma_mqd *m; 510 uint32_t sdma_rlc_reg_offset; 511 uint32_t sdma_rlc_rb_cntl; 512 513 m = get_sdma_mqd(mqd); 514 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 515 m->sdma_queue_id); 516 517 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 518 519 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 520 return true; 521 522 return false; 523 } 524 525 int kgd_gfx_v9_hqd_destroy(struct amdgpu_device *adev, void *mqd, 526 enum kfd_preempt_type reset_type, 527 unsigned int utimeout, uint32_t pipe_id, 528 uint32_t queue_id, uint32_t inst) 529 { 530 enum hqd_dequeue_request_type type; 531 unsigned long end_jiffies; 532 uint32_t temp; 533 struct v9_mqd *m = get_mqd(mqd); 534 535 if (amdgpu_in_reset(adev)) 536 return -EIO; 537 538 kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); 539 540 if (m->cp_hqd_vmid == 0) 541 WREG32_FIELD15_RLC(GC, GET_INST(GC, inst), RLC_CP_SCHEDULERS, scheduler1, 0); 542 543 switch (reset_type) { 544 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 545 type = DRAIN_PIPE; 546 break; 547 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 548 type = RESET_WAVES; 549 break; 550 case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: 551 type = SAVE_WAVES; 552 break; 553 default: 554 type = DRAIN_PIPE; 555 break; 556 } 557 558 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_DEQUEUE_REQUEST), type); 559 560 end_jiffies = (utimeout * HZ / 1000) + jiffies; 561 while (true) { 562 temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); 563 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 564 break; 565 if (time_after(jiffies, end_jiffies)) { 566 pr_err("cp queue preemption time out.\n"); 567 kgd_gfx_v9_release_queue(adev, inst); 568 return -ETIME; 569 } 570 usleep_range(500, 1000); 571 } 572 573 kgd_gfx_v9_release_queue(adev, inst); 574 return 0; 575 } 576 577 static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 578 unsigned int utimeout) 579 { 580 struct v9_sdma_mqd *m; 581 uint32_t sdma_rlc_reg_offset; 582 uint32_t temp; 583 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 584 585 m = get_sdma_mqd(mqd); 586 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 587 m->sdma_queue_id); 588 589 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 590 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 591 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 592 593 while (true) { 594 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 595 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 596 break; 597 if (time_after(jiffies, end_jiffies)) { 598 pr_err("SDMA RLC not idle in %s\n", __func__); 599 return -ETIME; 600 } 601 usleep_range(500, 1000); 602 } 603 604 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 605 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 606 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 607 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 608 609 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 610 m->sdmax_rlcx_rb_rptr_hi = 611 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 612 613 return 0; 614 } 615 616 bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 617 uint8_t vmid, uint16_t *p_pasid) 618 { 619 uint32_t value; 620 621 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 622 + vmid); 623 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 624 625 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 626 } 627 628 int kgd_gfx_v9_wave_control_execute(struct amdgpu_device *adev, 629 uint32_t gfx_index_val, 630 uint32_t sq_cmd, uint32_t inst) 631 { 632 uint32_t data = 0; 633 634 mutex_lock(&adev->grbm_idx_mutex); 635 636 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, gfx_index_val); 637 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, sq_cmd); 638 639 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 640 INSTANCE_BROADCAST_WRITES, 1); 641 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 642 SH_BROADCAST_WRITES, 1); 643 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 644 SE_BROADCAST_WRITES, 1); 645 646 WREG32_SOC15_RLC_SHADOW(GC, GET_INST(GC, inst), mmGRBM_GFX_INDEX, data); 647 mutex_unlock(&adev->grbm_idx_mutex); 648 649 return 0; 650 } 651 652 void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev, 653 uint32_t vmid, uint64_t page_table_base) 654 { 655 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 656 pr_err("trying to set page table base for wrong VMID %u\n", 657 vmid); 658 return; 659 } 660 661 adev->mmhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); 662 663 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); 664 } 665 666 static void lock_spi_csq_mutexes(struct amdgpu_device *adev) 667 { 668 mutex_lock(&adev->srbm_mutex); 669 mutex_lock(&adev->grbm_idx_mutex); 670 671 } 672 673 static void unlock_spi_csq_mutexes(struct amdgpu_device *adev) 674 { 675 mutex_unlock(&adev->grbm_idx_mutex); 676 mutex_unlock(&adev->srbm_mutex); 677 } 678 679 /** 680 * get_wave_count: Read device registers to get number of waves in flight for 681 * a particular queue. The method also returns the VMID associated with the 682 * queue. 683 * 684 * @adev: Handle of device whose registers are to be read 685 * @queue_idx: Index of queue in the queue-map bit-field 686 * @wave_cnt: Output parameter updated with number of waves in flight 687 * @vmid: Output parameter updated with VMID of queue whose wave count 688 * is being collected 689 */ 690 static void get_wave_count(struct amdgpu_device *adev, int queue_idx, 691 int *wave_cnt, int *vmid, uint32_t inst) 692 { 693 int pipe_idx; 694 int queue_slot; 695 unsigned int reg_val; 696 697 /* 698 * Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID 699 * parameters to read out waves in flight. Get VMID if there are 700 * non-zero waves in flight. 701 */ 702 *vmid = 0xFF; 703 *wave_cnt = 0; 704 pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; 705 queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; 706 soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, inst); 707 reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + 708 queue_slot); 709 *wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; 710 if (*wave_cnt != 0) 711 *vmid = (RREG32_SOC15(GC, inst, mmCP_HQD_VMID) & 712 CP_HQD_VMID__VMID_MASK) >> CP_HQD_VMID__VMID__SHIFT; 713 } 714 715 /** 716 * kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each 717 * shader engine and aggregates the number of waves that are in flight for the 718 * process whose pasid is provided as a parameter. The process could have ZERO 719 * or more queues running and submitting waves to compute units. 720 * 721 * @adev: Handle of device from which to get number of waves in flight 722 * @pasid: Identifies the process for which this query call is invoked 723 * @pasid_wave_cnt: Output parameter updated with number of waves in flight that 724 * belong to process with given pasid 725 * @max_waves_per_cu: Output parameter updated with maximum number of waves 726 * possible per Compute Unit 727 * 728 * Note: It's possible that the device has too many queues (oversubscription) 729 * in which case a VMID could be remapped to a different PASID. This could lead 730 * to an inaccurate wave count. Following is a high-level sequence: 731 * Time T1: vmid = getVmid(); vmid is associated with Pasid P1 732 * Time T2: passId = getPasId(vmid); vmid is associated with Pasid P2 733 * In the sequence above wave count obtained from time T1 will be incorrectly 734 * lost or added to total wave count. 735 * 736 * The registers that provide the waves in flight are: 737 * 738 * SPI_CSQ_WF_ACTIVE_STATUS - bit-map of queues per pipe. The bit is ON if a 739 * queue is slotted, OFF if there is no queue. A process could have ZERO or 740 * more queues slotted and submitting waves to be run on compute units. Even 741 * when there is a queue it is possible there could be zero wave fronts, this 742 * can happen when queue is waiting on top-of-pipe events - e.g. waitRegMem 743 * command 744 * 745 * For each bit that is ON from above: 746 * 747 * Read (SPI_CSQ_WF_ACTIVE_COUNT_0 + queue_idx) register. It provides the 748 * number of waves that are in flight for the queue at specified index. The 749 * index ranges from 0 to 7. 750 * 751 * If non-zero waves are in flight, read CP_HQD_VMID register to obtain VMID 752 * of the wave(s). 753 * 754 * Determine if VMID from above step maps to pasid provided as parameter. If 755 * it matches agrregate the wave count. That the VMID will not match pasid is 756 * a normal condition i.e. a device is expected to support multiple queues 757 * from multiple proceses. 758 * 759 * Reading registers referenced above involves programming GRBM appropriately 760 */ 761 void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, 762 int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst) 763 { 764 int qidx; 765 int vmid; 766 int se_idx; 767 int sh_idx; 768 int se_cnt; 769 int sh_cnt; 770 int wave_cnt; 771 int queue_map; 772 int pasid_tmp; 773 int max_queue_cnt; 774 int vmid_wave_cnt = 0; 775 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES); 776 777 lock_spi_csq_mutexes(adev); 778 soc15_grbm_select(adev, 1, 0, 0, 0, inst); 779 780 /* 781 * Iterate through the shader engines and arrays of the device 782 * to get number of waves in flight 783 */ 784 bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap, 785 KGD_MAX_QUEUES); 786 max_queue_cnt = adev->gfx.mec.num_pipe_per_mec * 787 adev->gfx.mec.num_queue_per_pipe; 788 sh_cnt = adev->gfx.config.max_sh_per_se; 789 se_cnt = adev->gfx.config.max_shader_engines; 790 for (se_idx = 0; se_idx < se_cnt; se_idx++) { 791 for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) { 792 793 amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff, inst); 794 queue_map = RREG32_SOC15(GC, inst, mmSPI_CSQ_WF_ACTIVE_STATUS); 795 796 /* 797 * Assumption: queue map encodes following schema: four 798 * pipes per each micro-engine, with each pipe mapping 799 * eight queues. This schema is true for GFX9 devices 800 * and must be verified for newer device families 801 */ 802 for (qidx = 0; qidx < max_queue_cnt; qidx++) { 803 804 /* Skip qeueus that are not associated with 805 * compute functions 806 */ 807 if (!test_bit(qidx, cp_queue_bitmap)) 808 continue; 809 810 if (!(queue_map & (1 << qidx))) 811 continue; 812 813 /* Get number of waves in flight and aggregate them */ 814 get_wave_count(adev, qidx, &wave_cnt, &vmid, 815 inst); 816 if (wave_cnt != 0) { 817 pasid_tmp = 818 RREG32(SOC15_REG_OFFSET(OSSSYS, inst, 819 mmIH_VMID_0_LUT) + vmid); 820 if (pasid_tmp == pasid) 821 vmid_wave_cnt += wave_cnt; 822 } 823 } 824 } 825 } 826 827 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, inst); 828 soc15_grbm_select(adev, 0, 0, 0, 0, inst); 829 unlock_spi_csq_mutexes(adev); 830 831 /* Update the output parameters and return */ 832 *pasid_wave_cnt = vmid_wave_cnt; 833 *max_waves_per_cu = adev->gfx.cu_info.simd_per_cu * 834 adev->gfx.cu_info.max_waves_per_simd; 835 } 836 837 void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, 838 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst) 839 { 840 kgd_gfx_v9_lock_srbm(adev, 0, 0, 0, vmid, inst); 841 842 /* 843 * Program TBA registers 844 */ 845 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_LO, 846 lower_32_bits(tba_addr >> 8)); 847 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TBA_HI, 848 upper_32_bits(tba_addr >> 8)); 849 850 /* 851 * Program TMA registers 852 */ 853 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_LO, 854 lower_32_bits(tma_addr >> 8)); 855 WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_SHADER_TMA_HI, 856 upper_32_bits(tma_addr >> 8)); 857 858 kgd_gfx_v9_unlock_srbm(adev, inst); 859 } 860 861 const struct kfd2kgd_calls gfx_v9_kfd2kgd = { 862 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 863 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 864 .init_interrupts = kgd_gfx_v9_init_interrupts, 865 .hqd_load = kgd_gfx_v9_hqd_load, 866 .hiq_mqd_load = kgd_gfx_v9_hiq_mqd_load, 867 .hqd_sdma_load = kgd_hqd_sdma_load, 868 .hqd_dump = kgd_gfx_v9_hqd_dump, 869 .hqd_sdma_dump = kgd_hqd_sdma_dump, 870 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 871 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 872 .hqd_destroy = kgd_gfx_v9_hqd_destroy, 873 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 874 .wave_control_execute = kgd_gfx_v9_wave_control_execute, 875 .get_atc_vmid_pasid_mapping_info = 876 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, 877 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 878 .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, 879 .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, 880 }; 881