1 /* 2 * Copyright 2014-2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #define pr_fmt(fmt) "kfd2kgd: " fmt 24 25 #include <linux/module.h> 26 #include <linux/fdtable.h> 27 #include <linux/uaccess.h> 28 #include <linux/firmware.h> 29 #include <drm/drmP.h> 30 #include "amdgpu.h" 31 #include "amdgpu_amdkfd.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_hw_ip.h" 34 #include "gc/gc_9_0_offset.h" 35 #include "gc/gc_9_0_sh_mask.h" 36 #include "vega10_enum.h" 37 #include "sdma0/sdma0_4_0_offset.h" 38 #include "sdma0/sdma0_4_0_sh_mask.h" 39 #include "sdma1/sdma1_4_0_offset.h" 40 #include "sdma1/sdma1_4_0_sh_mask.h" 41 #include "athub/athub_1_0_offset.h" 42 #include "athub/athub_1_0_sh_mask.h" 43 #include "oss/osssys_4_0_offset.h" 44 #include "oss/osssys_4_0_sh_mask.h" 45 #include "soc15_common.h" 46 #include "v9_structs.h" 47 #include "soc15.h" 48 #include "soc15d.h" 49 50 /* HACK: MMHUB and GC both have VM-related register with the same 51 * names but different offsets. Define the MMHUB register we need here 52 * with a prefix. A proper solution would be to move the functions 53 * programming these registers into gfx_v9_0.c and mmhub_v1_0.c 54 * respectively. 55 */ 56 #define mmMMHUB_VM_INVALIDATE_ENG16_REQ 0x06f3 57 #define mmMMHUB_VM_INVALIDATE_ENG16_REQ_BASE_IDX 0 58 59 #define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705 60 #define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0 61 62 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 63 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 64 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 65 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 66 67 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 68 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 69 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 70 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 71 72 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 73 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 74 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 75 #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 76 77 #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 78 #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 79 #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 80 #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 81 82 #define V9_PIPE_PER_MEC (4) 83 #define V9_QUEUES_PER_PIPE_MEC (8) 84 85 enum hqd_dequeue_request_type { 86 NO_ACTION = 0, 87 DRAIN_PIPE, 88 RESET_WAVES 89 }; 90 91 /* 92 * Register access functions 93 */ 94 95 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 96 uint32_t sh_mem_config, 97 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 98 uint32_t sh_mem_bases); 99 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 100 unsigned int vmid); 101 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 102 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 103 uint32_t queue_id, uint32_t __user *wptr, 104 uint32_t wptr_shift, uint32_t wptr_mask, 105 struct mm_struct *mm); 106 static int kgd_hqd_dump(struct kgd_dev *kgd, 107 uint32_t pipe_id, uint32_t queue_id, 108 uint32_t (**dump)[2], uint32_t *n_regs); 109 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 110 uint32_t __user *wptr, struct mm_struct *mm); 111 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 112 uint32_t engine_id, uint32_t queue_id, 113 uint32_t (**dump)[2], uint32_t *n_regs); 114 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 115 uint32_t pipe_id, uint32_t queue_id); 116 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 117 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 118 enum kfd_preempt_type reset_type, 119 unsigned int utimeout, uint32_t pipe_id, 120 uint32_t queue_id); 121 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 122 unsigned int utimeout); 123 static int kgd_address_watch_disable(struct kgd_dev *kgd); 124 static int kgd_address_watch_execute(struct kgd_dev *kgd, 125 unsigned int watch_point_id, 126 uint32_t cntl_val, 127 uint32_t addr_hi, 128 uint32_t addr_lo); 129 static int kgd_wave_control_execute(struct kgd_dev *kgd, 130 uint32_t gfx_index_val, 131 uint32_t sq_cmd); 132 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 133 unsigned int watch_point_id, 134 unsigned int reg_offset); 135 136 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 137 uint8_t vmid); 138 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 139 uint8_t vmid); 140 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 141 uint64_t page_table_base); 142 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 143 static void set_scratch_backing_va(struct kgd_dev *kgd, 144 uint64_t va, uint32_t vmid); 145 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 146 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 147 148 /* Because of REG_GET_FIELD() being used, we put this function in the 149 * asic specific file. 150 */ 151 static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 152 struct tile_config *config) 153 { 154 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 155 156 config->gb_addr_config = adev->gfx.config.gb_addr_config; 157 158 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 159 config->num_tile_configs = 160 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 161 config->macro_tile_config_ptr = 162 adev->gfx.config.macrotile_mode_array; 163 config->num_macro_tile_configs = 164 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 165 166 return 0; 167 } 168 169 static const struct kfd2kgd_calls kfd2kgd = { 170 .init_gtt_mem_allocation = alloc_gtt_mem, 171 .free_gtt_mem = free_gtt_mem, 172 .get_local_mem_info = get_local_mem_info, 173 .get_gpu_clock_counter = get_gpu_clock_counter, 174 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 175 .alloc_pasid = amdgpu_pasid_alloc, 176 .free_pasid = amdgpu_pasid_free, 177 .program_sh_mem_settings = kgd_program_sh_mem_settings, 178 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 179 .init_interrupts = kgd_init_interrupts, 180 .hqd_load = kgd_hqd_load, 181 .hqd_sdma_load = kgd_hqd_sdma_load, 182 .hqd_dump = kgd_hqd_dump, 183 .hqd_sdma_dump = kgd_hqd_sdma_dump, 184 .hqd_is_occupied = kgd_hqd_is_occupied, 185 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 186 .hqd_destroy = kgd_hqd_destroy, 187 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 188 .address_watch_disable = kgd_address_watch_disable, 189 .address_watch_execute = kgd_address_watch_execute, 190 .wave_control_execute = kgd_wave_control_execute, 191 .address_watch_get_offset = kgd_address_watch_get_offset, 192 .get_atc_vmid_pasid_mapping_pasid = 193 get_atc_vmid_pasid_mapping_pasid, 194 .get_atc_vmid_pasid_mapping_valid = 195 get_atc_vmid_pasid_mapping_valid, 196 .get_fw_version = get_fw_version, 197 .set_scratch_backing_va = set_scratch_backing_va, 198 .get_tile_config = amdgpu_amdkfd_get_tile_config, 199 .get_cu_info = get_cu_info, 200 .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 201 .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 202 .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm, 203 .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 204 .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm, 205 .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 206 .set_vm_context_page_table_base = set_vm_context_page_table_base, 207 .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 208 .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 209 .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 210 .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 211 .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 212 .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 213 .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 214 .invalidate_tlbs = invalidate_tlbs, 215 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 216 .submit_ib = amdgpu_amdkfd_submit_ib, 217 .gpu_recover = amdgpu_amdkfd_gpu_reset, 218 .set_compute_idle = amdgpu_amdkfd_set_compute_idle, 219 .get_hive_id = amdgpu_amdkfd_get_hive_id, 220 }; 221 222 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 223 { 224 return (struct kfd2kgd_calls *)&kfd2kgd; 225 } 226 227 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 228 { 229 return (struct amdgpu_device *)kgd; 230 } 231 232 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 233 uint32_t queue, uint32_t vmid) 234 { 235 struct amdgpu_device *adev = get_amdgpu_device(kgd); 236 237 mutex_lock(&adev->srbm_mutex); 238 soc15_grbm_select(adev, mec, pipe, queue, vmid); 239 } 240 241 static void unlock_srbm(struct kgd_dev *kgd) 242 { 243 struct amdgpu_device *adev = get_amdgpu_device(kgd); 244 245 soc15_grbm_select(adev, 0, 0, 0, 0); 246 mutex_unlock(&adev->srbm_mutex); 247 } 248 249 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 250 uint32_t queue_id) 251 { 252 struct amdgpu_device *adev = get_amdgpu_device(kgd); 253 254 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 255 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 256 257 lock_srbm(kgd, mec, pipe, queue_id, 0); 258 } 259 260 static uint32_t get_queue_mask(struct amdgpu_device *adev, 261 uint32_t pipe_id, uint32_t queue_id) 262 { 263 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 264 queue_id) & 31; 265 266 return ((uint32_t)1) << bit; 267 } 268 269 static void release_queue(struct kgd_dev *kgd) 270 { 271 unlock_srbm(kgd); 272 } 273 274 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 275 uint32_t sh_mem_config, 276 uint32_t sh_mem_ape1_base, 277 uint32_t sh_mem_ape1_limit, 278 uint32_t sh_mem_bases) 279 { 280 struct amdgpu_device *adev = get_amdgpu_device(kgd); 281 282 lock_srbm(kgd, 0, 0, 0, vmid); 283 284 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 285 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 286 /* APE1 no longer exists on GFX9 */ 287 288 unlock_srbm(kgd); 289 } 290 291 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 292 unsigned int vmid) 293 { 294 struct amdgpu_device *adev = get_amdgpu_device(kgd); 295 296 /* 297 * We have to assume that there is no outstanding mapping. 298 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 299 * a mapping is in progress or because a mapping finished 300 * and the SW cleared it. 301 * So the protocol is to always wait & clear. 302 */ 303 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 304 ATC_VMID0_PASID_MAPPING__VALID_MASK; 305 306 /* 307 * need to do this twice, once for gfx and once for mmhub 308 * for ATC add 16 to VMID for mmhub, for IH different registers. 309 * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 310 */ 311 312 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 313 pasid_mapping); 314 315 while (!(RREG32(SOC15_REG_OFFSET( 316 ATHUB, 0, 317 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 318 (1U << vmid))) 319 cpu_relax(); 320 321 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 322 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 323 1U << vmid); 324 325 /* Mapping vmid to pasid also for IH block */ 326 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 327 pasid_mapping); 328 329 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 330 pasid_mapping); 331 332 while (!(RREG32(SOC15_REG_OFFSET( 333 ATHUB, 0, 334 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 335 (1U << (vmid + 16)))) 336 cpu_relax(); 337 338 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 339 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 340 1U << (vmid + 16)); 341 342 /* Mapping vmid to pasid also for IH block */ 343 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 344 pasid_mapping); 345 return 0; 346 } 347 348 /* TODO - RING0 form of field is obsolete, seems to date back to SI 349 * but still works 350 */ 351 352 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 353 { 354 struct amdgpu_device *adev = get_amdgpu_device(kgd); 355 uint32_t mec; 356 uint32_t pipe; 357 358 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 359 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 360 361 lock_srbm(kgd, mec, pipe, 0, 0); 362 363 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 364 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 365 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 366 367 unlock_srbm(kgd); 368 369 return 0; 370 } 371 372 static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 373 unsigned int engine_id, 374 unsigned int queue_id) 375 { 376 uint32_t base[2] = { 377 SOC15_REG_OFFSET(SDMA0, 0, 378 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 379 SOC15_REG_OFFSET(SDMA1, 0, 380 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 381 }; 382 uint32_t retval; 383 384 retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 385 mmSDMA0_RLC0_RB_CNTL); 386 387 pr_debug("sdma base address: 0x%x\n", retval); 388 389 return retval; 390 } 391 392 static inline struct v9_mqd *get_mqd(void *mqd) 393 { 394 return (struct v9_mqd *)mqd; 395 } 396 397 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 398 { 399 return (struct v9_sdma_mqd *)mqd; 400 } 401 402 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 403 uint32_t queue_id, uint32_t __user *wptr, 404 uint32_t wptr_shift, uint32_t wptr_mask, 405 struct mm_struct *mm) 406 { 407 struct amdgpu_device *adev = get_amdgpu_device(kgd); 408 struct v9_mqd *m; 409 uint32_t *mqd_hqd; 410 uint32_t reg, hqd_base, data; 411 412 m = get_mqd(mqd); 413 414 acquire_queue(kgd, pipe_id, queue_id); 415 416 /* HIQ is set during driver init period with vmid set to 0*/ 417 if (m->cp_hqd_vmid == 0) { 418 uint32_t value, mec, pipe; 419 420 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 421 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 422 423 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 424 mec, pipe, queue_id); 425 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 426 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 427 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 428 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 429 } 430 431 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 432 mqd_hqd = &m->cp_mqd_base_addr_lo; 433 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 434 435 for (reg = hqd_base; 436 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 437 WREG32(reg, mqd_hqd[reg - hqd_base]); 438 439 440 /* Activate doorbell logic before triggering WPTR poll. */ 441 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 442 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 443 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 444 445 if (wptr) { 446 /* Don't read wptr with get_user because the user 447 * context may not be accessible (if this function 448 * runs in a work queue). Instead trigger a one-shot 449 * polling read from memory in the CP. This assumes 450 * that wptr is GPU-accessible in the queue's VMID via 451 * ATC or SVM. WPTR==RPTR before starting the poll so 452 * the CP starts fetching new commands from the right 453 * place. 454 * 455 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 456 * tricky. Assume that the queue didn't overflow. The 457 * number of valid bits in the 32-bit RPTR depends on 458 * the queue size. The remaining bits are taken from 459 * the saved 64-bit WPTR. If the WPTR wrapped, add the 460 * queue size. 461 */ 462 uint32_t queue_size = 463 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 464 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 465 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 466 467 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 468 guessed_wptr += queue_size; 469 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 470 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 471 472 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 473 lower_32_bits(guessed_wptr)); 474 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 475 upper_32_bits(guessed_wptr)); 476 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 477 lower_32_bits((uintptr_t)wptr)); 478 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 479 upper_32_bits((uintptr_t)wptr)); 480 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 481 get_queue_mask(adev, pipe_id, queue_id)); 482 } 483 484 /* Start the EOP fetcher */ 485 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 486 REG_SET_FIELD(m->cp_hqd_eop_rptr, 487 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 488 489 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 490 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 491 492 release_queue(kgd); 493 494 return 0; 495 } 496 497 static int kgd_hqd_dump(struct kgd_dev *kgd, 498 uint32_t pipe_id, uint32_t queue_id, 499 uint32_t (**dump)[2], uint32_t *n_regs) 500 { 501 struct amdgpu_device *adev = get_amdgpu_device(kgd); 502 uint32_t i = 0, reg; 503 #define HQD_N_REGS 56 504 #define DUMP_REG(addr) do { \ 505 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 506 break; \ 507 (*dump)[i][0] = (addr) << 2; \ 508 (*dump)[i++][1] = RREG32(addr); \ 509 } while (0) 510 511 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 512 if (*dump == NULL) 513 return -ENOMEM; 514 515 acquire_queue(kgd, pipe_id, queue_id); 516 517 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 518 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 519 DUMP_REG(reg); 520 521 release_queue(kgd); 522 523 WARN_ON_ONCE(i != HQD_N_REGS); 524 *n_regs = i; 525 526 return 0; 527 } 528 529 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 530 uint32_t __user *wptr, struct mm_struct *mm) 531 { 532 struct amdgpu_device *adev = get_amdgpu_device(kgd); 533 struct v9_sdma_mqd *m; 534 uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 535 unsigned long end_jiffies; 536 uint32_t data; 537 uint64_t data64; 538 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 539 540 m = get_sdma_mqd(mqd); 541 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 542 m->sdma_queue_id); 543 sdmax_gfx_context_cntl = m->sdma_engine_id ? 544 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 545 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 546 547 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 548 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 549 550 end_jiffies = msecs_to_jiffies(2000) + jiffies; 551 while (true) { 552 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 553 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 554 break; 555 if (time_after(jiffies, end_jiffies)) 556 return -ETIME; 557 usleep_range(500, 1000); 558 } 559 data = RREG32(sdmax_gfx_context_cntl); 560 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 561 RESUME_CTX, 0); 562 WREG32(sdmax_gfx_context_cntl, data); 563 564 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 565 m->sdmax_rlcx_doorbell_offset); 566 567 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 568 ENABLE, 1); 569 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 570 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 571 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 572 m->sdmax_rlcx_rb_rptr_hi); 573 574 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 575 if (read_user_wptr(mm, wptr64, data64)) { 576 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 577 lower_32_bits(data64)); 578 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 579 upper_32_bits(data64)); 580 } else { 581 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 582 m->sdmax_rlcx_rb_rptr); 583 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 584 m->sdmax_rlcx_rb_rptr_hi); 585 } 586 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 587 588 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 589 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 590 m->sdmax_rlcx_rb_base_hi); 591 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 592 m->sdmax_rlcx_rb_rptr_addr_lo); 593 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 594 m->sdmax_rlcx_rb_rptr_addr_hi); 595 596 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 597 RB_ENABLE, 1); 598 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 599 600 return 0; 601 } 602 603 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 604 uint32_t engine_id, uint32_t queue_id, 605 uint32_t (**dump)[2], uint32_t *n_regs) 606 { 607 struct amdgpu_device *adev = get_amdgpu_device(kgd); 608 uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 609 uint32_t i = 0, reg; 610 #undef HQD_N_REGS 611 #define HQD_N_REGS (19+6+7+10) 612 613 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 614 if (*dump == NULL) 615 return -ENOMEM; 616 617 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 618 DUMP_REG(sdma_base_addr + reg); 619 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 620 DUMP_REG(sdma_base_addr + reg); 621 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 622 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 623 DUMP_REG(sdma_base_addr + reg); 624 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 625 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 626 DUMP_REG(sdma_base_addr + reg); 627 628 WARN_ON_ONCE(i != HQD_N_REGS); 629 *n_regs = i; 630 631 return 0; 632 } 633 634 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 635 uint32_t pipe_id, uint32_t queue_id) 636 { 637 struct amdgpu_device *adev = get_amdgpu_device(kgd); 638 uint32_t act; 639 bool retval = false; 640 uint32_t low, high; 641 642 acquire_queue(kgd, pipe_id, queue_id); 643 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 644 if (act) { 645 low = lower_32_bits(queue_address >> 8); 646 high = upper_32_bits(queue_address >> 8); 647 648 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 649 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 650 retval = true; 651 } 652 release_queue(kgd); 653 return retval; 654 } 655 656 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 657 { 658 struct amdgpu_device *adev = get_amdgpu_device(kgd); 659 struct v9_sdma_mqd *m; 660 uint32_t sdma_base_addr; 661 uint32_t sdma_rlc_rb_cntl; 662 663 m = get_sdma_mqd(mqd); 664 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 665 m->sdma_queue_id); 666 667 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 668 669 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 670 return true; 671 672 return false; 673 } 674 675 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 676 enum kfd_preempt_type reset_type, 677 unsigned int utimeout, uint32_t pipe_id, 678 uint32_t queue_id) 679 { 680 struct amdgpu_device *adev = get_amdgpu_device(kgd); 681 enum hqd_dequeue_request_type type; 682 unsigned long end_jiffies; 683 uint32_t temp; 684 struct v9_mqd *m = get_mqd(mqd); 685 686 if (adev->in_gpu_reset) 687 return -EIO; 688 689 acquire_queue(kgd, pipe_id, queue_id); 690 691 if (m->cp_hqd_vmid == 0) 692 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 693 694 switch (reset_type) { 695 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 696 type = DRAIN_PIPE; 697 break; 698 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 699 type = RESET_WAVES; 700 break; 701 default: 702 type = DRAIN_PIPE; 703 break; 704 } 705 706 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 707 708 end_jiffies = (utimeout * HZ / 1000) + jiffies; 709 while (true) { 710 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 711 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 712 break; 713 if (time_after(jiffies, end_jiffies)) { 714 pr_err("cp queue preemption time out.\n"); 715 release_queue(kgd); 716 return -ETIME; 717 } 718 usleep_range(500, 1000); 719 } 720 721 release_queue(kgd); 722 return 0; 723 } 724 725 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 726 unsigned int utimeout) 727 { 728 struct amdgpu_device *adev = get_amdgpu_device(kgd); 729 struct v9_sdma_mqd *m; 730 uint32_t sdma_base_addr; 731 uint32_t temp; 732 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 733 734 m = get_sdma_mqd(mqd); 735 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 736 m->sdma_queue_id); 737 738 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 739 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 740 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 741 742 while (true) { 743 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 744 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 745 break; 746 if (time_after(jiffies, end_jiffies)) 747 return -ETIME; 748 usleep_range(500, 1000); 749 } 750 751 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 752 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 753 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 754 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 755 756 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 757 m->sdmax_rlcx_rb_rptr_hi = 758 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 759 760 return 0; 761 } 762 763 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 764 uint8_t vmid) 765 { 766 uint32_t reg; 767 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 768 769 reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 770 + vmid); 771 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 772 } 773 774 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 775 uint8_t vmid) 776 { 777 uint32_t reg; 778 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 779 780 reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 781 + vmid); 782 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 783 } 784 785 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 786 { 787 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 788 uint32_t req = (1 << vmid) | 789 (0 << VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT) | /* legacy */ 790 VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK | 791 VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK | 792 VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK | 793 VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK | 794 VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK; 795 796 mutex_lock(&adev->srbm_mutex); 797 798 /* Use legacy mode tlb invalidation. 799 * 800 * Currently on Raven the code below is broken for anything but 801 * legacy mode due to a MMHUB power gating problem. A workaround 802 * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 803 * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 804 * bit. 805 * 806 * TODO 1: agree on the right set of invalidation registers for 807 * KFD use. Use the last one for now. Invalidate both GC and 808 * MMHUB. 809 * 810 * TODO 2: support range-based invalidation, requires kfg2kgd 811 * interface change 812 */ 813 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 814 0xffffffff); 815 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 816 0x0000001f); 817 818 WREG32(SOC15_REG_OFFSET(MMHUB, 0, 819 mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 820 0xffffffff); 821 WREG32(SOC15_REG_OFFSET(MMHUB, 0, 822 mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 823 0x0000001f); 824 825 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req); 826 827 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ), 828 req); 829 830 while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) & 831 (1 << vmid))) 832 cpu_relax(); 833 834 while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0, 835 mmMMHUB_VM_INVALIDATE_ENG16_ACK)) & 836 (1 << vmid))) 837 cpu_relax(); 838 839 mutex_unlock(&adev->srbm_mutex); 840 841 } 842 843 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 844 { 845 signed long r; 846 uint32_t seq; 847 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 848 849 spin_lock(&adev->gfx.kiq.ring_lock); 850 amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 851 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 852 amdgpu_ring_write(ring, 853 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 854 PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 855 PACKET3_INVALIDATE_TLBS_PASID(pasid) | 856 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(0)); /* legacy */ 857 amdgpu_fence_emit_polling(ring, &seq); 858 amdgpu_ring_commit(ring); 859 spin_unlock(&adev->gfx.kiq.ring_lock); 860 861 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 862 if (r < 1) { 863 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 864 return -ETIME; 865 } 866 867 return 0; 868 } 869 870 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 871 { 872 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 873 int vmid; 874 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 875 876 if (adev->in_gpu_reset) 877 return -EIO; 878 879 if (ring->ready) 880 return invalidate_tlbs_with_kiq(adev, pasid); 881 882 for (vmid = 0; vmid < 16; vmid++) { 883 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 884 continue; 885 if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 886 if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 887 == pasid) { 888 write_vmid_invalidate_request(kgd, vmid); 889 break; 890 } 891 } 892 } 893 894 return 0; 895 } 896 897 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 898 { 899 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 900 901 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 902 pr_err("non kfd vmid %d\n", vmid); 903 return 0; 904 } 905 906 write_vmid_invalidate_request(kgd, vmid); 907 return 0; 908 } 909 910 static int kgd_address_watch_disable(struct kgd_dev *kgd) 911 { 912 return 0; 913 } 914 915 static int kgd_address_watch_execute(struct kgd_dev *kgd, 916 unsigned int watch_point_id, 917 uint32_t cntl_val, 918 uint32_t addr_hi, 919 uint32_t addr_lo) 920 { 921 return 0; 922 } 923 924 static int kgd_wave_control_execute(struct kgd_dev *kgd, 925 uint32_t gfx_index_val, 926 uint32_t sq_cmd) 927 { 928 struct amdgpu_device *adev = get_amdgpu_device(kgd); 929 uint32_t data = 0; 930 931 mutex_lock(&adev->grbm_idx_mutex); 932 933 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 934 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 935 936 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 937 INSTANCE_BROADCAST_WRITES, 1); 938 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 939 SH_BROADCAST_WRITES, 1); 940 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 941 SE_BROADCAST_WRITES, 1); 942 943 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 944 mutex_unlock(&adev->grbm_idx_mutex); 945 946 return 0; 947 } 948 949 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 950 unsigned int watch_point_id, 951 unsigned int reg_offset) 952 { 953 return 0; 954 } 955 956 static void set_scratch_backing_va(struct kgd_dev *kgd, 957 uint64_t va, uint32_t vmid) 958 { 959 /* No longer needed on GFXv9. The scratch base address is 960 * passed to the shader by the CP. It's the user mode driver's 961 * responsibility. 962 */ 963 } 964 965 /* FIXME: Does this need to be ASIC-specific code? */ 966 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 967 { 968 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 969 const union amdgpu_firmware_header *hdr; 970 971 switch (type) { 972 case KGD_ENGINE_PFP: 973 hdr = (const union amdgpu_firmware_header *)adev->gfx.pfp_fw->data; 974 break; 975 976 case KGD_ENGINE_ME: 977 hdr = (const union amdgpu_firmware_header *)adev->gfx.me_fw->data; 978 break; 979 980 case KGD_ENGINE_CE: 981 hdr = (const union amdgpu_firmware_header *)adev->gfx.ce_fw->data; 982 break; 983 984 case KGD_ENGINE_MEC1: 985 hdr = (const union amdgpu_firmware_header *)adev->gfx.mec_fw->data; 986 break; 987 988 case KGD_ENGINE_MEC2: 989 hdr = (const union amdgpu_firmware_header *)adev->gfx.mec2_fw->data; 990 break; 991 992 case KGD_ENGINE_RLC: 993 hdr = (const union amdgpu_firmware_header *)adev->gfx.rlc_fw->data; 994 break; 995 996 case KGD_ENGINE_SDMA1: 997 hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[0].fw->data; 998 break; 999 1000 case KGD_ENGINE_SDMA2: 1001 hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[1].fw->data; 1002 break; 1003 1004 default: 1005 return 0; 1006 } 1007 1008 if (hdr == NULL) 1009 return 0; 1010 1011 /* Only 12 bit in use*/ 1012 return hdr->common.ucode_version; 1013 } 1014 1015 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 1016 uint64_t page_table_base) 1017 { 1018 struct amdgpu_device *adev = get_amdgpu_device(kgd); 1019 uint64_t base = page_table_base | AMDGPU_PTE_VALID; 1020 1021 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 1022 pr_err("trying to set page table base for wrong VMID %u\n", 1023 vmid); 1024 return; 1025 } 1026 1027 /* TODO: take advantage of per-process address space size. For 1028 * now, all processes share the same address space size, like 1029 * on GFX8 and older. 1030 */ 1031 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1032 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1033 1034 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1035 lower_32_bits(adev->vm_manager.max_pfn - 1)); 1036 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1037 upper_32_bits(adev->vm_manager.max_pfn - 1)); 1038 1039 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1040 WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1041 1042 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1043 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1044 1045 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1046 lower_32_bits(adev->vm_manager.max_pfn - 1)); 1047 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1048 upper_32_bits(adev->vm_manager.max_pfn - 1)); 1049 1050 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1051 WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1052 } 1053