1d5a114a6SFelix Kuehling /* 2d5a114a6SFelix Kuehling * Copyright 2014-2018 Advanced Micro Devices, Inc. 3d5a114a6SFelix Kuehling * 4d5a114a6SFelix Kuehling * Permission is hereby granted, free of charge, to any person obtaining a 5d5a114a6SFelix Kuehling * copy of this software and associated documentation files (the "Software"), 6d5a114a6SFelix Kuehling * to deal in the Software without restriction, including without limitation 7d5a114a6SFelix Kuehling * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d5a114a6SFelix Kuehling * and/or sell copies of the Software, and to permit persons to whom the 9d5a114a6SFelix Kuehling * Software is furnished to do so, subject to the following conditions: 10d5a114a6SFelix Kuehling * 11d5a114a6SFelix Kuehling * The above copyright notice and this permission notice shall be included in 12d5a114a6SFelix Kuehling * all copies or substantial portions of the Software. 13d5a114a6SFelix Kuehling * 14d5a114a6SFelix Kuehling * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d5a114a6SFelix Kuehling * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d5a114a6SFelix Kuehling * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d5a114a6SFelix Kuehling * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d5a114a6SFelix Kuehling * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d5a114a6SFelix Kuehling * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d5a114a6SFelix Kuehling * OTHER DEALINGS IN THE SOFTWARE. 21d5a114a6SFelix Kuehling */ 22d5a114a6SFelix Kuehling 23d5a114a6SFelix Kuehling #define pr_fmt(fmt) "kfd2kgd: " fmt 24d5a114a6SFelix Kuehling 25d5a114a6SFelix Kuehling #include <linux/module.h> 26d5a114a6SFelix Kuehling #include <linux/fdtable.h> 27d5a114a6SFelix Kuehling #include <linux/uaccess.h> 28d5a114a6SFelix Kuehling #include <linux/firmware.h> 29d5a114a6SFelix Kuehling #include <drm/drmP.h> 30d5a114a6SFelix Kuehling #include "amdgpu.h" 31d5a114a6SFelix Kuehling #include "amdgpu_amdkfd.h" 32d5a114a6SFelix Kuehling #include "amdgpu_ucode.h" 33d5a114a6SFelix Kuehling #include "soc15_hw_ip.h" 34d5a114a6SFelix Kuehling #include "gc/gc_9_0_offset.h" 35d5a114a6SFelix Kuehling #include "gc/gc_9_0_sh_mask.h" 36d5a114a6SFelix Kuehling #include "vega10_enum.h" 37d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_offset.h" 38d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_sh_mask.h" 39d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_offset.h" 40d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_sh_mask.h" 41d5a114a6SFelix Kuehling #include "athub/athub_1_0_offset.h" 42d5a114a6SFelix Kuehling #include "athub/athub_1_0_sh_mask.h" 43d5a114a6SFelix Kuehling #include "oss/osssys_4_0_offset.h" 44d5a114a6SFelix Kuehling #include "oss/osssys_4_0_sh_mask.h" 45d5a114a6SFelix Kuehling #include "soc15_common.h" 46d5a114a6SFelix Kuehling #include "v9_structs.h" 47d5a114a6SFelix Kuehling #include "soc15.h" 48d5a114a6SFelix Kuehling #include "soc15d.h" 49d5a114a6SFelix Kuehling 50d5a114a6SFelix Kuehling /* HACK: MMHUB and GC both have VM-related register with the same 51d5a114a6SFelix Kuehling * names but different offsets. Define the MMHUB register we need here 52d5a114a6SFelix Kuehling * with a prefix. A proper solution would be to move the functions 53d5a114a6SFelix Kuehling * programming these registers into gfx_v9_0.c and mmhub_v1_0.c 54d5a114a6SFelix Kuehling * respectively. 55d5a114a6SFelix Kuehling */ 56d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ 0x06f3 57d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ_BASE_IDX 0 58d5a114a6SFelix Kuehling 59d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705 60d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0 61d5a114a6SFelix Kuehling 62d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 63d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 64d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 65d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 66d5a114a6SFelix Kuehling 67d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 68d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 69d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 70d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 71d5a114a6SFelix Kuehling 72d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 73d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 74d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 75d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 76d5a114a6SFelix Kuehling 77d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 78d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 79d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 80d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 81d5a114a6SFelix Kuehling 82d5a114a6SFelix Kuehling #define V9_PIPE_PER_MEC (4) 83d5a114a6SFelix Kuehling #define V9_QUEUES_PER_PIPE_MEC (8) 84d5a114a6SFelix Kuehling 85d5a114a6SFelix Kuehling enum hqd_dequeue_request_type { 86d5a114a6SFelix Kuehling NO_ACTION = 0, 87d5a114a6SFelix Kuehling DRAIN_PIPE, 88d5a114a6SFelix Kuehling RESET_WAVES 89d5a114a6SFelix Kuehling }; 90d5a114a6SFelix Kuehling 91d5a114a6SFelix Kuehling /* 92d5a114a6SFelix Kuehling * Register access functions 93d5a114a6SFelix Kuehling */ 94d5a114a6SFelix Kuehling 95d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 96d5a114a6SFelix Kuehling uint32_t sh_mem_config, 97d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 98d5a114a6SFelix Kuehling uint32_t sh_mem_bases); 99d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 100d5a114a6SFelix Kuehling unsigned int vmid); 101d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 102d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 103d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 104d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 105d5a114a6SFelix Kuehling struct mm_struct *mm); 106d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 107d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 108d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 109d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 110d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm); 111d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 112d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 113d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 114d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 115d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id); 116d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 117d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 118d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 119d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 120d5a114a6SFelix Kuehling uint32_t queue_id); 121d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 122d5a114a6SFelix Kuehling unsigned int utimeout); 123d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd); 124d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 125d5a114a6SFelix Kuehling unsigned int watch_point_id, 126d5a114a6SFelix Kuehling uint32_t cntl_val, 127d5a114a6SFelix Kuehling uint32_t addr_hi, 128d5a114a6SFelix Kuehling uint32_t addr_lo); 129d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 130d5a114a6SFelix Kuehling uint32_t gfx_index_val, 131d5a114a6SFelix Kuehling uint32_t sq_cmd); 132d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 133d5a114a6SFelix Kuehling unsigned int watch_point_id, 134d5a114a6SFelix Kuehling unsigned int reg_offset); 135d5a114a6SFelix Kuehling 136d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 137d5a114a6SFelix Kuehling uint8_t vmid); 138d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 139d5a114a6SFelix Kuehling uint8_t vmid); 140d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 141e715c6d0SShaoyun Liu uint64_t page_table_base); 142d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 143d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 144d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid); 145d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 146d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 147d5a114a6SFelix Kuehling 148d5a114a6SFelix Kuehling /* Because of REG_GET_FIELD() being used, we put this function in the 149d5a114a6SFelix Kuehling * asic specific file. 150d5a114a6SFelix Kuehling */ 151d5a114a6SFelix Kuehling static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 152d5a114a6SFelix Kuehling struct tile_config *config) 153d5a114a6SFelix Kuehling { 154d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 155d5a114a6SFelix Kuehling 156d5a114a6SFelix Kuehling config->gb_addr_config = adev->gfx.config.gb_addr_config; 157d5a114a6SFelix Kuehling 158d5a114a6SFelix Kuehling config->tile_config_ptr = adev->gfx.config.tile_mode_array; 159d5a114a6SFelix Kuehling config->num_tile_configs = 160d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.tile_mode_array); 161d5a114a6SFelix Kuehling config->macro_tile_config_ptr = 162d5a114a6SFelix Kuehling adev->gfx.config.macrotile_mode_array; 163d5a114a6SFelix Kuehling config->num_macro_tile_configs = 164d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 165d5a114a6SFelix Kuehling 166d5a114a6SFelix Kuehling return 0; 167d5a114a6SFelix Kuehling } 168d5a114a6SFelix Kuehling 169d5a114a6SFelix Kuehling static const struct kfd2kgd_calls kfd2kgd = { 170d5a114a6SFelix Kuehling .init_gtt_mem_allocation = alloc_gtt_mem, 171d5a114a6SFelix Kuehling .free_gtt_mem = free_gtt_mem, 172d5a114a6SFelix Kuehling .get_local_mem_info = get_local_mem_info, 173d5a114a6SFelix Kuehling .get_gpu_clock_counter = get_gpu_clock_counter, 174d5a114a6SFelix Kuehling .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 175d5a114a6SFelix Kuehling .alloc_pasid = amdgpu_pasid_alloc, 176d5a114a6SFelix Kuehling .free_pasid = amdgpu_pasid_free, 177d5a114a6SFelix Kuehling .program_sh_mem_settings = kgd_program_sh_mem_settings, 178d5a114a6SFelix Kuehling .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 179d5a114a6SFelix Kuehling .init_interrupts = kgd_init_interrupts, 180d5a114a6SFelix Kuehling .hqd_load = kgd_hqd_load, 181d5a114a6SFelix Kuehling .hqd_sdma_load = kgd_hqd_sdma_load, 182d5a114a6SFelix Kuehling .hqd_dump = kgd_hqd_dump, 183d5a114a6SFelix Kuehling .hqd_sdma_dump = kgd_hqd_sdma_dump, 184d5a114a6SFelix Kuehling .hqd_is_occupied = kgd_hqd_is_occupied, 185d5a114a6SFelix Kuehling .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 186d5a114a6SFelix Kuehling .hqd_destroy = kgd_hqd_destroy, 187d5a114a6SFelix Kuehling .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 188d5a114a6SFelix Kuehling .address_watch_disable = kgd_address_watch_disable, 189d5a114a6SFelix Kuehling .address_watch_execute = kgd_address_watch_execute, 190d5a114a6SFelix Kuehling .wave_control_execute = kgd_wave_control_execute, 191d5a114a6SFelix Kuehling .address_watch_get_offset = kgd_address_watch_get_offset, 192d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_pasid = 193d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_pasid, 194d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_valid = 195d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_valid, 196d5a114a6SFelix Kuehling .get_fw_version = get_fw_version, 197d5a114a6SFelix Kuehling .set_scratch_backing_va = set_scratch_backing_va, 198d5a114a6SFelix Kuehling .get_tile_config = amdgpu_amdkfd_get_tile_config, 199d5a114a6SFelix Kuehling .get_cu_info = get_cu_info, 200d5a114a6SFelix Kuehling .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 201d5a114a6SFelix Kuehling .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 202d5a114a6SFelix Kuehling .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm, 203d5a114a6SFelix Kuehling .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 204bf47afbaSOak Zeng .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm, 205d5a114a6SFelix Kuehling .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 206d5a114a6SFelix Kuehling .set_vm_context_page_table_base = set_vm_context_page_table_base, 207d5a114a6SFelix Kuehling .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 208d5a114a6SFelix Kuehling .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 209d5a114a6SFelix Kuehling .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 210d5a114a6SFelix Kuehling .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 211d5a114a6SFelix Kuehling .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 212d5a114a6SFelix Kuehling .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 213d5a114a6SFelix Kuehling .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 214d5a114a6SFelix Kuehling .invalidate_tlbs = invalidate_tlbs, 215d5a114a6SFelix Kuehling .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 216d5a114a6SFelix Kuehling .submit_ib = amdgpu_amdkfd_submit_ib, 21701c097dbSFelix Kuehling .gpu_recover = amdgpu_amdkfd_gpu_reset, 218db8b62c0SShaoyun Liu .set_compute_idle = amdgpu_amdkfd_set_compute_idle, 219db8b62c0SShaoyun Liu .get_hive_id = amdgpu_amdkfd_get_hive_id, 220d5a114a6SFelix Kuehling }; 221d5a114a6SFelix Kuehling 222d5a114a6SFelix Kuehling struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 223d5a114a6SFelix Kuehling { 224d5a114a6SFelix Kuehling return (struct kfd2kgd_calls *)&kfd2kgd; 225d5a114a6SFelix Kuehling } 226d5a114a6SFelix Kuehling 227d5a114a6SFelix Kuehling static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 228d5a114a6SFelix Kuehling { 229d5a114a6SFelix Kuehling return (struct amdgpu_device *)kgd; 230d5a114a6SFelix Kuehling } 231d5a114a6SFelix Kuehling 232d5a114a6SFelix Kuehling static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 233d5a114a6SFelix Kuehling uint32_t queue, uint32_t vmid) 234d5a114a6SFelix Kuehling { 235d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 236d5a114a6SFelix Kuehling 237d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 238d5a114a6SFelix Kuehling soc15_grbm_select(adev, mec, pipe, queue, vmid); 239d5a114a6SFelix Kuehling } 240d5a114a6SFelix Kuehling 241d5a114a6SFelix Kuehling static void unlock_srbm(struct kgd_dev *kgd) 242d5a114a6SFelix Kuehling { 243d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 244d5a114a6SFelix Kuehling 245d5a114a6SFelix Kuehling soc15_grbm_select(adev, 0, 0, 0, 0); 246d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 247d5a114a6SFelix Kuehling } 248d5a114a6SFelix Kuehling 249d5a114a6SFelix Kuehling static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 250d5a114a6SFelix Kuehling uint32_t queue_id) 251d5a114a6SFelix Kuehling { 252d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 253d5a114a6SFelix Kuehling 254d5a114a6SFelix Kuehling uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 255d5a114a6SFelix Kuehling uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 256d5a114a6SFelix Kuehling 257d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, queue_id, 0); 258d5a114a6SFelix Kuehling } 259d5a114a6SFelix Kuehling 260d5a114a6SFelix Kuehling static uint32_t get_queue_mask(struct amdgpu_device *adev, 261d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 262d5a114a6SFelix Kuehling { 263d5a114a6SFelix Kuehling unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 264d5a114a6SFelix Kuehling queue_id) & 31; 265d5a114a6SFelix Kuehling 266d5a114a6SFelix Kuehling return ((uint32_t)1) << bit; 267d5a114a6SFelix Kuehling } 268d5a114a6SFelix Kuehling 269d5a114a6SFelix Kuehling static void release_queue(struct kgd_dev *kgd) 270d5a114a6SFelix Kuehling { 271d5a114a6SFelix Kuehling unlock_srbm(kgd); 272d5a114a6SFelix Kuehling } 273d5a114a6SFelix Kuehling 274d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 275d5a114a6SFelix Kuehling uint32_t sh_mem_config, 276d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, 277d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_limit, 278d5a114a6SFelix Kuehling uint32_t sh_mem_bases) 279d5a114a6SFelix Kuehling { 280d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 281d5a114a6SFelix Kuehling 282d5a114a6SFelix Kuehling lock_srbm(kgd, 0, 0, 0, vmid); 283d5a114a6SFelix Kuehling 284d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 285d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 286d5a114a6SFelix Kuehling /* APE1 no longer exists on GFX9 */ 287d5a114a6SFelix Kuehling 288d5a114a6SFelix Kuehling unlock_srbm(kgd); 289d5a114a6SFelix Kuehling } 290d5a114a6SFelix Kuehling 291d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 292d5a114a6SFelix Kuehling unsigned int vmid) 293d5a114a6SFelix Kuehling { 294d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 295d5a114a6SFelix Kuehling 296d5a114a6SFelix Kuehling /* 297d5a114a6SFelix Kuehling * We have to assume that there is no outstanding mapping. 298d5a114a6SFelix Kuehling * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 299d5a114a6SFelix Kuehling * a mapping is in progress or because a mapping finished 300d5a114a6SFelix Kuehling * and the SW cleared it. 301d5a114a6SFelix Kuehling * So the protocol is to always wait & clear. 302d5a114a6SFelix Kuehling */ 303d5a114a6SFelix Kuehling uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 304d5a114a6SFelix Kuehling ATC_VMID0_PASID_MAPPING__VALID_MASK; 305d5a114a6SFelix Kuehling 306d5a114a6SFelix Kuehling /* 307d5a114a6SFelix Kuehling * need to do this twice, once for gfx and once for mmhub 308d5a114a6SFelix Kuehling * for ATC add 16 to VMID for mmhub, for IH different registers. 309d5a114a6SFelix Kuehling * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 310d5a114a6SFelix Kuehling */ 311d5a114a6SFelix Kuehling 312d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 313d5a114a6SFelix Kuehling pasid_mapping); 314d5a114a6SFelix Kuehling 315d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 316d5a114a6SFelix Kuehling ATHUB, 0, 317d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 318d5a114a6SFelix Kuehling (1U << vmid))) 319d5a114a6SFelix Kuehling cpu_relax(); 320d5a114a6SFelix Kuehling 321d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 322d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 323d5a114a6SFelix Kuehling 1U << vmid); 324d5a114a6SFelix Kuehling 325d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 326d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 327d5a114a6SFelix Kuehling pasid_mapping); 328d5a114a6SFelix Kuehling 329d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 330d5a114a6SFelix Kuehling pasid_mapping); 331d5a114a6SFelix Kuehling 332d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 333d5a114a6SFelix Kuehling ATHUB, 0, 334d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 335d5a114a6SFelix Kuehling (1U << (vmid + 16)))) 336d5a114a6SFelix Kuehling cpu_relax(); 337d5a114a6SFelix Kuehling 338d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 339d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 340d5a114a6SFelix Kuehling 1U << (vmid + 16)); 341d5a114a6SFelix Kuehling 342d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 343d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 344d5a114a6SFelix Kuehling pasid_mapping); 345d5a114a6SFelix Kuehling return 0; 346d5a114a6SFelix Kuehling } 347d5a114a6SFelix Kuehling 348d5a114a6SFelix Kuehling /* TODO - RING0 form of field is obsolete, seems to date back to SI 349d5a114a6SFelix Kuehling * but still works 350d5a114a6SFelix Kuehling */ 351d5a114a6SFelix Kuehling 352d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 353d5a114a6SFelix Kuehling { 354d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 355d5a114a6SFelix Kuehling uint32_t mec; 356d5a114a6SFelix Kuehling uint32_t pipe; 357d5a114a6SFelix Kuehling 358d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 359d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 360d5a114a6SFelix Kuehling 361d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, 0, 0); 362d5a114a6SFelix Kuehling 363d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 364d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 365d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 366d5a114a6SFelix Kuehling 367d5a114a6SFelix Kuehling unlock_srbm(kgd); 368d5a114a6SFelix Kuehling 369d5a114a6SFelix Kuehling return 0; 370d5a114a6SFelix Kuehling } 371d5a114a6SFelix Kuehling 372d5a114a6SFelix Kuehling static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 373d5a114a6SFelix Kuehling unsigned int engine_id, 374d5a114a6SFelix Kuehling unsigned int queue_id) 375d5a114a6SFelix Kuehling { 376d5a114a6SFelix Kuehling uint32_t base[2] = { 377d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, 378d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 379d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, 380d5a114a6SFelix Kuehling mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 381d5a114a6SFelix Kuehling }; 382d5a114a6SFelix Kuehling uint32_t retval; 383d5a114a6SFelix Kuehling 384d5a114a6SFelix Kuehling retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 385d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL); 386d5a114a6SFelix Kuehling 387d5a114a6SFelix Kuehling pr_debug("sdma base address: 0x%x\n", retval); 388d5a114a6SFelix Kuehling 389d5a114a6SFelix Kuehling return retval; 390d5a114a6SFelix Kuehling } 391d5a114a6SFelix Kuehling 392d5a114a6SFelix Kuehling static inline struct v9_mqd *get_mqd(void *mqd) 393d5a114a6SFelix Kuehling { 394d5a114a6SFelix Kuehling return (struct v9_mqd *)mqd; 395d5a114a6SFelix Kuehling } 396d5a114a6SFelix Kuehling 397d5a114a6SFelix Kuehling static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 398d5a114a6SFelix Kuehling { 399d5a114a6SFelix Kuehling return (struct v9_sdma_mqd *)mqd; 400d5a114a6SFelix Kuehling } 401d5a114a6SFelix Kuehling 402d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 403d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 404d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 405d5a114a6SFelix Kuehling struct mm_struct *mm) 406d5a114a6SFelix Kuehling { 407d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 408d5a114a6SFelix Kuehling struct v9_mqd *m; 409d5a114a6SFelix Kuehling uint32_t *mqd_hqd; 410d5a114a6SFelix Kuehling uint32_t reg, hqd_base, data; 411d5a114a6SFelix Kuehling 412d5a114a6SFelix Kuehling m = get_mqd(mqd); 413d5a114a6SFelix Kuehling 414d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 415d5a114a6SFelix Kuehling 416d5a114a6SFelix Kuehling /* HIQ is set during driver init period with vmid set to 0*/ 417d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) { 418d5a114a6SFelix Kuehling uint32_t value, mec, pipe; 419d5a114a6SFelix Kuehling 420d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 421d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 422d5a114a6SFelix Kuehling 423d5a114a6SFelix Kuehling pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 424d5a114a6SFelix Kuehling mec, pipe, queue_id); 425d5a114a6SFelix Kuehling value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 426d5a114a6SFelix Kuehling value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 427d5a114a6SFelix Kuehling ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 428d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 429d5a114a6SFelix Kuehling } 430d5a114a6SFelix Kuehling 431d5a114a6SFelix Kuehling /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 432d5a114a6SFelix Kuehling mqd_hqd = &m->cp_mqd_base_addr_lo; 433d5a114a6SFelix Kuehling hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 434d5a114a6SFelix Kuehling 435d5a114a6SFelix Kuehling for (reg = hqd_base; 436d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 437d5a114a6SFelix Kuehling WREG32(reg, mqd_hqd[reg - hqd_base]); 438d5a114a6SFelix Kuehling 439d5a114a6SFelix Kuehling 440d5a114a6SFelix Kuehling /* Activate doorbell logic before triggering WPTR poll. */ 441d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 442d5a114a6SFelix Kuehling CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 443d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 444d5a114a6SFelix Kuehling 445d5a114a6SFelix Kuehling if (wptr) { 446d5a114a6SFelix Kuehling /* Don't read wptr with get_user because the user 447d5a114a6SFelix Kuehling * context may not be accessible (if this function 448d5a114a6SFelix Kuehling * runs in a work queue). Instead trigger a one-shot 449d5a114a6SFelix Kuehling * polling read from memory in the CP. This assumes 450d5a114a6SFelix Kuehling * that wptr is GPU-accessible in the queue's VMID via 451d5a114a6SFelix Kuehling * ATC or SVM. WPTR==RPTR before starting the poll so 452d5a114a6SFelix Kuehling * the CP starts fetching new commands from the right 453d5a114a6SFelix Kuehling * place. 454d5a114a6SFelix Kuehling * 455d5a114a6SFelix Kuehling * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 456d5a114a6SFelix Kuehling * tricky. Assume that the queue didn't overflow. The 457d5a114a6SFelix Kuehling * number of valid bits in the 32-bit RPTR depends on 458d5a114a6SFelix Kuehling * the queue size. The remaining bits are taken from 459d5a114a6SFelix Kuehling * the saved 64-bit WPTR. If the WPTR wrapped, add the 460d5a114a6SFelix Kuehling * queue size. 461d5a114a6SFelix Kuehling */ 462d5a114a6SFelix Kuehling uint32_t queue_size = 463d5a114a6SFelix Kuehling 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 464d5a114a6SFelix Kuehling CP_HQD_PQ_CONTROL, QUEUE_SIZE); 465d5a114a6SFelix Kuehling uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 466d5a114a6SFelix Kuehling 467d5a114a6SFelix Kuehling if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 468d5a114a6SFelix Kuehling guessed_wptr += queue_size; 469d5a114a6SFelix Kuehling guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 470d5a114a6SFelix Kuehling guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 471d5a114a6SFelix Kuehling 472d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 473d5a114a6SFelix Kuehling lower_32_bits(guessed_wptr)); 474d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 475d5a114a6SFelix Kuehling upper_32_bits(guessed_wptr)); 476d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 477ebe1d22bSArnd Bergmann lower_32_bits((uintptr_t)wptr)); 478d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 479ebe1d22bSArnd Bergmann upper_32_bits((uintptr_t)wptr)); 480d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 481d5a114a6SFelix Kuehling get_queue_mask(adev, pipe_id, queue_id)); 482d5a114a6SFelix Kuehling } 483d5a114a6SFelix Kuehling 484d5a114a6SFelix Kuehling /* Start the EOP fetcher */ 485d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 486d5a114a6SFelix Kuehling REG_SET_FIELD(m->cp_hqd_eop_rptr, 487d5a114a6SFelix Kuehling CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 488d5a114a6SFelix Kuehling 489d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 490d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 491d5a114a6SFelix Kuehling 492d5a114a6SFelix Kuehling release_queue(kgd); 493d5a114a6SFelix Kuehling 494d5a114a6SFelix Kuehling return 0; 495d5a114a6SFelix Kuehling } 496d5a114a6SFelix Kuehling 497d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 498d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 499d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 500d5a114a6SFelix Kuehling { 501d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 502d5a114a6SFelix Kuehling uint32_t i = 0, reg; 503d5a114a6SFelix Kuehling #define HQD_N_REGS 56 504d5a114a6SFelix Kuehling #define DUMP_REG(addr) do { \ 505d5a114a6SFelix Kuehling if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 506d5a114a6SFelix Kuehling break; \ 507d5a114a6SFelix Kuehling (*dump)[i][0] = (addr) << 2; \ 508d5a114a6SFelix Kuehling (*dump)[i++][1] = RREG32(addr); \ 509d5a114a6SFelix Kuehling } while (0) 510d5a114a6SFelix Kuehling 5116da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 512d5a114a6SFelix Kuehling if (*dump == NULL) 513d5a114a6SFelix Kuehling return -ENOMEM; 514d5a114a6SFelix Kuehling 515d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 516d5a114a6SFelix Kuehling 517d5a114a6SFelix Kuehling for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 518d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 519d5a114a6SFelix Kuehling DUMP_REG(reg); 520d5a114a6SFelix Kuehling 521d5a114a6SFelix Kuehling release_queue(kgd); 522d5a114a6SFelix Kuehling 523d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 524d5a114a6SFelix Kuehling *n_regs = i; 525d5a114a6SFelix Kuehling 526d5a114a6SFelix Kuehling return 0; 527d5a114a6SFelix Kuehling } 528d5a114a6SFelix Kuehling 529d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 530d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm) 531d5a114a6SFelix Kuehling { 532d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 533d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 534d5a114a6SFelix Kuehling uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 535d5a114a6SFelix Kuehling unsigned long end_jiffies; 536d5a114a6SFelix Kuehling uint32_t data; 537d5a114a6SFelix Kuehling uint64_t data64; 538d5a114a6SFelix Kuehling uint64_t __user *wptr64 = (uint64_t __user *)wptr; 539d5a114a6SFelix Kuehling 540d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 541d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 542d5a114a6SFelix Kuehling m->sdma_queue_id); 543d5a114a6SFelix Kuehling sdmax_gfx_context_cntl = m->sdma_engine_id ? 544d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 545d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 546d5a114a6SFelix Kuehling 547d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 548d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 549d5a114a6SFelix Kuehling 550d5a114a6SFelix Kuehling end_jiffies = msecs_to_jiffies(2000) + jiffies; 551d5a114a6SFelix Kuehling while (true) { 552d5a114a6SFelix Kuehling data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 553d5a114a6SFelix Kuehling if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 554d5a114a6SFelix Kuehling break; 555d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 556d5a114a6SFelix Kuehling return -ETIME; 557d5a114a6SFelix Kuehling usleep_range(500, 1000); 558d5a114a6SFelix Kuehling } 559d5a114a6SFelix Kuehling data = RREG32(sdmax_gfx_context_cntl); 560d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 561d5a114a6SFelix Kuehling RESUME_CTX, 0); 562d5a114a6SFelix Kuehling WREG32(sdmax_gfx_context_cntl, data); 563d5a114a6SFelix Kuehling 564d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 565d5a114a6SFelix Kuehling m->sdmax_rlcx_doorbell_offset); 566d5a114a6SFelix Kuehling 567d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 568d5a114a6SFelix Kuehling ENABLE, 1); 569d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 570d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 571d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 572d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 573d5a114a6SFelix Kuehling 574d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 575d5a114a6SFelix Kuehling if (read_user_wptr(mm, wptr64, data64)) { 576d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 577d5a114a6SFelix Kuehling lower_32_bits(data64)); 578d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 579d5a114a6SFelix Kuehling upper_32_bits(data64)); 580d5a114a6SFelix Kuehling } else { 581d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 582d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr); 583d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 584d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 585d5a114a6SFelix Kuehling } 586d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 587d5a114a6SFelix Kuehling 588d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 589d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 590d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_base_hi); 591d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 592d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_lo); 593d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 594d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_hi); 595d5a114a6SFelix Kuehling 596d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 597d5a114a6SFelix Kuehling RB_ENABLE, 1); 598d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 599d5a114a6SFelix Kuehling 600d5a114a6SFelix Kuehling return 0; 601d5a114a6SFelix Kuehling } 602d5a114a6SFelix Kuehling 603d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 604d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 605d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 606d5a114a6SFelix Kuehling { 607d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 608d5a114a6SFelix Kuehling uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 609d5a114a6SFelix Kuehling uint32_t i = 0, reg; 610d5a114a6SFelix Kuehling #undef HQD_N_REGS 611d5a114a6SFelix Kuehling #define HQD_N_REGS (19+6+7+10) 612d5a114a6SFelix Kuehling 6136da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 614d5a114a6SFelix Kuehling if (*dump == NULL) 615d5a114a6SFelix Kuehling return -ENOMEM; 616d5a114a6SFelix Kuehling 617d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 618d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 619d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 620d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 621d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 622d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 623d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 624d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 625d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 626d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 627d5a114a6SFelix Kuehling 628d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 629d5a114a6SFelix Kuehling *n_regs = i; 630d5a114a6SFelix Kuehling 631d5a114a6SFelix Kuehling return 0; 632d5a114a6SFelix Kuehling } 633d5a114a6SFelix Kuehling 634d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 635d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 636d5a114a6SFelix Kuehling { 637d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 638d5a114a6SFelix Kuehling uint32_t act; 639d5a114a6SFelix Kuehling bool retval = false; 640d5a114a6SFelix Kuehling uint32_t low, high; 641d5a114a6SFelix Kuehling 642d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 643d5a114a6SFelix Kuehling act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 644d5a114a6SFelix Kuehling if (act) { 645d5a114a6SFelix Kuehling low = lower_32_bits(queue_address >> 8); 646d5a114a6SFelix Kuehling high = upper_32_bits(queue_address >> 8); 647d5a114a6SFelix Kuehling 648d5a114a6SFelix Kuehling if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 649d5a114a6SFelix Kuehling high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 650d5a114a6SFelix Kuehling retval = true; 651d5a114a6SFelix Kuehling } 652d5a114a6SFelix Kuehling release_queue(kgd); 653d5a114a6SFelix Kuehling return retval; 654d5a114a6SFelix Kuehling } 655d5a114a6SFelix Kuehling 656d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 657d5a114a6SFelix Kuehling { 658d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 659d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 660d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 661d5a114a6SFelix Kuehling uint32_t sdma_rlc_rb_cntl; 662d5a114a6SFelix Kuehling 663d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 664d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 665d5a114a6SFelix Kuehling m->sdma_queue_id); 666d5a114a6SFelix Kuehling 667d5a114a6SFelix Kuehling sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 668d5a114a6SFelix Kuehling 669d5a114a6SFelix Kuehling if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 670d5a114a6SFelix Kuehling return true; 671d5a114a6SFelix Kuehling 672d5a114a6SFelix Kuehling return false; 673d5a114a6SFelix Kuehling } 674d5a114a6SFelix Kuehling 675d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 676d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 677d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 678d5a114a6SFelix Kuehling uint32_t queue_id) 679d5a114a6SFelix Kuehling { 680d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 681d5a114a6SFelix Kuehling enum hqd_dequeue_request_type type; 682d5a114a6SFelix Kuehling unsigned long end_jiffies; 683d5a114a6SFelix Kuehling uint32_t temp; 684d5a114a6SFelix Kuehling struct v9_mqd *m = get_mqd(mqd); 685d5a114a6SFelix Kuehling 6861b0bfcffSShaoyun Liu if (adev->in_gpu_reset) 6871b0bfcffSShaoyun Liu return -EIO; 6881b0bfcffSShaoyun Liu 689d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 690d5a114a6SFelix Kuehling 691d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) 692d5a114a6SFelix Kuehling WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 693d5a114a6SFelix Kuehling 694d5a114a6SFelix Kuehling switch (reset_type) { 695d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 696d5a114a6SFelix Kuehling type = DRAIN_PIPE; 697d5a114a6SFelix Kuehling break; 698d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 699d5a114a6SFelix Kuehling type = RESET_WAVES; 700d5a114a6SFelix Kuehling break; 701d5a114a6SFelix Kuehling default: 702d5a114a6SFelix Kuehling type = DRAIN_PIPE; 703d5a114a6SFelix Kuehling break; 704d5a114a6SFelix Kuehling } 705d5a114a6SFelix Kuehling 706d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 707d5a114a6SFelix Kuehling 708d5a114a6SFelix Kuehling end_jiffies = (utimeout * HZ / 1000) + jiffies; 709d5a114a6SFelix Kuehling while (true) { 710d5a114a6SFelix Kuehling temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 711d5a114a6SFelix Kuehling if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 712d5a114a6SFelix Kuehling break; 713d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) { 714d5a114a6SFelix Kuehling pr_err("cp queue preemption time out.\n"); 715d5a114a6SFelix Kuehling release_queue(kgd); 716d5a114a6SFelix Kuehling return -ETIME; 717d5a114a6SFelix Kuehling } 718d5a114a6SFelix Kuehling usleep_range(500, 1000); 719d5a114a6SFelix Kuehling } 720d5a114a6SFelix Kuehling 721d5a114a6SFelix Kuehling release_queue(kgd); 722d5a114a6SFelix Kuehling return 0; 723d5a114a6SFelix Kuehling } 724d5a114a6SFelix Kuehling 725d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 726d5a114a6SFelix Kuehling unsigned int utimeout) 727d5a114a6SFelix Kuehling { 728d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 729d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 730d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 731d5a114a6SFelix Kuehling uint32_t temp; 732d5a114a6SFelix Kuehling unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 733d5a114a6SFelix Kuehling 734d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 735d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 736d5a114a6SFelix Kuehling m->sdma_queue_id); 737d5a114a6SFelix Kuehling 738d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 739d5a114a6SFelix Kuehling temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 740d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 741d5a114a6SFelix Kuehling 742d5a114a6SFelix Kuehling while (true) { 743d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 744d5a114a6SFelix Kuehling if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 745d5a114a6SFelix Kuehling break; 746d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 747d5a114a6SFelix Kuehling return -ETIME; 748d5a114a6SFelix Kuehling usleep_range(500, 1000); 749d5a114a6SFelix Kuehling } 750d5a114a6SFelix Kuehling 751d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 752d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 753d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 754d5a114a6SFelix Kuehling SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 755d5a114a6SFelix Kuehling 756d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 757d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi = 758d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 759d5a114a6SFelix Kuehling 760d5a114a6SFelix Kuehling return 0; 761d5a114a6SFelix Kuehling } 762d5a114a6SFelix Kuehling 763d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 764d5a114a6SFelix Kuehling uint8_t vmid) 765d5a114a6SFelix Kuehling { 766d5a114a6SFelix Kuehling uint32_t reg; 767d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 768d5a114a6SFelix Kuehling 769d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 770d5a114a6SFelix Kuehling + vmid); 771d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 772d5a114a6SFelix Kuehling } 773d5a114a6SFelix Kuehling 774d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 775d5a114a6SFelix Kuehling uint8_t vmid) 776d5a114a6SFelix Kuehling { 777d5a114a6SFelix Kuehling uint32_t reg; 778d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 779d5a114a6SFelix Kuehling 780d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 781d5a114a6SFelix Kuehling + vmid); 782d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 783d5a114a6SFelix Kuehling } 784d5a114a6SFelix Kuehling 785d5a114a6SFelix Kuehling static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 786d5a114a6SFelix Kuehling { 787d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 788d5a114a6SFelix Kuehling uint32_t req = (1 << vmid) | 789d5a114a6SFelix Kuehling (0 << VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT) | /* legacy */ 790d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK | 791d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK | 792d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK | 793d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK | 794d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK; 795d5a114a6SFelix Kuehling 796d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 797d5a114a6SFelix Kuehling 798d5a114a6SFelix Kuehling /* Use legacy mode tlb invalidation. 799d5a114a6SFelix Kuehling * 800d5a114a6SFelix Kuehling * Currently on Raven the code below is broken for anything but 801d5a114a6SFelix Kuehling * legacy mode due to a MMHUB power gating problem. A workaround 802d5a114a6SFelix Kuehling * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 803d5a114a6SFelix Kuehling * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 804d5a114a6SFelix Kuehling * bit. 805d5a114a6SFelix Kuehling * 806d5a114a6SFelix Kuehling * TODO 1: agree on the right set of invalidation registers for 807d5a114a6SFelix Kuehling * KFD use. Use the last one for now. Invalidate both GC and 808d5a114a6SFelix Kuehling * MMHUB. 809d5a114a6SFelix Kuehling * 810d5a114a6SFelix Kuehling * TODO 2: support range-based invalidation, requires kfg2kgd 811d5a114a6SFelix Kuehling * interface change 812d5a114a6SFelix Kuehling */ 813d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 814d5a114a6SFelix Kuehling 0xffffffff); 815d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 816d5a114a6SFelix Kuehling 0x0000001f); 817d5a114a6SFelix Kuehling 818d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 819d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 820d5a114a6SFelix Kuehling 0xffffffff); 821d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 822d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 823d5a114a6SFelix Kuehling 0x0000001f); 824d5a114a6SFelix Kuehling 825d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req); 826d5a114a6SFelix Kuehling 827d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ), 828d5a114a6SFelix Kuehling req); 829d5a114a6SFelix Kuehling 830d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) & 831d5a114a6SFelix Kuehling (1 << vmid))) 832d5a114a6SFelix Kuehling cpu_relax(); 833d5a114a6SFelix Kuehling 834d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0, 835d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ACK)) & 836d5a114a6SFelix Kuehling (1 << vmid))) 837d5a114a6SFelix Kuehling cpu_relax(); 838d5a114a6SFelix Kuehling 839d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 840d5a114a6SFelix Kuehling 841d5a114a6SFelix Kuehling } 842d5a114a6SFelix Kuehling 843d5a114a6SFelix Kuehling static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 844d5a114a6SFelix Kuehling { 845d5a114a6SFelix Kuehling signed long r; 846d5a114a6SFelix Kuehling uint32_t seq; 847d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 848d5a114a6SFelix Kuehling 849d5a114a6SFelix Kuehling spin_lock(&adev->gfx.kiq.ring_lock); 850d5a114a6SFelix Kuehling amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 851d5a114a6SFelix Kuehling amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 852d5a114a6SFelix Kuehling amdgpu_ring_write(ring, 853d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 854d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 855d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_PASID(pasid) | 856d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(0)); /* legacy */ 857d5a114a6SFelix Kuehling amdgpu_fence_emit_polling(ring, &seq); 858d5a114a6SFelix Kuehling amdgpu_ring_commit(ring); 859d5a114a6SFelix Kuehling spin_unlock(&adev->gfx.kiq.ring_lock); 860d5a114a6SFelix Kuehling 861d5a114a6SFelix Kuehling r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 862d5a114a6SFelix Kuehling if (r < 1) { 863d5a114a6SFelix Kuehling DRM_ERROR("wait for kiq fence error: %ld.\n", r); 864d5a114a6SFelix Kuehling return -ETIME; 865d5a114a6SFelix Kuehling } 866d5a114a6SFelix Kuehling 867d5a114a6SFelix Kuehling return 0; 868d5a114a6SFelix Kuehling } 869d5a114a6SFelix Kuehling 870d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 871d5a114a6SFelix Kuehling { 872d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 873d5a114a6SFelix Kuehling int vmid; 874d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 875d5a114a6SFelix Kuehling 876bff418a2SShaoyun Liu if (adev->in_gpu_reset) 877bff418a2SShaoyun Liu return -EIO; 878bff418a2SShaoyun Liu 879d5a114a6SFelix Kuehling if (ring->ready) 880d5a114a6SFelix Kuehling return invalidate_tlbs_with_kiq(adev, pasid); 881d5a114a6SFelix Kuehling 882d5a114a6SFelix Kuehling for (vmid = 0; vmid < 16; vmid++) { 883d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 884d5a114a6SFelix Kuehling continue; 885d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 886d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 887d5a114a6SFelix Kuehling == pasid) { 888d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 889d5a114a6SFelix Kuehling break; 890d5a114a6SFelix Kuehling } 891d5a114a6SFelix Kuehling } 892d5a114a6SFelix Kuehling } 893d5a114a6SFelix Kuehling 894d5a114a6SFelix Kuehling return 0; 895d5a114a6SFelix Kuehling } 896d5a114a6SFelix Kuehling 897d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 898d5a114a6SFelix Kuehling { 899d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 900d5a114a6SFelix Kuehling 901d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 902d5a114a6SFelix Kuehling pr_err("non kfd vmid %d\n", vmid); 903d5a114a6SFelix Kuehling return 0; 904d5a114a6SFelix Kuehling } 905d5a114a6SFelix Kuehling 906d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 907d5a114a6SFelix Kuehling return 0; 908d5a114a6SFelix Kuehling } 909d5a114a6SFelix Kuehling 910d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd) 911d5a114a6SFelix Kuehling { 912d5a114a6SFelix Kuehling return 0; 913d5a114a6SFelix Kuehling } 914d5a114a6SFelix Kuehling 915d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 916d5a114a6SFelix Kuehling unsigned int watch_point_id, 917d5a114a6SFelix Kuehling uint32_t cntl_val, 918d5a114a6SFelix Kuehling uint32_t addr_hi, 919d5a114a6SFelix Kuehling uint32_t addr_lo) 920d5a114a6SFelix Kuehling { 921d5a114a6SFelix Kuehling return 0; 922d5a114a6SFelix Kuehling } 923d5a114a6SFelix Kuehling 924d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 925d5a114a6SFelix Kuehling uint32_t gfx_index_val, 926d5a114a6SFelix Kuehling uint32_t sq_cmd) 927d5a114a6SFelix Kuehling { 928d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 929d5a114a6SFelix Kuehling uint32_t data = 0; 930d5a114a6SFelix Kuehling 931d5a114a6SFelix Kuehling mutex_lock(&adev->grbm_idx_mutex); 932d5a114a6SFelix Kuehling 933d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 934d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 935d5a114a6SFelix Kuehling 936d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 937d5a114a6SFelix Kuehling INSTANCE_BROADCAST_WRITES, 1); 938d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 939d5a114a6SFelix Kuehling SH_BROADCAST_WRITES, 1); 940d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 941d5a114a6SFelix Kuehling SE_BROADCAST_WRITES, 1); 942d5a114a6SFelix Kuehling 943d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 944d5a114a6SFelix Kuehling mutex_unlock(&adev->grbm_idx_mutex); 945d5a114a6SFelix Kuehling 946d5a114a6SFelix Kuehling return 0; 947d5a114a6SFelix Kuehling } 948d5a114a6SFelix Kuehling 949d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 950d5a114a6SFelix Kuehling unsigned int watch_point_id, 951d5a114a6SFelix Kuehling unsigned int reg_offset) 952d5a114a6SFelix Kuehling { 953d5a114a6SFelix Kuehling return 0; 954d5a114a6SFelix Kuehling } 955d5a114a6SFelix Kuehling 956d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 957d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid) 958d5a114a6SFelix Kuehling { 959d5a114a6SFelix Kuehling /* No longer needed on GFXv9. The scratch base address is 960d5a114a6SFelix Kuehling * passed to the shader by the CP. It's the user mode driver's 961d5a114a6SFelix Kuehling * responsibility. 962d5a114a6SFelix Kuehling */ 963d5a114a6SFelix Kuehling } 964d5a114a6SFelix Kuehling 965d5a114a6SFelix Kuehling /* FIXME: Does this need to be ASIC-specific code? */ 966d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 967d5a114a6SFelix Kuehling { 968d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 969d5a114a6SFelix Kuehling const union amdgpu_firmware_header *hdr; 970d5a114a6SFelix Kuehling 971d5a114a6SFelix Kuehling switch (type) { 972d5a114a6SFelix Kuehling case KGD_ENGINE_PFP: 973d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.pfp_fw->data; 974d5a114a6SFelix Kuehling break; 975d5a114a6SFelix Kuehling 976d5a114a6SFelix Kuehling case KGD_ENGINE_ME: 977d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.me_fw->data; 978d5a114a6SFelix Kuehling break; 979d5a114a6SFelix Kuehling 980d5a114a6SFelix Kuehling case KGD_ENGINE_CE: 981d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.ce_fw->data; 982d5a114a6SFelix Kuehling break; 983d5a114a6SFelix Kuehling 984d5a114a6SFelix Kuehling case KGD_ENGINE_MEC1: 985d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec_fw->data; 986d5a114a6SFelix Kuehling break; 987d5a114a6SFelix Kuehling 988d5a114a6SFelix Kuehling case KGD_ENGINE_MEC2: 989d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec2_fw->data; 990d5a114a6SFelix Kuehling break; 991d5a114a6SFelix Kuehling 992d5a114a6SFelix Kuehling case KGD_ENGINE_RLC: 993d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.rlc_fw->data; 994d5a114a6SFelix Kuehling break; 995d5a114a6SFelix Kuehling 996d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA1: 997d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[0].fw->data; 998d5a114a6SFelix Kuehling break; 999d5a114a6SFelix Kuehling 1000d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA2: 1001d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[1].fw->data; 1002d5a114a6SFelix Kuehling break; 1003d5a114a6SFelix Kuehling 1004d5a114a6SFelix Kuehling default: 1005d5a114a6SFelix Kuehling return 0; 1006d5a114a6SFelix Kuehling } 1007d5a114a6SFelix Kuehling 1008d5a114a6SFelix Kuehling if (hdr == NULL) 1009d5a114a6SFelix Kuehling return 0; 1010d5a114a6SFelix Kuehling 1011d5a114a6SFelix Kuehling /* Only 12 bit in use*/ 1012d5a114a6SFelix Kuehling return hdr->common.ucode_version; 1013d5a114a6SFelix Kuehling } 1014d5a114a6SFelix Kuehling 1015d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 1016e715c6d0SShaoyun Liu uint64_t page_table_base) 1017d5a114a6SFelix Kuehling { 1018d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 1019e715c6d0SShaoyun Liu uint64_t base = page_table_base | AMDGPU_PTE_VALID; 1020d5a114a6SFelix Kuehling 1021d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 1022d5a114a6SFelix Kuehling pr_err("trying to set page table base for wrong VMID %u\n", 1023d5a114a6SFelix Kuehling vmid); 1024d5a114a6SFelix Kuehling return; 1025d5a114a6SFelix Kuehling } 1026d5a114a6SFelix Kuehling 1027d5a114a6SFelix Kuehling /* TODO: take advantage of per-process address space size. For 1028d5a114a6SFelix Kuehling * now, all processes share the same address space size, like 1029d5a114a6SFelix Kuehling * on GFX8 and older. 1030d5a114a6SFelix Kuehling */ 1031d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1032d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1033d5a114a6SFelix Kuehling 1034d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1035d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1036d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1037d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1038d5a114a6SFelix Kuehling 1039d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1040d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1041d5a114a6SFelix Kuehling 1042d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1043d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1044d5a114a6SFelix Kuehling 1045d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1046d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1047d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1048d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1049d5a114a6SFelix Kuehling 1050d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1051d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1052d5a114a6SFelix Kuehling } 1053