1d5a114a6SFelix Kuehling /* 2d5a114a6SFelix Kuehling * Copyright 2014-2018 Advanced Micro Devices, Inc. 3d5a114a6SFelix Kuehling * 4d5a114a6SFelix Kuehling * Permission is hereby granted, free of charge, to any person obtaining a 5d5a114a6SFelix Kuehling * copy of this software and associated documentation files (the "Software"), 6d5a114a6SFelix Kuehling * to deal in the Software without restriction, including without limitation 7d5a114a6SFelix Kuehling * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d5a114a6SFelix Kuehling * and/or sell copies of the Software, and to permit persons to whom the 9d5a114a6SFelix Kuehling * Software is furnished to do so, subject to the following conditions: 10d5a114a6SFelix Kuehling * 11d5a114a6SFelix Kuehling * The above copyright notice and this permission notice shall be included in 12d5a114a6SFelix Kuehling * all copies or substantial portions of the Software. 13d5a114a6SFelix Kuehling * 14d5a114a6SFelix Kuehling * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d5a114a6SFelix Kuehling * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d5a114a6SFelix Kuehling * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d5a114a6SFelix Kuehling * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d5a114a6SFelix Kuehling * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d5a114a6SFelix Kuehling * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d5a114a6SFelix Kuehling * OTHER DEALINGS IN THE SOFTWARE. 21d5a114a6SFelix Kuehling */ 22d5a114a6SFelix Kuehling 23d5a114a6SFelix Kuehling #define pr_fmt(fmt) "kfd2kgd: " fmt 24d5a114a6SFelix Kuehling 25d5a114a6SFelix Kuehling #include <linux/module.h> 26d5a114a6SFelix Kuehling #include <linux/fdtable.h> 27d5a114a6SFelix Kuehling #include <linux/uaccess.h> 285634e38cSKuehling, Felix #include <linux/mmu_context.h> 29d5a114a6SFelix Kuehling #include <drm/drmP.h> 30d5a114a6SFelix Kuehling #include "amdgpu.h" 31d5a114a6SFelix Kuehling #include "amdgpu_amdkfd.h" 32d5a114a6SFelix Kuehling #include "soc15_hw_ip.h" 33d5a114a6SFelix Kuehling #include "gc/gc_9_0_offset.h" 34d5a114a6SFelix Kuehling #include "gc/gc_9_0_sh_mask.h" 35d5a114a6SFelix Kuehling #include "vega10_enum.h" 36d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_offset.h" 37d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_sh_mask.h" 38d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_offset.h" 39d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_sh_mask.h" 40d5a114a6SFelix Kuehling #include "athub/athub_1_0_offset.h" 41d5a114a6SFelix Kuehling #include "athub/athub_1_0_sh_mask.h" 42d5a114a6SFelix Kuehling #include "oss/osssys_4_0_offset.h" 43d5a114a6SFelix Kuehling #include "oss/osssys_4_0_sh_mask.h" 44d5a114a6SFelix Kuehling #include "soc15_common.h" 45d5a114a6SFelix Kuehling #include "v9_structs.h" 46d5a114a6SFelix Kuehling #include "soc15.h" 47d5a114a6SFelix Kuehling #include "soc15d.h" 48e4312d45SAlex Deucher #include "mmhub_v1_0.h" 49e4312d45SAlex Deucher #include "gfxhub_v1_0.h" 50d5a114a6SFelix Kuehling 51d5a114a6SFelix Kuehling 52d5a114a6SFelix Kuehling #define V9_PIPE_PER_MEC (4) 53d5a114a6SFelix Kuehling #define V9_QUEUES_PER_PIPE_MEC (8) 54d5a114a6SFelix Kuehling 55d5a114a6SFelix Kuehling enum hqd_dequeue_request_type { 56d5a114a6SFelix Kuehling NO_ACTION = 0, 57d5a114a6SFelix Kuehling DRAIN_PIPE, 58d5a114a6SFelix Kuehling RESET_WAVES 59d5a114a6SFelix Kuehling }; 60d5a114a6SFelix Kuehling 61d5a114a6SFelix Kuehling /* 62d5a114a6SFelix Kuehling * Register access functions 63d5a114a6SFelix Kuehling */ 64d5a114a6SFelix Kuehling 65d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 66d5a114a6SFelix Kuehling uint32_t sh_mem_config, 67d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 68d5a114a6SFelix Kuehling uint32_t sh_mem_bases); 69d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 70d5a114a6SFelix Kuehling unsigned int vmid); 71d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 72d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 73d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 74d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 75d5a114a6SFelix Kuehling struct mm_struct *mm); 76d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 77d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 78d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 79d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 80d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm); 81d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 82d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 83d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 84d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 85d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id); 86d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 87d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 88d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 89d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 90d5a114a6SFelix Kuehling uint32_t queue_id); 91d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 92d5a114a6SFelix Kuehling unsigned int utimeout); 93d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd); 94d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 95d5a114a6SFelix Kuehling unsigned int watch_point_id, 96d5a114a6SFelix Kuehling uint32_t cntl_val, 97d5a114a6SFelix Kuehling uint32_t addr_hi, 98d5a114a6SFelix Kuehling uint32_t addr_lo); 99d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 100d5a114a6SFelix Kuehling uint32_t gfx_index_val, 101d5a114a6SFelix Kuehling uint32_t sq_cmd); 102d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 103d5a114a6SFelix Kuehling unsigned int watch_point_id, 104d5a114a6SFelix Kuehling unsigned int reg_offset); 105d5a114a6SFelix Kuehling 106d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 107d5a114a6SFelix Kuehling uint8_t vmid); 108d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 109d5a114a6SFelix Kuehling uint8_t vmid); 110d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 111e715c6d0SShaoyun Liu uint64_t page_table_base); 112d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 113d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid); 114d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 115d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 116d5a114a6SFelix Kuehling 117d5a114a6SFelix Kuehling /* Because of REG_GET_FIELD() being used, we put this function in the 118d5a114a6SFelix Kuehling * asic specific file. 119d5a114a6SFelix Kuehling */ 120d5a114a6SFelix Kuehling static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 121d5a114a6SFelix Kuehling struct tile_config *config) 122d5a114a6SFelix Kuehling { 123d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 124d5a114a6SFelix Kuehling 125d5a114a6SFelix Kuehling config->gb_addr_config = adev->gfx.config.gb_addr_config; 126d5a114a6SFelix Kuehling 127d5a114a6SFelix Kuehling config->tile_config_ptr = adev->gfx.config.tile_mode_array; 128d5a114a6SFelix Kuehling config->num_tile_configs = 129d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.tile_mode_array); 130d5a114a6SFelix Kuehling config->macro_tile_config_ptr = 131d5a114a6SFelix Kuehling adev->gfx.config.macrotile_mode_array; 132d5a114a6SFelix Kuehling config->num_macro_tile_configs = 133d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 134d5a114a6SFelix Kuehling 135d5a114a6SFelix Kuehling return 0; 136d5a114a6SFelix Kuehling } 137d5a114a6SFelix Kuehling 138d5a114a6SFelix Kuehling static const struct kfd2kgd_calls kfd2kgd = { 139d5a114a6SFelix Kuehling .program_sh_mem_settings = kgd_program_sh_mem_settings, 140d5a114a6SFelix Kuehling .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 141d5a114a6SFelix Kuehling .init_interrupts = kgd_init_interrupts, 142d5a114a6SFelix Kuehling .hqd_load = kgd_hqd_load, 143d5a114a6SFelix Kuehling .hqd_sdma_load = kgd_hqd_sdma_load, 144d5a114a6SFelix Kuehling .hqd_dump = kgd_hqd_dump, 145d5a114a6SFelix Kuehling .hqd_sdma_dump = kgd_hqd_sdma_dump, 146d5a114a6SFelix Kuehling .hqd_is_occupied = kgd_hqd_is_occupied, 147d5a114a6SFelix Kuehling .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 148d5a114a6SFelix Kuehling .hqd_destroy = kgd_hqd_destroy, 149d5a114a6SFelix Kuehling .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 150d5a114a6SFelix Kuehling .address_watch_disable = kgd_address_watch_disable, 151d5a114a6SFelix Kuehling .address_watch_execute = kgd_address_watch_execute, 152d5a114a6SFelix Kuehling .wave_control_execute = kgd_wave_control_execute, 153d5a114a6SFelix Kuehling .address_watch_get_offset = kgd_address_watch_get_offset, 154d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_pasid = 155d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_pasid, 156d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_valid = 157d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_valid, 158d5a114a6SFelix Kuehling .set_scratch_backing_va = set_scratch_backing_va, 159d5a114a6SFelix Kuehling .get_tile_config = amdgpu_amdkfd_get_tile_config, 160d5a114a6SFelix Kuehling .set_vm_context_page_table_base = set_vm_context_page_table_base, 161d5a114a6SFelix Kuehling .invalidate_tlbs = invalidate_tlbs, 162d5a114a6SFelix Kuehling .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 163db8b62c0SShaoyun Liu .get_hive_id = amdgpu_amdkfd_get_hive_id, 164d5a114a6SFelix Kuehling }; 165d5a114a6SFelix Kuehling 166d5a114a6SFelix Kuehling struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 167d5a114a6SFelix Kuehling { 168d5a114a6SFelix Kuehling return (struct kfd2kgd_calls *)&kfd2kgd; 169d5a114a6SFelix Kuehling } 170d5a114a6SFelix Kuehling 171d5a114a6SFelix Kuehling static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 172d5a114a6SFelix Kuehling { 173d5a114a6SFelix Kuehling return (struct amdgpu_device *)kgd; 174d5a114a6SFelix Kuehling } 175d5a114a6SFelix Kuehling 176d5a114a6SFelix Kuehling static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 177d5a114a6SFelix Kuehling uint32_t queue, uint32_t vmid) 178d5a114a6SFelix Kuehling { 179d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 180d5a114a6SFelix Kuehling 181d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 182d5a114a6SFelix Kuehling soc15_grbm_select(adev, mec, pipe, queue, vmid); 183d5a114a6SFelix Kuehling } 184d5a114a6SFelix Kuehling 185d5a114a6SFelix Kuehling static void unlock_srbm(struct kgd_dev *kgd) 186d5a114a6SFelix Kuehling { 187d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 188d5a114a6SFelix Kuehling 189d5a114a6SFelix Kuehling soc15_grbm_select(adev, 0, 0, 0, 0); 190d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 191d5a114a6SFelix Kuehling } 192d5a114a6SFelix Kuehling 193d5a114a6SFelix Kuehling static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 194d5a114a6SFelix Kuehling uint32_t queue_id) 195d5a114a6SFelix Kuehling { 196d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 197d5a114a6SFelix Kuehling 198d5a114a6SFelix Kuehling uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 199d5a114a6SFelix Kuehling uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 200d5a114a6SFelix Kuehling 201d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, queue_id, 0); 202d5a114a6SFelix Kuehling } 203d5a114a6SFelix Kuehling 204d5a114a6SFelix Kuehling static uint32_t get_queue_mask(struct amdgpu_device *adev, 205d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 206d5a114a6SFelix Kuehling { 207d5a114a6SFelix Kuehling unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 208d5a114a6SFelix Kuehling queue_id) & 31; 209d5a114a6SFelix Kuehling 210d5a114a6SFelix Kuehling return ((uint32_t)1) << bit; 211d5a114a6SFelix Kuehling } 212d5a114a6SFelix Kuehling 213d5a114a6SFelix Kuehling static void release_queue(struct kgd_dev *kgd) 214d5a114a6SFelix Kuehling { 215d5a114a6SFelix Kuehling unlock_srbm(kgd); 216d5a114a6SFelix Kuehling } 217d5a114a6SFelix Kuehling 218d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 219d5a114a6SFelix Kuehling uint32_t sh_mem_config, 220d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, 221d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_limit, 222d5a114a6SFelix Kuehling uint32_t sh_mem_bases) 223d5a114a6SFelix Kuehling { 224d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 225d5a114a6SFelix Kuehling 226d5a114a6SFelix Kuehling lock_srbm(kgd, 0, 0, 0, vmid); 227d5a114a6SFelix Kuehling 2281bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 2291bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 230d5a114a6SFelix Kuehling /* APE1 no longer exists on GFX9 */ 231d5a114a6SFelix Kuehling 232d5a114a6SFelix Kuehling unlock_srbm(kgd); 233d5a114a6SFelix Kuehling } 234d5a114a6SFelix Kuehling 235d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 236d5a114a6SFelix Kuehling unsigned int vmid) 237d5a114a6SFelix Kuehling { 238d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 239d5a114a6SFelix Kuehling 240d5a114a6SFelix Kuehling /* 241d5a114a6SFelix Kuehling * We have to assume that there is no outstanding mapping. 242d5a114a6SFelix Kuehling * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 243d5a114a6SFelix Kuehling * a mapping is in progress or because a mapping finished 244d5a114a6SFelix Kuehling * and the SW cleared it. 245d5a114a6SFelix Kuehling * So the protocol is to always wait & clear. 246d5a114a6SFelix Kuehling */ 247d5a114a6SFelix Kuehling uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 248d5a114a6SFelix Kuehling ATC_VMID0_PASID_MAPPING__VALID_MASK; 249d5a114a6SFelix Kuehling 250d5a114a6SFelix Kuehling /* 251d5a114a6SFelix Kuehling * need to do this twice, once for gfx and once for mmhub 252d5a114a6SFelix Kuehling * for ATC add 16 to VMID for mmhub, for IH different registers. 253d5a114a6SFelix Kuehling * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 254d5a114a6SFelix Kuehling */ 255d5a114a6SFelix Kuehling 256d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 257d5a114a6SFelix Kuehling pasid_mapping); 258d5a114a6SFelix Kuehling 259d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 260d5a114a6SFelix Kuehling ATHUB, 0, 261d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 262d5a114a6SFelix Kuehling (1U << vmid))) 263d5a114a6SFelix Kuehling cpu_relax(); 264d5a114a6SFelix Kuehling 265d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 266d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 267d5a114a6SFelix Kuehling 1U << vmid); 268d5a114a6SFelix Kuehling 269d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 270d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 271d5a114a6SFelix Kuehling pasid_mapping); 272d5a114a6SFelix Kuehling 273d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 274d5a114a6SFelix Kuehling pasid_mapping); 275d5a114a6SFelix Kuehling 276d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 277d5a114a6SFelix Kuehling ATHUB, 0, 278d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 279d5a114a6SFelix Kuehling (1U << (vmid + 16)))) 280d5a114a6SFelix Kuehling cpu_relax(); 281d5a114a6SFelix Kuehling 282d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 283d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 284d5a114a6SFelix Kuehling 1U << (vmid + 16)); 285d5a114a6SFelix Kuehling 286d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 287d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 288d5a114a6SFelix Kuehling pasid_mapping); 289d5a114a6SFelix Kuehling return 0; 290d5a114a6SFelix Kuehling } 291d5a114a6SFelix Kuehling 292d5a114a6SFelix Kuehling /* TODO - RING0 form of field is obsolete, seems to date back to SI 293d5a114a6SFelix Kuehling * but still works 294d5a114a6SFelix Kuehling */ 295d5a114a6SFelix Kuehling 296d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 297d5a114a6SFelix Kuehling { 298d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 299d5a114a6SFelix Kuehling uint32_t mec; 300d5a114a6SFelix Kuehling uint32_t pipe; 301d5a114a6SFelix Kuehling 302d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 303d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 304d5a114a6SFelix Kuehling 305d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, 0, 0); 306d5a114a6SFelix Kuehling 307d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 308d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 309d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 310d5a114a6SFelix Kuehling 311d5a114a6SFelix Kuehling unlock_srbm(kgd); 312d5a114a6SFelix Kuehling 313d5a114a6SFelix Kuehling return 0; 314d5a114a6SFelix Kuehling } 315d5a114a6SFelix Kuehling 316d5a114a6SFelix Kuehling static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 317d5a114a6SFelix Kuehling unsigned int engine_id, 318d5a114a6SFelix Kuehling unsigned int queue_id) 319d5a114a6SFelix Kuehling { 320d5a114a6SFelix Kuehling uint32_t base[2] = { 321d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, 322d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 323d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, 324d5a114a6SFelix Kuehling mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 325d5a114a6SFelix Kuehling }; 326d5a114a6SFelix Kuehling uint32_t retval; 327d5a114a6SFelix Kuehling 328d5a114a6SFelix Kuehling retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 329d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL); 330d5a114a6SFelix Kuehling 331d5a114a6SFelix Kuehling pr_debug("sdma base address: 0x%x\n", retval); 332d5a114a6SFelix Kuehling 333d5a114a6SFelix Kuehling return retval; 334d5a114a6SFelix Kuehling } 335d5a114a6SFelix Kuehling 336d5a114a6SFelix Kuehling static inline struct v9_mqd *get_mqd(void *mqd) 337d5a114a6SFelix Kuehling { 338d5a114a6SFelix Kuehling return (struct v9_mqd *)mqd; 339d5a114a6SFelix Kuehling } 340d5a114a6SFelix Kuehling 341d5a114a6SFelix Kuehling static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 342d5a114a6SFelix Kuehling { 343d5a114a6SFelix Kuehling return (struct v9_sdma_mqd *)mqd; 344d5a114a6SFelix Kuehling } 345d5a114a6SFelix Kuehling 346d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 347d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 348d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 349d5a114a6SFelix Kuehling struct mm_struct *mm) 350d5a114a6SFelix Kuehling { 351d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 352d5a114a6SFelix Kuehling struct v9_mqd *m; 353d5a114a6SFelix Kuehling uint32_t *mqd_hqd; 354d5a114a6SFelix Kuehling uint32_t reg, hqd_base, data; 355d5a114a6SFelix Kuehling 356d5a114a6SFelix Kuehling m = get_mqd(mqd); 357d5a114a6SFelix Kuehling 358d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 359d5a114a6SFelix Kuehling 360d5a114a6SFelix Kuehling /* HIQ is set during driver init period with vmid set to 0*/ 361d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) { 362d5a114a6SFelix Kuehling uint32_t value, mec, pipe; 363d5a114a6SFelix Kuehling 364d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 365d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 366d5a114a6SFelix Kuehling 367d5a114a6SFelix Kuehling pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 368d5a114a6SFelix Kuehling mec, pipe, queue_id); 369d5a114a6SFelix Kuehling value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 370d5a114a6SFelix Kuehling value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 371d5a114a6SFelix Kuehling ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 3721bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 373d5a114a6SFelix Kuehling } 374d5a114a6SFelix Kuehling 375d5a114a6SFelix Kuehling /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 376d5a114a6SFelix Kuehling mqd_hqd = &m->cp_mqd_base_addr_lo; 377d5a114a6SFelix Kuehling hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 378d5a114a6SFelix Kuehling 379d5a114a6SFelix Kuehling for (reg = hqd_base; 380d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 3811bff7f6cSTrigger Huang WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 382d5a114a6SFelix Kuehling 383d5a114a6SFelix Kuehling 384d5a114a6SFelix Kuehling /* Activate doorbell logic before triggering WPTR poll. */ 385d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 386d5a114a6SFelix Kuehling CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 3871bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 388d5a114a6SFelix Kuehling 389d5a114a6SFelix Kuehling if (wptr) { 390d5a114a6SFelix Kuehling /* Don't read wptr with get_user because the user 391d5a114a6SFelix Kuehling * context may not be accessible (if this function 392d5a114a6SFelix Kuehling * runs in a work queue). Instead trigger a one-shot 393d5a114a6SFelix Kuehling * polling read from memory in the CP. This assumes 394d5a114a6SFelix Kuehling * that wptr is GPU-accessible in the queue's VMID via 395d5a114a6SFelix Kuehling * ATC or SVM. WPTR==RPTR before starting the poll so 396d5a114a6SFelix Kuehling * the CP starts fetching new commands from the right 397d5a114a6SFelix Kuehling * place. 398d5a114a6SFelix Kuehling * 399d5a114a6SFelix Kuehling * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 400d5a114a6SFelix Kuehling * tricky. Assume that the queue didn't overflow. The 401d5a114a6SFelix Kuehling * number of valid bits in the 32-bit RPTR depends on 402d5a114a6SFelix Kuehling * the queue size. The remaining bits are taken from 403d5a114a6SFelix Kuehling * the saved 64-bit WPTR. If the WPTR wrapped, add the 404d5a114a6SFelix Kuehling * queue size. 405d5a114a6SFelix Kuehling */ 406d5a114a6SFelix Kuehling uint32_t queue_size = 407d5a114a6SFelix Kuehling 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 408d5a114a6SFelix Kuehling CP_HQD_PQ_CONTROL, QUEUE_SIZE); 409d5a114a6SFelix Kuehling uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 410d5a114a6SFelix Kuehling 411d5a114a6SFelix Kuehling if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 412d5a114a6SFelix Kuehling guessed_wptr += queue_size; 413d5a114a6SFelix Kuehling guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 414d5a114a6SFelix Kuehling guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 415d5a114a6SFelix Kuehling 4161bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 417d5a114a6SFelix Kuehling lower_32_bits(guessed_wptr)); 4181bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 419d5a114a6SFelix Kuehling upper_32_bits(guessed_wptr)); 4201bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 421ebe1d22bSArnd Bergmann lower_32_bits((uintptr_t)wptr)); 4221bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 423ebe1d22bSArnd Bergmann upper_32_bits((uintptr_t)wptr)); 424d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 425d5a114a6SFelix Kuehling get_queue_mask(adev, pipe_id, queue_id)); 426d5a114a6SFelix Kuehling } 427d5a114a6SFelix Kuehling 428d5a114a6SFelix Kuehling /* Start the EOP fetcher */ 4291bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 430d5a114a6SFelix Kuehling REG_SET_FIELD(m->cp_hqd_eop_rptr, 431d5a114a6SFelix Kuehling CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 432d5a114a6SFelix Kuehling 433d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 4341bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 435d5a114a6SFelix Kuehling 436d5a114a6SFelix Kuehling release_queue(kgd); 437d5a114a6SFelix Kuehling 438d5a114a6SFelix Kuehling return 0; 439d5a114a6SFelix Kuehling } 440d5a114a6SFelix Kuehling 441d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 442d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 443d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 444d5a114a6SFelix Kuehling { 445d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 446d5a114a6SFelix Kuehling uint32_t i = 0, reg; 447d5a114a6SFelix Kuehling #define HQD_N_REGS 56 448d5a114a6SFelix Kuehling #define DUMP_REG(addr) do { \ 449d5a114a6SFelix Kuehling if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 450d5a114a6SFelix Kuehling break; \ 451d5a114a6SFelix Kuehling (*dump)[i][0] = (addr) << 2; \ 452d5a114a6SFelix Kuehling (*dump)[i++][1] = RREG32(addr); \ 453d5a114a6SFelix Kuehling } while (0) 454d5a114a6SFelix Kuehling 4556da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 456d5a114a6SFelix Kuehling if (*dump == NULL) 457d5a114a6SFelix Kuehling return -ENOMEM; 458d5a114a6SFelix Kuehling 459d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 460d5a114a6SFelix Kuehling 461d5a114a6SFelix Kuehling for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 462d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 463d5a114a6SFelix Kuehling DUMP_REG(reg); 464d5a114a6SFelix Kuehling 465d5a114a6SFelix Kuehling release_queue(kgd); 466d5a114a6SFelix Kuehling 467d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 468d5a114a6SFelix Kuehling *n_regs = i; 469d5a114a6SFelix Kuehling 470d5a114a6SFelix Kuehling return 0; 471d5a114a6SFelix Kuehling } 472d5a114a6SFelix Kuehling 473d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 474d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm) 475d5a114a6SFelix Kuehling { 476d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 477d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 478d5a114a6SFelix Kuehling uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 479d5a114a6SFelix Kuehling unsigned long end_jiffies; 480d5a114a6SFelix Kuehling uint32_t data; 481d5a114a6SFelix Kuehling uint64_t data64; 482d5a114a6SFelix Kuehling uint64_t __user *wptr64 = (uint64_t __user *)wptr; 483d5a114a6SFelix Kuehling 484d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 485d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 486d5a114a6SFelix Kuehling m->sdma_queue_id); 487d5a114a6SFelix Kuehling sdmax_gfx_context_cntl = m->sdma_engine_id ? 488d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 489d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 490d5a114a6SFelix Kuehling 491d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 492d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 493d5a114a6SFelix Kuehling 494d5a114a6SFelix Kuehling end_jiffies = msecs_to_jiffies(2000) + jiffies; 495d5a114a6SFelix Kuehling while (true) { 496d5a114a6SFelix Kuehling data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 497d5a114a6SFelix Kuehling if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 498d5a114a6SFelix Kuehling break; 499d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 500d5a114a6SFelix Kuehling return -ETIME; 501d5a114a6SFelix Kuehling usleep_range(500, 1000); 502d5a114a6SFelix Kuehling } 503d5a114a6SFelix Kuehling data = RREG32(sdmax_gfx_context_cntl); 504d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 505d5a114a6SFelix Kuehling RESUME_CTX, 0); 506d5a114a6SFelix Kuehling WREG32(sdmax_gfx_context_cntl, data); 507d5a114a6SFelix Kuehling 508d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 509d5a114a6SFelix Kuehling m->sdmax_rlcx_doorbell_offset); 510d5a114a6SFelix Kuehling 511d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 512d5a114a6SFelix Kuehling ENABLE, 1); 513d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 514d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 515d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 516d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 517d5a114a6SFelix Kuehling 518d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 519d5a114a6SFelix Kuehling if (read_user_wptr(mm, wptr64, data64)) { 520d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 521d5a114a6SFelix Kuehling lower_32_bits(data64)); 522d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 523d5a114a6SFelix Kuehling upper_32_bits(data64)); 524d5a114a6SFelix Kuehling } else { 525d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 526d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr); 527d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 528d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 529d5a114a6SFelix Kuehling } 530d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 531d5a114a6SFelix Kuehling 532d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 533d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 534d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_base_hi); 535d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 536d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_lo); 537d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 538d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_hi); 539d5a114a6SFelix Kuehling 540d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 541d5a114a6SFelix Kuehling RB_ENABLE, 1); 542d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 543d5a114a6SFelix Kuehling 544d5a114a6SFelix Kuehling return 0; 545d5a114a6SFelix Kuehling } 546d5a114a6SFelix Kuehling 547d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 548d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 549d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 550d5a114a6SFelix Kuehling { 551d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 552d5a114a6SFelix Kuehling uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 553d5a114a6SFelix Kuehling uint32_t i = 0, reg; 554d5a114a6SFelix Kuehling #undef HQD_N_REGS 555d5a114a6SFelix Kuehling #define HQD_N_REGS (19+6+7+10) 556d5a114a6SFelix Kuehling 5576da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 558d5a114a6SFelix Kuehling if (*dump == NULL) 559d5a114a6SFelix Kuehling return -ENOMEM; 560d5a114a6SFelix Kuehling 561d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 562d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 563d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 564d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 565d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 566d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 567d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 568d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 569d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 570d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 571d5a114a6SFelix Kuehling 572d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 573d5a114a6SFelix Kuehling *n_regs = i; 574d5a114a6SFelix Kuehling 575d5a114a6SFelix Kuehling return 0; 576d5a114a6SFelix Kuehling } 577d5a114a6SFelix Kuehling 578d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 579d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 580d5a114a6SFelix Kuehling { 581d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 582d5a114a6SFelix Kuehling uint32_t act; 583d5a114a6SFelix Kuehling bool retval = false; 584d5a114a6SFelix Kuehling uint32_t low, high; 585d5a114a6SFelix Kuehling 586d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 587d5a114a6SFelix Kuehling act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 588d5a114a6SFelix Kuehling if (act) { 589d5a114a6SFelix Kuehling low = lower_32_bits(queue_address >> 8); 590d5a114a6SFelix Kuehling high = upper_32_bits(queue_address >> 8); 591d5a114a6SFelix Kuehling 592d5a114a6SFelix Kuehling if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 593d5a114a6SFelix Kuehling high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 594d5a114a6SFelix Kuehling retval = true; 595d5a114a6SFelix Kuehling } 596d5a114a6SFelix Kuehling release_queue(kgd); 597d5a114a6SFelix Kuehling return retval; 598d5a114a6SFelix Kuehling } 599d5a114a6SFelix Kuehling 600d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 601d5a114a6SFelix Kuehling { 602d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 603d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 604d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 605d5a114a6SFelix Kuehling uint32_t sdma_rlc_rb_cntl; 606d5a114a6SFelix Kuehling 607d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 608d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 609d5a114a6SFelix Kuehling m->sdma_queue_id); 610d5a114a6SFelix Kuehling 611d5a114a6SFelix Kuehling sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 612d5a114a6SFelix Kuehling 613d5a114a6SFelix Kuehling if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 614d5a114a6SFelix Kuehling return true; 615d5a114a6SFelix Kuehling 616d5a114a6SFelix Kuehling return false; 617d5a114a6SFelix Kuehling } 618d5a114a6SFelix Kuehling 619d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 620d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 621d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 622d5a114a6SFelix Kuehling uint32_t queue_id) 623d5a114a6SFelix Kuehling { 624d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 625d5a114a6SFelix Kuehling enum hqd_dequeue_request_type type; 626d5a114a6SFelix Kuehling unsigned long end_jiffies; 627d5a114a6SFelix Kuehling uint32_t temp; 628d5a114a6SFelix Kuehling struct v9_mqd *m = get_mqd(mqd); 629d5a114a6SFelix Kuehling 6301b0bfcffSShaoyun Liu if (adev->in_gpu_reset) 6311b0bfcffSShaoyun Liu return -EIO; 6321b0bfcffSShaoyun Liu 633d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 634d5a114a6SFelix Kuehling 635d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) 6361bff7f6cSTrigger Huang WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 637d5a114a6SFelix Kuehling 638d5a114a6SFelix Kuehling switch (reset_type) { 639d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 640d5a114a6SFelix Kuehling type = DRAIN_PIPE; 641d5a114a6SFelix Kuehling break; 642d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 643d5a114a6SFelix Kuehling type = RESET_WAVES; 644d5a114a6SFelix Kuehling break; 645d5a114a6SFelix Kuehling default: 646d5a114a6SFelix Kuehling type = DRAIN_PIPE; 647d5a114a6SFelix Kuehling break; 648d5a114a6SFelix Kuehling } 649d5a114a6SFelix Kuehling 6501bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 651d5a114a6SFelix Kuehling 652d5a114a6SFelix Kuehling end_jiffies = (utimeout * HZ / 1000) + jiffies; 653d5a114a6SFelix Kuehling while (true) { 654d5a114a6SFelix Kuehling temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 655d5a114a6SFelix Kuehling if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 656d5a114a6SFelix Kuehling break; 657d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) { 658d5a114a6SFelix Kuehling pr_err("cp queue preemption time out.\n"); 659d5a114a6SFelix Kuehling release_queue(kgd); 660d5a114a6SFelix Kuehling return -ETIME; 661d5a114a6SFelix Kuehling } 662d5a114a6SFelix Kuehling usleep_range(500, 1000); 663d5a114a6SFelix Kuehling } 664d5a114a6SFelix Kuehling 665d5a114a6SFelix Kuehling release_queue(kgd); 666d5a114a6SFelix Kuehling return 0; 667d5a114a6SFelix Kuehling } 668d5a114a6SFelix Kuehling 669d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 670d5a114a6SFelix Kuehling unsigned int utimeout) 671d5a114a6SFelix Kuehling { 672d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 673d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 674d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 675d5a114a6SFelix Kuehling uint32_t temp; 676d5a114a6SFelix Kuehling unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 677d5a114a6SFelix Kuehling 678d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 679d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 680d5a114a6SFelix Kuehling m->sdma_queue_id); 681d5a114a6SFelix Kuehling 682d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 683d5a114a6SFelix Kuehling temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 684d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 685d5a114a6SFelix Kuehling 686d5a114a6SFelix Kuehling while (true) { 687d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 688d5a114a6SFelix Kuehling if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 689d5a114a6SFelix Kuehling break; 690d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 691d5a114a6SFelix Kuehling return -ETIME; 692d5a114a6SFelix Kuehling usleep_range(500, 1000); 693d5a114a6SFelix Kuehling } 694d5a114a6SFelix Kuehling 695d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 696d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 697d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 698d5a114a6SFelix Kuehling SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 699d5a114a6SFelix Kuehling 700d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 701d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi = 702d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 703d5a114a6SFelix Kuehling 704d5a114a6SFelix Kuehling return 0; 705d5a114a6SFelix Kuehling } 706d5a114a6SFelix Kuehling 707d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 708d5a114a6SFelix Kuehling uint8_t vmid) 709d5a114a6SFelix Kuehling { 710d5a114a6SFelix Kuehling uint32_t reg; 711d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 712d5a114a6SFelix Kuehling 713d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 714d5a114a6SFelix Kuehling + vmid); 715d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 716d5a114a6SFelix Kuehling } 717d5a114a6SFelix Kuehling 718d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 719d5a114a6SFelix Kuehling uint8_t vmid) 720d5a114a6SFelix Kuehling { 721d5a114a6SFelix Kuehling uint32_t reg; 722d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 723d5a114a6SFelix Kuehling 724d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 725d5a114a6SFelix Kuehling + vmid); 726d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 727d5a114a6SFelix Kuehling } 728d5a114a6SFelix Kuehling 729e14ba95bSshaoyunl static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid, 730e14ba95bSshaoyunl uint32_t flush_type) 731d5a114a6SFelix Kuehling { 732d5a114a6SFelix Kuehling signed long r; 733d5a114a6SFelix Kuehling uint32_t seq; 734d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 735d5a114a6SFelix Kuehling 736d5a114a6SFelix Kuehling spin_lock(&adev->gfx.kiq.ring_lock); 737d5a114a6SFelix Kuehling amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 738d5a114a6SFelix Kuehling amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 739d5a114a6SFelix Kuehling amdgpu_ring_write(ring, 740d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 741d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 742d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_PASID(pasid) | 743e14ba95bSshaoyunl PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 744d5a114a6SFelix Kuehling amdgpu_fence_emit_polling(ring, &seq); 745d5a114a6SFelix Kuehling amdgpu_ring_commit(ring); 746d5a114a6SFelix Kuehling spin_unlock(&adev->gfx.kiq.ring_lock); 747d5a114a6SFelix Kuehling 748d5a114a6SFelix Kuehling r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 749d5a114a6SFelix Kuehling if (r < 1) { 750d5a114a6SFelix Kuehling DRM_ERROR("wait for kiq fence error: %ld.\n", r); 751d5a114a6SFelix Kuehling return -ETIME; 752d5a114a6SFelix Kuehling } 753d5a114a6SFelix Kuehling 754d5a114a6SFelix Kuehling return 0; 755d5a114a6SFelix Kuehling } 756d5a114a6SFelix Kuehling 757d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 758d5a114a6SFelix Kuehling { 759d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 760d5a114a6SFelix Kuehling int vmid; 761d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 762e14ba95bSshaoyunl uint32_t flush_type = 0; 763d5a114a6SFelix Kuehling 764bff418a2SShaoyun Liu if (adev->in_gpu_reset) 765bff418a2SShaoyun Liu return -EIO; 766e14ba95bSshaoyunl if (adev->gmc.xgmi.num_physical_nodes && 767e14ba95bSshaoyunl adev->asic_type == CHIP_VEGA20) 768e14ba95bSshaoyunl flush_type = 2; 769bff418a2SShaoyun Liu 770c66ed765SAndrey Grodzovsky if (ring->sched.ready) 771e14ba95bSshaoyunl return invalidate_tlbs_with_kiq(adev, pasid, flush_type); 772d5a114a6SFelix Kuehling 773d5a114a6SFelix Kuehling for (vmid = 0; vmid < 16; vmid++) { 774d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 775d5a114a6SFelix Kuehling continue; 776d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 777d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 778d5a114a6SFelix Kuehling == pasid) { 779e14ba95bSshaoyunl amdgpu_gmc_flush_gpu_tlb(adev, vmid, 780e14ba95bSshaoyunl flush_type); 781d5a114a6SFelix Kuehling break; 782d5a114a6SFelix Kuehling } 783d5a114a6SFelix Kuehling } 784d5a114a6SFelix Kuehling } 785d5a114a6SFelix Kuehling 786d5a114a6SFelix Kuehling return 0; 787d5a114a6SFelix Kuehling } 788d5a114a6SFelix Kuehling 789d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 790d5a114a6SFelix Kuehling { 791d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 792d5a114a6SFelix Kuehling 793d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 794d5a114a6SFelix Kuehling pr_err("non kfd vmid %d\n", vmid); 795d5a114a6SFelix Kuehling return 0; 796d5a114a6SFelix Kuehling } 797d5a114a6SFelix Kuehling 798e14ba95bSshaoyunl /* Use legacy mode tlb invalidation. 799e14ba95bSshaoyunl * 800e14ba95bSshaoyunl * Currently on Raven the code below is broken for anything but 801e14ba95bSshaoyunl * legacy mode due to a MMHUB power gating problem. A workaround 802e14ba95bSshaoyunl * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 803e14ba95bSshaoyunl * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 804e14ba95bSshaoyunl * bit. 805e14ba95bSshaoyunl * 806e14ba95bSshaoyunl * TODO 1: agree on the right set of invalidation registers for 807e14ba95bSshaoyunl * KFD use. Use the last one for now. Invalidate both GC and 808e14ba95bSshaoyunl * MMHUB. 809e14ba95bSshaoyunl * 810e14ba95bSshaoyunl * TODO 2: support range-based invalidation, requires kfg2kgd 811e14ba95bSshaoyunl * interface change 812e14ba95bSshaoyunl */ 813e14ba95bSshaoyunl amdgpu_gmc_flush_gpu_tlb(adev, vmid, 0); 814d5a114a6SFelix Kuehling return 0; 815d5a114a6SFelix Kuehling } 816d5a114a6SFelix Kuehling 817d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd) 818d5a114a6SFelix Kuehling { 819d5a114a6SFelix Kuehling return 0; 820d5a114a6SFelix Kuehling } 821d5a114a6SFelix Kuehling 822d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 823d5a114a6SFelix Kuehling unsigned int watch_point_id, 824d5a114a6SFelix Kuehling uint32_t cntl_val, 825d5a114a6SFelix Kuehling uint32_t addr_hi, 826d5a114a6SFelix Kuehling uint32_t addr_lo) 827d5a114a6SFelix Kuehling { 828d5a114a6SFelix Kuehling return 0; 829d5a114a6SFelix Kuehling } 830d5a114a6SFelix Kuehling 831d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 832d5a114a6SFelix Kuehling uint32_t gfx_index_val, 833d5a114a6SFelix Kuehling uint32_t sq_cmd) 834d5a114a6SFelix Kuehling { 835d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 836d5a114a6SFelix Kuehling uint32_t data = 0; 837d5a114a6SFelix Kuehling 838d5a114a6SFelix Kuehling mutex_lock(&adev->grbm_idx_mutex); 839d5a114a6SFelix Kuehling 8401bff7f6cSTrigger Huang WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); 841d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 842d5a114a6SFelix Kuehling 843d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 844d5a114a6SFelix Kuehling INSTANCE_BROADCAST_WRITES, 1); 845d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 846d5a114a6SFelix Kuehling SH_BROADCAST_WRITES, 1); 847d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 848d5a114a6SFelix Kuehling SE_BROADCAST_WRITES, 1); 849d5a114a6SFelix Kuehling 8501bff7f6cSTrigger Huang WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 851d5a114a6SFelix Kuehling mutex_unlock(&adev->grbm_idx_mutex); 852d5a114a6SFelix Kuehling 853d5a114a6SFelix Kuehling return 0; 854d5a114a6SFelix Kuehling } 855d5a114a6SFelix Kuehling 856d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 857d5a114a6SFelix Kuehling unsigned int watch_point_id, 858d5a114a6SFelix Kuehling unsigned int reg_offset) 859d5a114a6SFelix Kuehling { 860d5a114a6SFelix Kuehling return 0; 861d5a114a6SFelix Kuehling } 862d5a114a6SFelix Kuehling 863d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 864d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid) 865d5a114a6SFelix Kuehling { 866d5a114a6SFelix Kuehling /* No longer needed on GFXv9. The scratch base address is 867d5a114a6SFelix Kuehling * passed to the shader by the CP. It's the user mode driver's 868d5a114a6SFelix Kuehling * responsibility. 869d5a114a6SFelix Kuehling */ 870d5a114a6SFelix Kuehling } 871d5a114a6SFelix Kuehling 872d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 873e715c6d0SShaoyun Liu uint64_t page_table_base) 874d5a114a6SFelix Kuehling { 875d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 876d5a114a6SFelix Kuehling 877d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 878d5a114a6SFelix Kuehling pr_err("trying to set page table base for wrong VMID %u\n", 879d5a114a6SFelix Kuehling vmid); 880d5a114a6SFelix Kuehling return; 881d5a114a6SFelix Kuehling } 882d5a114a6SFelix Kuehling 883d5a114a6SFelix Kuehling /* TODO: take advantage of per-process address space size. For 884d5a114a6SFelix Kuehling * now, all processes share the same address space size, like 885d5a114a6SFelix Kuehling * on GFX8 and older. 886d5a114a6SFelix Kuehling */ 887435e2f97SYong Zhao mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 888d5a114a6SFelix Kuehling 889435e2f97SYong Zhao gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 890d5a114a6SFelix Kuehling } 891