1d5a114a6SFelix Kuehling /* 2d5a114a6SFelix Kuehling * Copyright 2014-2018 Advanced Micro Devices, Inc. 3d5a114a6SFelix Kuehling * 4d5a114a6SFelix Kuehling * Permission is hereby granted, free of charge, to any person obtaining a 5d5a114a6SFelix Kuehling * copy of this software and associated documentation files (the "Software"), 6d5a114a6SFelix Kuehling * to deal in the Software without restriction, including without limitation 7d5a114a6SFelix Kuehling * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d5a114a6SFelix Kuehling * and/or sell copies of the Software, and to permit persons to whom the 9d5a114a6SFelix Kuehling * Software is furnished to do so, subject to the following conditions: 10d5a114a6SFelix Kuehling * 11d5a114a6SFelix Kuehling * The above copyright notice and this permission notice shall be included in 12d5a114a6SFelix Kuehling * all copies or substantial portions of the Software. 13d5a114a6SFelix Kuehling * 14d5a114a6SFelix Kuehling * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d5a114a6SFelix Kuehling * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d5a114a6SFelix Kuehling * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d5a114a6SFelix Kuehling * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d5a114a6SFelix Kuehling * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d5a114a6SFelix Kuehling * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d5a114a6SFelix Kuehling * OTHER DEALINGS IN THE SOFTWARE. 21d5a114a6SFelix Kuehling */ 22d5a114a6SFelix Kuehling 23d5a114a6SFelix Kuehling #define pr_fmt(fmt) "kfd2kgd: " fmt 24d5a114a6SFelix Kuehling 25d5a114a6SFelix Kuehling #include <linux/module.h> 26d5a114a6SFelix Kuehling #include <linux/fdtable.h> 27d5a114a6SFelix Kuehling #include <linux/uaccess.h> 28d5a114a6SFelix Kuehling #include <linux/firmware.h> 29d5a114a6SFelix Kuehling #include <drm/drmP.h> 30d5a114a6SFelix Kuehling #include "amdgpu.h" 31d5a114a6SFelix Kuehling #include "amdgpu_amdkfd.h" 32d5a114a6SFelix Kuehling #include "amdgpu_ucode.h" 33d5a114a6SFelix Kuehling #include "soc15_hw_ip.h" 34d5a114a6SFelix Kuehling #include "gc/gc_9_0_offset.h" 35d5a114a6SFelix Kuehling #include "gc/gc_9_0_sh_mask.h" 36d5a114a6SFelix Kuehling #include "vega10_enum.h" 37d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_offset.h" 38d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_sh_mask.h" 39d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_offset.h" 40d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_sh_mask.h" 41d5a114a6SFelix Kuehling #include "athub/athub_1_0_offset.h" 42d5a114a6SFelix Kuehling #include "athub/athub_1_0_sh_mask.h" 43d5a114a6SFelix Kuehling #include "oss/osssys_4_0_offset.h" 44d5a114a6SFelix Kuehling #include "oss/osssys_4_0_sh_mask.h" 45d5a114a6SFelix Kuehling #include "soc15_common.h" 46d5a114a6SFelix Kuehling #include "v9_structs.h" 47d5a114a6SFelix Kuehling #include "soc15.h" 48d5a114a6SFelix Kuehling #include "soc15d.h" 49d5a114a6SFelix Kuehling 50d5a114a6SFelix Kuehling /* HACK: MMHUB and GC both have VM-related register with the same 51d5a114a6SFelix Kuehling * names but different offsets. Define the MMHUB register we need here 52d5a114a6SFelix Kuehling * with a prefix. A proper solution would be to move the functions 53d5a114a6SFelix Kuehling * programming these registers into gfx_v9_0.c and mmhub_v1_0.c 54d5a114a6SFelix Kuehling * respectively. 55d5a114a6SFelix Kuehling */ 56d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ 0x06f3 57d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ_BASE_IDX 0 58d5a114a6SFelix Kuehling 59d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705 60d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0 61d5a114a6SFelix Kuehling 62d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 63d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 64d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 65d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 66d5a114a6SFelix Kuehling 67d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 68d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 69d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 70d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 71d5a114a6SFelix Kuehling 72d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 73d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 74d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 75d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 76d5a114a6SFelix Kuehling 77d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 78d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 79d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 80d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 81d5a114a6SFelix Kuehling 82d5a114a6SFelix Kuehling #define V9_PIPE_PER_MEC (4) 83d5a114a6SFelix Kuehling #define V9_QUEUES_PER_PIPE_MEC (8) 84d5a114a6SFelix Kuehling 85d5a114a6SFelix Kuehling enum hqd_dequeue_request_type { 86d5a114a6SFelix Kuehling NO_ACTION = 0, 87d5a114a6SFelix Kuehling DRAIN_PIPE, 88d5a114a6SFelix Kuehling RESET_WAVES 89d5a114a6SFelix Kuehling }; 90d5a114a6SFelix Kuehling 91d5a114a6SFelix Kuehling /* 92d5a114a6SFelix Kuehling * Register access functions 93d5a114a6SFelix Kuehling */ 94d5a114a6SFelix Kuehling 95d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 96d5a114a6SFelix Kuehling uint32_t sh_mem_config, 97d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 98d5a114a6SFelix Kuehling uint32_t sh_mem_bases); 99d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 100d5a114a6SFelix Kuehling unsigned int vmid); 101d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 102d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 103d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 104d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 105d5a114a6SFelix Kuehling struct mm_struct *mm); 106d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 107d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 108d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 109d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 110d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm); 111d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 112d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 113d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 114d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 115d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id); 116d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 117d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 118d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 119d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 120d5a114a6SFelix Kuehling uint32_t queue_id); 121d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 122d5a114a6SFelix Kuehling unsigned int utimeout); 123d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd); 124d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 125d5a114a6SFelix Kuehling unsigned int watch_point_id, 126d5a114a6SFelix Kuehling uint32_t cntl_val, 127d5a114a6SFelix Kuehling uint32_t addr_hi, 128d5a114a6SFelix Kuehling uint32_t addr_lo); 129d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 130d5a114a6SFelix Kuehling uint32_t gfx_index_val, 131d5a114a6SFelix Kuehling uint32_t sq_cmd); 132d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 133d5a114a6SFelix Kuehling unsigned int watch_point_id, 134d5a114a6SFelix Kuehling unsigned int reg_offset); 135d5a114a6SFelix Kuehling 136d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 137d5a114a6SFelix Kuehling uint8_t vmid); 138d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 139d5a114a6SFelix Kuehling uint8_t vmid); 140d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 141d5a114a6SFelix Kuehling uint32_t page_table_base); 142d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 143d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 144d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid); 145d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 146d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 147d5a114a6SFelix Kuehling 148d5a114a6SFelix Kuehling /* Because of REG_GET_FIELD() being used, we put this function in the 149d5a114a6SFelix Kuehling * asic specific file. 150d5a114a6SFelix Kuehling */ 151d5a114a6SFelix Kuehling static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 152d5a114a6SFelix Kuehling struct tile_config *config) 153d5a114a6SFelix Kuehling { 154d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 155d5a114a6SFelix Kuehling 156d5a114a6SFelix Kuehling config->gb_addr_config = adev->gfx.config.gb_addr_config; 157d5a114a6SFelix Kuehling 158d5a114a6SFelix Kuehling config->tile_config_ptr = adev->gfx.config.tile_mode_array; 159d5a114a6SFelix Kuehling config->num_tile_configs = 160d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.tile_mode_array); 161d5a114a6SFelix Kuehling config->macro_tile_config_ptr = 162d5a114a6SFelix Kuehling adev->gfx.config.macrotile_mode_array; 163d5a114a6SFelix Kuehling config->num_macro_tile_configs = 164d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 165d5a114a6SFelix Kuehling 166d5a114a6SFelix Kuehling return 0; 167d5a114a6SFelix Kuehling } 168d5a114a6SFelix Kuehling 169d5a114a6SFelix Kuehling static const struct kfd2kgd_calls kfd2kgd = { 170d5a114a6SFelix Kuehling .init_gtt_mem_allocation = alloc_gtt_mem, 171d5a114a6SFelix Kuehling .free_gtt_mem = free_gtt_mem, 172d5a114a6SFelix Kuehling .get_local_mem_info = get_local_mem_info, 173d5a114a6SFelix Kuehling .get_gpu_clock_counter = get_gpu_clock_counter, 174d5a114a6SFelix Kuehling .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 175d5a114a6SFelix Kuehling .alloc_pasid = amdgpu_pasid_alloc, 176d5a114a6SFelix Kuehling .free_pasid = amdgpu_pasid_free, 177d5a114a6SFelix Kuehling .program_sh_mem_settings = kgd_program_sh_mem_settings, 178d5a114a6SFelix Kuehling .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 179d5a114a6SFelix Kuehling .init_interrupts = kgd_init_interrupts, 180d5a114a6SFelix Kuehling .hqd_load = kgd_hqd_load, 181d5a114a6SFelix Kuehling .hqd_sdma_load = kgd_hqd_sdma_load, 182d5a114a6SFelix Kuehling .hqd_dump = kgd_hqd_dump, 183d5a114a6SFelix Kuehling .hqd_sdma_dump = kgd_hqd_sdma_dump, 184d5a114a6SFelix Kuehling .hqd_is_occupied = kgd_hqd_is_occupied, 185d5a114a6SFelix Kuehling .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 186d5a114a6SFelix Kuehling .hqd_destroy = kgd_hqd_destroy, 187d5a114a6SFelix Kuehling .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 188d5a114a6SFelix Kuehling .address_watch_disable = kgd_address_watch_disable, 189d5a114a6SFelix Kuehling .address_watch_execute = kgd_address_watch_execute, 190d5a114a6SFelix Kuehling .wave_control_execute = kgd_wave_control_execute, 191d5a114a6SFelix Kuehling .address_watch_get_offset = kgd_address_watch_get_offset, 192d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_pasid = 193d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_pasid, 194d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_valid = 195d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_valid, 196d5a114a6SFelix Kuehling .get_fw_version = get_fw_version, 197d5a114a6SFelix Kuehling .set_scratch_backing_va = set_scratch_backing_va, 198d5a114a6SFelix Kuehling .get_tile_config = amdgpu_amdkfd_get_tile_config, 199d5a114a6SFelix Kuehling .get_cu_info = get_cu_info, 200d5a114a6SFelix Kuehling .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 201d5a114a6SFelix Kuehling .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 202d5a114a6SFelix Kuehling .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm, 203d5a114a6SFelix Kuehling .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 204d5a114a6SFelix Kuehling .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 205d5a114a6SFelix Kuehling .set_vm_context_page_table_base = set_vm_context_page_table_base, 206d5a114a6SFelix Kuehling .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 207d5a114a6SFelix Kuehling .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 208d5a114a6SFelix Kuehling .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 209d5a114a6SFelix Kuehling .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 210d5a114a6SFelix Kuehling .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 211d5a114a6SFelix Kuehling .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 212d5a114a6SFelix Kuehling .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 213d5a114a6SFelix Kuehling .invalidate_tlbs = invalidate_tlbs, 214d5a114a6SFelix Kuehling .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 215d5a114a6SFelix Kuehling .submit_ib = amdgpu_amdkfd_submit_ib, 21624da5a9cSShaoyun Liu .gpu_recover = amdgpu_amdkfd_gpu_reset 217d5a114a6SFelix Kuehling }; 218d5a114a6SFelix Kuehling 219d5a114a6SFelix Kuehling struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 220d5a114a6SFelix Kuehling { 221d5a114a6SFelix Kuehling return (struct kfd2kgd_calls *)&kfd2kgd; 222d5a114a6SFelix Kuehling } 223d5a114a6SFelix Kuehling 224d5a114a6SFelix Kuehling static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 225d5a114a6SFelix Kuehling { 226d5a114a6SFelix Kuehling return (struct amdgpu_device *)kgd; 227d5a114a6SFelix Kuehling } 228d5a114a6SFelix Kuehling 229d5a114a6SFelix Kuehling static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 230d5a114a6SFelix Kuehling uint32_t queue, uint32_t vmid) 231d5a114a6SFelix Kuehling { 232d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 233d5a114a6SFelix Kuehling 234d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 235d5a114a6SFelix Kuehling soc15_grbm_select(adev, mec, pipe, queue, vmid); 236d5a114a6SFelix Kuehling } 237d5a114a6SFelix Kuehling 238d5a114a6SFelix Kuehling static void unlock_srbm(struct kgd_dev *kgd) 239d5a114a6SFelix Kuehling { 240d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 241d5a114a6SFelix Kuehling 242d5a114a6SFelix Kuehling soc15_grbm_select(adev, 0, 0, 0, 0); 243d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 244d5a114a6SFelix Kuehling } 245d5a114a6SFelix Kuehling 246d5a114a6SFelix Kuehling static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 247d5a114a6SFelix Kuehling uint32_t queue_id) 248d5a114a6SFelix Kuehling { 249d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 250d5a114a6SFelix Kuehling 251d5a114a6SFelix Kuehling uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 252d5a114a6SFelix Kuehling uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 253d5a114a6SFelix Kuehling 254d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, queue_id, 0); 255d5a114a6SFelix Kuehling } 256d5a114a6SFelix Kuehling 257d5a114a6SFelix Kuehling static uint32_t get_queue_mask(struct amdgpu_device *adev, 258d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 259d5a114a6SFelix Kuehling { 260d5a114a6SFelix Kuehling unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 261d5a114a6SFelix Kuehling queue_id) & 31; 262d5a114a6SFelix Kuehling 263d5a114a6SFelix Kuehling return ((uint32_t)1) << bit; 264d5a114a6SFelix Kuehling } 265d5a114a6SFelix Kuehling 266d5a114a6SFelix Kuehling static void release_queue(struct kgd_dev *kgd) 267d5a114a6SFelix Kuehling { 268d5a114a6SFelix Kuehling unlock_srbm(kgd); 269d5a114a6SFelix Kuehling } 270d5a114a6SFelix Kuehling 271d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 272d5a114a6SFelix Kuehling uint32_t sh_mem_config, 273d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, 274d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_limit, 275d5a114a6SFelix Kuehling uint32_t sh_mem_bases) 276d5a114a6SFelix Kuehling { 277d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 278d5a114a6SFelix Kuehling 279d5a114a6SFelix Kuehling lock_srbm(kgd, 0, 0, 0, vmid); 280d5a114a6SFelix Kuehling 281d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 282d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 283d5a114a6SFelix Kuehling /* APE1 no longer exists on GFX9 */ 284d5a114a6SFelix Kuehling 285d5a114a6SFelix Kuehling unlock_srbm(kgd); 286d5a114a6SFelix Kuehling } 287d5a114a6SFelix Kuehling 288d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 289d5a114a6SFelix Kuehling unsigned int vmid) 290d5a114a6SFelix Kuehling { 291d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 292d5a114a6SFelix Kuehling 293d5a114a6SFelix Kuehling /* 294d5a114a6SFelix Kuehling * We have to assume that there is no outstanding mapping. 295d5a114a6SFelix Kuehling * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 296d5a114a6SFelix Kuehling * a mapping is in progress or because a mapping finished 297d5a114a6SFelix Kuehling * and the SW cleared it. 298d5a114a6SFelix Kuehling * So the protocol is to always wait & clear. 299d5a114a6SFelix Kuehling */ 300d5a114a6SFelix Kuehling uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 301d5a114a6SFelix Kuehling ATC_VMID0_PASID_MAPPING__VALID_MASK; 302d5a114a6SFelix Kuehling 303d5a114a6SFelix Kuehling /* 304d5a114a6SFelix Kuehling * need to do this twice, once for gfx and once for mmhub 305d5a114a6SFelix Kuehling * for ATC add 16 to VMID for mmhub, for IH different registers. 306d5a114a6SFelix Kuehling * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 307d5a114a6SFelix Kuehling */ 308d5a114a6SFelix Kuehling 309d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 310d5a114a6SFelix Kuehling pasid_mapping); 311d5a114a6SFelix Kuehling 312d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 313d5a114a6SFelix Kuehling ATHUB, 0, 314d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 315d5a114a6SFelix Kuehling (1U << vmid))) 316d5a114a6SFelix Kuehling cpu_relax(); 317d5a114a6SFelix Kuehling 318d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 319d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 320d5a114a6SFelix Kuehling 1U << vmid); 321d5a114a6SFelix Kuehling 322d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 323d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 324d5a114a6SFelix Kuehling pasid_mapping); 325d5a114a6SFelix Kuehling 326d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 327d5a114a6SFelix Kuehling pasid_mapping); 328d5a114a6SFelix Kuehling 329d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 330d5a114a6SFelix Kuehling ATHUB, 0, 331d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 332d5a114a6SFelix Kuehling (1U << (vmid + 16)))) 333d5a114a6SFelix Kuehling cpu_relax(); 334d5a114a6SFelix Kuehling 335d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 336d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 337d5a114a6SFelix Kuehling 1U << (vmid + 16)); 338d5a114a6SFelix Kuehling 339d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 340d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 341d5a114a6SFelix Kuehling pasid_mapping); 342d5a114a6SFelix Kuehling return 0; 343d5a114a6SFelix Kuehling } 344d5a114a6SFelix Kuehling 345d5a114a6SFelix Kuehling /* TODO - RING0 form of field is obsolete, seems to date back to SI 346d5a114a6SFelix Kuehling * but still works 347d5a114a6SFelix Kuehling */ 348d5a114a6SFelix Kuehling 349d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 350d5a114a6SFelix Kuehling { 351d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 352d5a114a6SFelix Kuehling uint32_t mec; 353d5a114a6SFelix Kuehling uint32_t pipe; 354d5a114a6SFelix Kuehling 355d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 356d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 357d5a114a6SFelix Kuehling 358d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, 0, 0); 359d5a114a6SFelix Kuehling 360d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 361d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 362d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 363d5a114a6SFelix Kuehling 364d5a114a6SFelix Kuehling unlock_srbm(kgd); 365d5a114a6SFelix Kuehling 366d5a114a6SFelix Kuehling return 0; 367d5a114a6SFelix Kuehling } 368d5a114a6SFelix Kuehling 369d5a114a6SFelix Kuehling static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 370d5a114a6SFelix Kuehling unsigned int engine_id, 371d5a114a6SFelix Kuehling unsigned int queue_id) 372d5a114a6SFelix Kuehling { 373d5a114a6SFelix Kuehling uint32_t base[2] = { 374d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, 375d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 376d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, 377d5a114a6SFelix Kuehling mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 378d5a114a6SFelix Kuehling }; 379d5a114a6SFelix Kuehling uint32_t retval; 380d5a114a6SFelix Kuehling 381d5a114a6SFelix Kuehling retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 382d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL); 383d5a114a6SFelix Kuehling 384d5a114a6SFelix Kuehling pr_debug("sdma base address: 0x%x\n", retval); 385d5a114a6SFelix Kuehling 386d5a114a6SFelix Kuehling return retval; 387d5a114a6SFelix Kuehling } 388d5a114a6SFelix Kuehling 389d5a114a6SFelix Kuehling static inline struct v9_mqd *get_mqd(void *mqd) 390d5a114a6SFelix Kuehling { 391d5a114a6SFelix Kuehling return (struct v9_mqd *)mqd; 392d5a114a6SFelix Kuehling } 393d5a114a6SFelix Kuehling 394d5a114a6SFelix Kuehling static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 395d5a114a6SFelix Kuehling { 396d5a114a6SFelix Kuehling return (struct v9_sdma_mqd *)mqd; 397d5a114a6SFelix Kuehling } 398d5a114a6SFelix Kuehling 399d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 400d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 401d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 402d5a114a6SFelix Kuehling struct mm_struct *mm) 403d5a114a6SFelix Kuehling { 404d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 405d5a114a6SFelix Kuehling struct v9_mqd *m; 406d5a114a6SFelix Kuehling uint32_t *mqd_hqd; 407d5a114a6SFelix Kuehling uint32_t reg, hqd_base, data; 408d5a114a6SFelix Kuehling 409d5a114a6SFelix Kuehling m = get_mqd(mqd); 410d5a114a6SFelix Kuehling 411d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 412d5a114a6SFelix Kuehling 413d5a114a6SFelix Kuehling /* HIQ is set during driver init period with vmid set to 0*/ 414d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) { 415d5a114a6SFelix Kuehling uint32_t value, mec, pipe; 416d5a114a6SFelix Kuehling 417d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 418d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 419d5a114a6SFelix Kuehling 420d5a114a6SFelix Kuehling pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 421d5a114a6SFelix Kuehling mec, pipe, queue_id); 422d5a114a6SFelix Kuehling value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 423d5a114a6SFelix Kuehling value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 424d5a114a6SFelix Kuehling ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 425d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 426d5a114a6SFelix Kuehling } 427d5a114a6SFelix Kuehling 428d5a114a6SFelix Kuehling /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 429d5a114a6SFelix Kuehling mqd_hqd = &m->cp_mqd_base_addr_lo; 430d5a114a6SFelix Kuehling hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 431d5a114a6SFelix Kuehling 432d5a114a6SFelix Kuehling for (reg = hqd_base; 433d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 434d5a114a6SFelix Kuehling WREG32(reg, mqd_hqd[reg - hqd_base]); 435d5a114a6SFelix Kuehling 436d5a114a6SFelix Kuehling 437d5a114a6SFelix Kuehling /* Activate doorbell logic before triggering WPTR poll. */ 438d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 439d5a114a6SFelix Kuehling CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 440d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 441d5a114a6SFelix Kuehling 442d5a114a6SFelix Kuehling if (wptr) { 443d5a114a6SFelix Kuehling /* Don't read wptr with get_user because the user 444d5a114a6SFelix Kuehling * context may not be accessible (if this function 445d5a114a6SFelix Kuehling * runs in a work queue). Instead trigger a one-shot 446d5a114a6SFelix Kuehling * polling read from memory in the CP. This assumes 447d5a114a6SFelix Kuehling * that wptr is GPU-accessible in the queue's VMID via 448d5a114a6SFelix Kuehling * ATC or SVM. WPTR==RPTR before starting the poll so 449d5a114a6SFelix Kuehling * the CP starts fetching new commands from the right 450d5a114a6SFelix Kuehling * place. 451d5a114a6SFelix Kuehling * 452d5a114a6SFelix Kuehling * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 453d5a114a6SFelix Kuehling * tricky. Assume that the queue didn't overflow. The 454d5a114a6SFelix Kuehling * number of valid bits in the 32-bit RPTR depends on 455d5a114a6SFelix Kuehling * the queue size. The remaining bits are taken from 456d5a114a6SFelix Kuehling * the saved 64-bit WPTR. If the WPTR wrapped, add the 457d5a114a6SFelix Kuehling * queue size. 458d5a114a6SFelix Kuehling */ 459d5a114a6SFelix Kuehling uint32_t queue_size = 460d5a114a6SFelix Kuehling 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 461d5a114a6SFelix Kuehling CP_HQD_PQ_CONTROL, QUEUE_SIZE); 462d5a114a6SFelix Kuehling uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 463d5a114a6SFelix Kuehling 464d5a114a6SFelix Kuehling if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 465d5a114a6SFelix Kuehling guessed_wptr += queue_size; 466d5a114a6SFelix Kuehling guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 467d5a114a6SFelix Kuehling guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 468d5a114a6SFelix Kuehling 469d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 470d5a114a6SFelix Kuehling lower_32_bits(guessed_wptr)); 471d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 472d5a114a6SFelix Kuehling upper_32_bits(guessed_wptr)); 473d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 474ebe1d22bSArnd Bergmann lower_32_bits((uintptr_t)wptr)); 475d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 476ebe1d22bSArnd Bergmann upper_32_bits((uintptr_t)wptr)); 477d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 478d5a114a6SFelix Kuehling get_queue_mask(adev, pipe_id, queue_id)); 479d5a114a6SFelix Kuehling } 480d5a114a6SFelix Kuehling 481d5a114a6SFelix Kuehling /* Start the EOP fetcher */ 482d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 483d5a114a6SFelix Kuehling REG_SET_FIELD(m->cp_hqd_eop_rptr, 484d5a114a6SFelix Kuehling CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 485d5a114a6SFelix Kuehling 486d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 487d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 488d5a114a6SFelix Kuehling 489d5a114a6SFelix Kuehling release_queue(kgd); 490d5a114a6SFelix Kuehling 491d5a114a6SFelix Kuehling return 0; 492d5a114a6SFelix Kuehling } 493d5a114a6SFelix Kuehling 494d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 495d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 496d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 497d5a114a6SFelix Kuehling { 498d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 499d5a114a6SFelix Kuehling uint32_t i = 0, reg; 500d5a114a6SFelix Kuehling #define HQD_N_REGS 56 501d5a114a6SFelix Kuehling #define DUMP_REG(addr) do { \ 502d5a114a6SFelix Kuehling if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 503d5a114a6SFelix Kuehling break; \ 504d5a114a6SFelix Kuehling (*dump)[i][0] = (addr) << 2; \ 505d5a114a6SFelix Kuehling (*dump)[i++][1] = RREG32(addr); \ 506d5a114a6SFelix Kuehling } while (0) 507d5a114a6SFelix Kuehling 5086da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 509d5a114a6SFelix Kuehling if (*dump == NULL) 510d5a114a6SFelix Kuehling return -ENOMEM; 511d5a114a6SFelix Kuehling 512d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 513d5a114a6SFelix Kuehling 514d5a114a6SFelix Kuehling for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 515d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 516d5a114a6SFelix Kuehling DUMP_REG(reg); 517d5a114a6SFelix Kuehling 518d5a114a6SFelix Kuehling release_queue(kgd); 519d5a114a6SFelix Kuehling 520d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 521d5a114a6SFelix Kuehling *n_regs = i; 522d5a114a6SFelix Kuehling 523d5a114a6SFelix Kuehling return 0; 524d5a114a6SFelix Kuehling } 525d5a114a6SFelix Kuehling 526d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 527d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm) 528d5a114a6SFelix Kuehling { 529d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 530d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 531d5a114a6SFelix Kuehling uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 532d5a114a6SFelix Kuehling unsigned long end_jiffies; 533d5a114a6SFelix Kuehling uint32_t data; 534d5a114a6SFelix Kuehling uint64_t data64; 535d5a114a6SFelix Kuehling uint64_t __user *wptr64 = (uint64_t __user *)wptr; 536d5a114a6SFelix Kuehling 537d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 538d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 539d5a114a6SFelix Kuehling m->sdma_queue_id); 540d5a114a6SFelix Kuehling sdmax_gfx_context_cntl = m->sdma_engine_id ? 541d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 542d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 543d5a114a6SFelix Kuehling 544d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 545d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 546d5a114a6SFelix Kuehling 547d5a114a6SFelix Kuehling end_jiffies = msecs_to_jiffies(2000) + jiffies; 548d5a114a6SFelix Kuehling while (true) { 549d5a114a6SFelix Kuehling data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 550d5a114a6SFelix Kuehling if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 551d5a114a6SFelix Kuehling break; 552d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 553d5a114a6SFelix Kuehling return -ETIME; 554d5a114a6SFelix Kuehling usleep_range(500, 1000); 555d5a114a6SFelix Kuehling } 556d5a114a6SFelix Kuehling data = RREG32(sdmax_gfx_context_cntl); 557d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 558d5a114a6SFelix Kuehling RESUME_CTX, 0); 559d5a114a6SFelix Kuehling WREG32(sdmax_gfx_context_cntl, data); 560d5a114a6SFelix Kuehling 561d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 562d5a114a6SFelix Kuehling m->sdmax_rlcx_doorbell_offset); 563d5a114a6SFelix Kuehling 564d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 565d5a114a6SFelix Kuehling ENABLE, 1); 566d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 567d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 568d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 569d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 570d5a114a6SFelix Kuehling 571d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 572d5a114a6SFelix Kuehling if (read_user_wptr(mm, wptr64, data64)) { 573d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 574d5a114a6SFelix Kuehling lower_32_bits(data64)); 575d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 576d5a114a6SFelix Kuehling upper_32_bits(data64)); 577d5a114a6SFelix Kuehling } else { 578d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 579d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr); 580d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 581d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 582d5a114a6SFelix Kuehling } 583d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 584d5a114a6SFelix Kuehling 585d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 586d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 587d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_base_hi); 588d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 589d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_lo); 590d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 591d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_hi); 592d5a114a6SFelix Kuehling 593d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 594d5a114a6SFelix Kuehling RB_ENABLE, 1); 595d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 596d5a114a6SFelix Kuehling 597d5a114a6SFelix Kuehling return 0; 598d5a114a6SFelix Kuehling } 599d5a114a6SFelix Kuehling 600d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 601d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 602d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 603d5a114a6SFelix Kuehling { 604d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 605d5a114a6SFelix Kuehling uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 606d5a114a6SFelix Kuehling uint32_t i = 0, reg; 607d5a114a6SFelix Kuehling #undef HQD_N_REGS 608d5a114a6SFelix Kuehling #define HQD_N_REGS (19+6+7+10) 609d5a114a6SFelix Kuehling 6106da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 611d5a114a6SFelix Kuehling if (*dump == NULL) 612d5a114a6SFelix Kuehling return -ENOMEM; 613d5a114a6SFelix Kuehling 614d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 615d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 616d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 617d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 618d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 619d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 620d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 621d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 622d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 623d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 624d5a114a6SFelix Kuehling 625d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 626d5a114a6SFelix Kuehling *n_regs = i; 627d5a114a6SFelix Kuehling 628d5a114a6SFelix Kuehling return 0; 629d5a114a6SFelix Kuehling } 630d5a114a6SFelix Kuehling 631d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 632d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 633d5a114a6SFelix Kuehling { 634d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 635d5a114a6SFelix Kuehling uint32_t act; 636d5a114a6SFelix Kuehling bool retval = false; 637d5a114a6SFelix Kuehling uint32_t low, high; 638d5a114a6SFelix Kuehling 639d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 640d5a114a6SFelix Kuehling act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 641d5a114a6SFelix Kuehling if (act) { 642d5a114a6SFelix Kuehling low = lower_32_bits(queue_address >> 8); 643d5a114a6SFelix Kuehling high = upper_32_bits(queue_address >> 8); 644d5a114a6SFelix Kuehling 645d5a114a6SFelix Kuehling if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 646d5a114a6SFelix Kuehling high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 647d5a114a6SFelix Kuehling retval = true; 648d5a114a6SFelix Kuehling } 649d5a114a6SFelix Kuehling release_queue(kgd); 650d5a114a6SFelix Kuehling return retval; 651d5a114a6SFelix Kuehling } 652d5a114a6SFelix Kuehling 653d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 654d5a114a6SFelix Kuehling { 655d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 656d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 657d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 658d5a114a6SFelix Kuehling uint32_t sdma_rlc_rb_cntl; 659d5a114a6SFelix Kuehling 660d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 661d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 662d5a114a6SFelix Kuehling m->sdma_queue_id); 663d5a114a6SFelix Kuehling 664d5a114a6SFelix Kuehling sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 665d5a114a6SFelix Kuehling 666d5a114a6SFelix Kuehling if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 667d5a114a6SFelix Kuehling return true; 668d5a114a6SFelix Kuehling 669d5a114a6SFelix Kuehling return false; 670d5a114a6SFelix Kuehling } 671d5a114a6SFelix Kuehling 672d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 673d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 674d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 675d5a114a6SFelix Kuehling uint32_t queue_id) 676d5a114a6SFelix Kuehling { 677d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 678d5a114a6SFelix Kuehling enum hqd_dequeue_request_type type; 679d5a114a6SFelix Kuehling unsigned long end_jiffies; 680d5a114a6SFelix Kuehling uint32_t temp; 681d5a114a6SFelix Kuehling struct v9_mqd *m = get_mqd(mqd); 682d5a114a6SFelix Kuehling 683d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 684d5a114a6SFelix Kuehling 685d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) 686d5a114a6SFelix Kuehling WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 687d5a114a6SFelix Kuehling 688d5a114a6SFelix Kuehling switch (reset_type) { 689d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 690d5a114a6SFelix Kuehling type = DRAIN_PIPE; 691d5a114a6SFelix Kuehling break; 692d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 693d5a114a6SFelix Kuehling type = RESET_WAVES; 694d5a114a6SFelix Kuehling break; 695d5a114a6SFelix Kuehling default: 696d5a114a6SFelix Kuehling type = DRAIN_PIPE; 697d5a114a6SFelix Kuehling break; 698d5a114a6SFelix Kuehling } 699d5a114a6SFelix Kuehling 700d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 701d5a114a6SFelix Kuehling 702d5a114a6SFelix Kuehling end_jiffies = (utimeout * HZ / 1000) + jiffies; 703d5a114a6SFelix Kuehling while (true) { 704d5a114a6SFelix Kuehling temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 705d5a114a6SFelix Kuehling if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 706d5a114a6SFelix Kuehling break; 707d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) { 708d5a114a6SFelix Kuehling pr_err("cp queue preemption time out.\n"); 709d5a114a6SFelix Kuehling release_queue(kgd); 710d5a114a6SFelix Kuehling return -ETIME; 711d5a114a6SFelix Kuehling } 712d5a114a6SFelix Kuehling usleep_range(500, 1000); 713d5a114a6SFelix Kuehling } 714d5a114a6SFelix Kuehling 715d5a114a6SFelix Kuehling release_queue(kgd); 716d5a114a6SFelix Kuehling return 0; 717d5a114a6SFelix Kuehling } 718d5a114a6SFelix Kuehling 719d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 720d5a114a6SFelix Kuehling unsigned int utimeout) 721d5a114a6SFelix Kuehling { 722d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 723d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 724d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 725d5a114a6SFelix Kuehling uint32_t temp; 726d5a114a6SFelix Kuehling unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 727d5a114a6SFelix Kuehling 728d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 729d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 730d5a114a6SFelix Kuehling m->sdma_queue_id); 731d5a114a6SFelix Kuehling 732d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 733d5a114a6SFelix Kuehling temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 734d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 735d5a114a6SFelix Kuehling 736d5a114a6SFelix Kuehling while (true) { 737d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 738d5a114a6SFelix Kuehling if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 739d5a114a6SFelix Kuehling break; 740d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 741d5a114a6SFelix Kuehling return -ETIME; 742d5a114a6SFelix Kuehling usleep_range(500, 1000); 743d5a114a6SFelix Kuehling } 744d5a114a6SFelix Kuehling 745d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 746d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 747d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 748d5a114a6SFelix Kuehling SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 749d5a114a6SFelix Kuehling 750d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 751d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi = 752d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 753d5a114a6SFelix Kuehling 754d5a114a6SFelix Kuehling return 0; 755d5a114a6SFelix Kuehling } 756d5a114a6SFelix Kuehling 757d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 758d5a114a6SFelix Kuehling uint8_t vmid) 759d5a114a6SFelix Kuehling { 760d5a114a6SFelix Kuehling uint32_t reg; 761d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 762d5a114a6SFelix Kuehling 763d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 764d5a114a6SFelix Kuehling + vmid); 765d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 766d5a114a6SFelix Kuehling } 767d5a114a6SFelix Kuehling 768d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 769d5a114a6SFelix Kuehling uint8_t vmid) 770d5a114a6SFelix Kuehling { 771d5a114a6SFelix Kuehling uint32_t reg; 772d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 773d5a114a6SFelix Kuehling 774d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 775d5a114a6SFelix Kuehling + vmid); 776d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 777d5a114a6SFelix Kuehling } 778d5a114a6SFelix Kuehling 779d5a114a6SFelix Kuehling static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 780d5a114a6SFelix Kuehling { 781d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 782d5a114a6SFelix Kuehling uint32_t req = (1 << vmid) | 783d5a114a6SFelix Kuehling (0 << VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT) | /* legacy */ 784d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK | 785d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK | 786d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK | 787d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK | 788d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK; 789d5a114a6SFelix Kuehling 790d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 791d5a114a6SFelix Kuehling 792d5a114a6SFelix Kuehling /* Use legacy mode tlb invalidation. 793d5a114a6SFelix Kuehling * 794d5a114a6SFelix Kuehling * Currently on Raven the code below is broken for anything but 795d5a114a6SFelix Kuehling * legacy mode due to a MMHUB power gating problem. A workaround 796d5a114a6SFelix Kuehling * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 797d5a114a6SFelix Kuehling * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 798d5a114a6SFelix Kuehling * bit. 799d5a114a6SFelix Kuehling * 800d5a114a6SFelix Kuehling * TODO 1: agree on the right set of invalidation registers for 801d5a114a6SFelix Kuehling * KFD use. Use the last one for now. Invalidate both GC and 802d5a114a6SFelix Kuehling * MMHUB. 803d5a114a6SFelix Kuehling * 804d5a114a6SFelix Kuehling * TODO 2: support range-based invalidation, requires kfg2kgd 805d5a114a6SFelix Kuehling * interface change 806d5a114a6SFelix Kuehling */ 807d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 808d5a114a6SFelix Kuehling 0xffffffff); 809d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 810d5a114a6SFelix Kuehling 0x0000001f); 811d5a114a6SFelix Kuehling 812d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 813d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 814d5a114a6SFelix Kuehling 0xffffffff); 815d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 816d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 817d5a114a6SFelix Kuehling 0x0000001f); 818d5a114a6SFelix Kuehling 819d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req); 820d5a114a6SFelix Kuehling 821d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ), 822d5a114a6SFelix Kuehling req); 823d5a114a6SFelix Kuehling 824d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) & 825d5a114a6SFelix Kuehling (1 << vmid))) 826d5a114a6SFelix Kuehling cpu_relax(); 827d5a114a6SFelix Kuehling 828d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0, 829d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ACK)) & 830d5a114a6SFelix Kuehling (1 << vmid))) 831d5a114a6SFelix Kuehling cpu_relax(); 832d5a114a6SFelix Kuehling 833d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 834d5a114a6SFelix Kuehling 835d5a114a6SFelix Kuehling } 836d5a114a6SFelix Kuehling 837d5a114a6SFelix Kuehling static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 838d5a114a6SFelix Kuehling { 839d5a114a6SFelix Kuehling signed long r; 840d5a114a6SFelix Kuehling uint32_t seq; 841d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 842d5a114a6SFelix Kuehling 843d5a114a6SFelix Kuehling spin_lock(&adev->gfx.kiq.ring_lock); 844d5a114a6SFelix Kuehling amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 845d5a114a6SFelix Kuehling amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 846d5a114a6SFelix Kuehling amdgpu_ring_write(ring, 847d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 848d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 849d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_PASID(pasid) | 850d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(0)); /* legacy */ 851d5a114a6SFelix Kuehling amdgpu_fence_emit_polling(ring, &seq); 852d5a114a6SFelix Kuehling amdgpu_ring_commit(ring); 853d5a114a6SFelix Kuehling spin_unlock(&adev->gfx.kiq.ring_lock); 854d5a114a6SFelix Kuehling 855d5a114a6SFelix Kuehling r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 856d5a114a6SFelix Kuehling if (r < 1) { 857d5a114a6SFelix Kuehling DRM_ERROR("wait for kiq fence error: %ld.\n", r); 858d5a114a6SFelix Kuehling return -ETIME; 859d5a114a6SFelix Kuehling } 860d5a114a6SFelix Kuehling 861d5a114a6SFelix Kuehling return 0; 862d5a114a6SFelix Kuehling } 863d5a114a6SFelix Kuehling 864d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 865d5a114a6SFelix Kuehling { 866d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 867d5a114a6SFelix Kuehling int vmid; 868d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 869d5a114a6SFelix Kuehling 870bff418a2SShaoyun Liu if (adev->in_gpu_reset) 871bff418a2SShaoyun Liu return -EIO; 872bff418a2SShaoyun Liu 873d5a114a6SFelix Kuehling if (ring->ready) 874d5a114a6SFelix Kuehling return invalidate_tlbs_with_kiq(adev, pasid); 875d5a114a6SFelix Kuehling 876d5a114a6SFelix Kuehling for (vmid = 0; vmid < 16; vmid++) { 877d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 878d5a114a6SFelix Kuehling continue; 879d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 880d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 881d5a114a6SFelix Kuehling == pasid) { 882d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 883d5a114a6SFelix Kuehling break; 884d5a114a6SFelix Kuehling } 885d5a114a6SFelix Kuehling } 886d5a114a6SFelix Kuehling } 887d5a114a6SFelix Kuehling 888d5a114a6SFelix Kuehling return 0; 889d5a114a6SFelix Kuehling } 890d5a114a6SFelix Kuehling 891d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 892d5a114a6SFelix Kuehling { 893d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 894d5a114a6SFelix Kuehling 895d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 896d5a114a6SFelix Kuehling pr_err("non kfd vmid %d\n", vmid); 897d5a114a6SFelix Kuehling return 0; 898d5a114a6SFelix Kuehling } 899d5a114a6SFelix Kuehling 900d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 901d5a114a6SFelix Kuehling return 0; 902d5a114a6SFelix Kuehling } 903d5a114a6SFelix Kuehling 904d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd) 905d5a114a6SFelix Kuehling { 906d5a114a6SFelix Kuehling return 0; 907d5a114a6SFelix Kuehling } 908d5a114a6SFelix Kuehling 909d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 910d5a114a6SFelix Kuehling unsigned int watch_point_id, 911d5a114a6SFelix Kuehling uint32_t cntl_val, 912d5a114a6SFelix Kuehling uint32_t addr_hi, 913d5a114a6SFelix Kuehling uint32_t addr_lo) 914d5a114a6SFelix Kuehling { 915d5a114a6SFelix Kuehling return 0; 916d5a114a6SFelix Kuehling } 917d5a114a6SFelix Kuehling 918d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 919d5a114a6SFelix Kuehling uint32_t gfx_index_val, 920d5a114a6SFelix Kuehling uint32_t sq_cmd) 921d5a114a6SFelix Kuehling { 922d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 923d5a114a6SFelix Kuehling uint32_t data = 0; 924d5a114a6SFelix Kuehling 925d5a114a6SFelix Kuehling mutex_lock(&adev->grbm_idx_mutex); 926d5a114a6SFelix Kuehling 927d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 928d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 929d5a114a6SFelix Kuehling 930d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 931d5a114a6SFelix Kuehling INSTANCE_BROADCAST_WRITES, 1); 932d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 933d5a114a6SFelix Kuehling SH_BROADCAST_WRITES, 1); 934d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 935d5a114a6SFelix Kuehling SE_BROADCAST_WRITES, 1); 936d5a114a6SFelix Kuehling 937d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 938d5a114a6SFelix Kuehling mutex_unlock(&adev->grbm_idx_mutex); 939d5a114a6SFelix Kuehling 940d5a114a6SFelix Kuehling return 0; 941d5a114a6SFelix Kuehling } 942d5a114a6SFelix Kuehling 943d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 944d5a114a6SFelix Kuehling unsigned int watch_point_id, 945d5a114a6SFelix Kuehling unsigned int reg_offset) 946d5a114a6SFelix Kuehling { 947d5a114a6SFelix Kuehling return 0; 948d5a114a6SFelix Kuehling } 949d5a114a6SFelix Kuehling 950d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 951d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid) 952d5a114a6SFelix Kuehling { 953d5a114a6SFelix Kuehling /* No longer needed on GFXv9. The scratch base address is 954d5a114a6SFelix Kuehling * passed to the shader by the CP. It's the user mode driver's 955d5a114a6SFelix Kuehling * responsibility. 956d5a114a6SFelix Kuehling */ 957d5a114a6SFelix Kuehling } 958d5a114a6SFelix Kuehling 959d5a114a6SFelix Kuehling /* FIXME: Does this need to be ASIC-specific code? */ 960d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 961d5a114a6SFelix Kuehling { 962d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 963d5a114a6SFelix Kuehling const union amdgpu_firmware_header *hdr; 964d5a114a6SFelix Kuehling 965d5a114a6SFelix Kuehling switch (type) { 966d5a114a6SFelix Kuehling case KGD_ENGINE_PFP: 967d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.pfp_fw->data; 968d5a114a6SFelix Kuehling break; 969d5a114a6SFelix Kuehling 970d5a114a6SFelix Kuehling case KGD_ENGINE_ME: 971d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.me_fw->data; 972d5a114a6SFelix Kuehling break; 973d5a114a6SFelix Kuehling 974d5a114a6SFelix Kuehling case KGD_ENGINE_CE: 975d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.ce_fw->data; 976d5a114a6SFelix Kuehling break; 977d5a114a6SFelix Kuehling 978d5a114a6SFelix Kuehling case KGD_ENGINE_MEC1: 979d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec_fw->data; 980d5a114a6SFelix Kuehling break; 981d5a114a6SFelix Kuehling 982d5a114a6SFelix Kuehling case KGD_ENGINE_MEC2: 983d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec2_fw->data; 984d5a114a6SFelix Kuehling break; 985d5a114a6SFelix Kuehling 986d5a114a6SFelix Kuehling case KGD_ENGINE_RLC: 987d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.rlc_fw->data; 988d5a114a6SFelix Kuehling break; 989d5a114a6SFelix Kuehling 990d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA1: 991d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[0].fw->data; 992d5a114a6SFelix Kuehling break; 993d5a114a6SFelix Kuehling 994d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA2: 995d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[1].fw->data; 996d5a114a6SFelix Kuehling break; 997d5a114a6SFelix Kuehling 998d5a114a6SFelix Kuehling default: 999d5a114a6SFelix Kuehling return 0; 1000d5a114a6SFelix Kuehling } 1001d5a114a6SFelix Kuehling 1002d5a114a6SFelix Kuehling if (hdr == NULL) 1003d5a114a6SFelix Kuehling return 0; 1004d5a114a6SFelix Kuehling 1005d5a114a6SFelix Kuehling /* Only 12 bit in use*/ 1006d5a114a6SFelix Kuehling return hdr->common.ucode_version; 1007d5a114a6SFelix Kuehling } 1008d5a114a6SFelix Kuehling 1009d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 1010d5a114a6SFelix Kuehling uint32_t page_table_base) 1011d5a114a6SFelix Kuehling { 1012d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 1013d5a114a6SFelix Kuehling uint64_t base = (uint64_t)page_table_base << PAGE_SHIFT | 1014d5a114a6SFelix Kuehling AMDGPU_PTE_VALID; 1015d5a114a6SFelix Kuehling 1016d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 1017d5a114a6SFelix Kuehling pr_err("trying to set page table base for wrong VMID %u\n", 1018d5a114a6SFelix Kuehling vmid); 1019d5a114a6SFelix Kuehling return; 1020d5a114a6SFelix Kuehling } 1021d5a114a6SFelix Kuehling 1022d5a114a6SFelix Kuehling /* TODO: take advantage of per-process address space size. For 1023d5a114a6SFelix Kuehling * now, all processes share the same address space size, like 1024d5a114a6SFelix Kuehling * on GFX8 and older. 1025d5a114a6SFelix Kuehling */ 1026d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1027d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1028d5a114a6SFelix Kuehling 1029d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1030d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1031d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1032d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1033d5a114a6SFelix Kuehling 1034d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1035d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1036d5a114a6SFelix Kuehling 1037d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1038d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1039d5a114a6SFelix Kuehling 1040d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1041d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1042d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1043d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1044d5a114a6SFelix Kuehling 1045d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1046d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1047d5a114a6SFelix Kuehling } 1048