1d5a114a6SFelix Kuehling /* 2d5a114a6SFelix Kuehling * Copyright 2014-2018 Advanced Micro Devices, Inc. 3d5a114a6SFelix Kuehling * 4d5a114a6SFelix Kuehling * Permission is hereby granted, free of charge, to any person obtaining a 5d5a114a6SFelix Kuehling * copy of this software and associated documentation files (the "Software"), 6d5a114a6SFelix Kuehling * to deal in the Software without restriction, including without limitation 7d5a114a6SFelix Kuehling * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d5a114a6SFelix Kuehling * and/or sell copies of the Software, and to permit persons to whom the 9d5a114a6SFelix Kuehling * Software is furnished to do so, subject to the following conditions: 10d5a114a6SFelix Kuehling * 11d5a114a6SFelix Kuehling * The above copyright notice and this permission notice shall be included in 12d5a114a6SFelix Kuehling * all copies or substantial portions of the Software. 13d5a114a6SFelix Kuehling * 14d5a114a6SFelix Kuehling * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d5a114a6SFelix Kuehling * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d5a114a6SFelix Kuehling * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d5a114a6SFelix Kuehling * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d5a114a6SFelix Kuehling * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d5a114a6SFelix Kuehling * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d5a114a6SFelix Kuehling * OTHER DEALINGS IN THE SOFTWARE. 21d5a114a6SFelix Kuehling */ 22d5a114a6SFelix Kuehling 23d5a114a6SFelix Kuehling #define pr_fmt(fmt) "kfd2kgd: " fmt 24d5a114a6SFelix Kuehling 25d5a114a6SFelix Kuehling #include <linux/module.h> 26d5a114a6SFelix Kuehling #include <linux/fdtable.h> 27d5a114a6SFelix Kuehling #include <linux/uaccess.h> 28d5a114a6SFelix Kuehling #include <linux/firmware.h> 29d5a114a6SFelix Kuehling #include <drm/drmP.h> 30d5a114a6SFelix Kuehling #include "amdgpu.h" 31d5a114a6SFelix Kuehling #include "amdgpu_amdkfd.h" 32d5a114a6SFelix Kuehling #include "amdgpu_ucode.h" 33d5a114a6SFelix Kuehling #include "soc15_hw_ip.h" 34d5a114a6SFelix Kuehling #include "gc/gc_9_0_offset.h" 35d5a114a6SFelix Kuehling #include "gc/gc_9_0_sh_mask.h" 36d5a114a6SFelix Kuehling #include "vega10_enum.h" 37d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_offset.h" 38d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_sh_mask.h" 39d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_offset.h" 40d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_sh_mask.h" 41d5a114a6SFelix Kuehling #include "athub/athub_1_0_offset.h" 42d5a114a6SFelix Kuehling #include "athub/athub_1_0_sh_mask.h" 43d5a114a6SFelix Kuehling #include "oss/osssys_4_0_offset.h" 44d5a114a6SFelix Kuehling #include "oss/osssys_4_0_sh_mask.h" 45d5a114a6SFelix Kuehling #include "soc15_common.h" 46d5a114a6SFelix Kuehling #include "v9_structs.h" 47d5a114a6SFelix Kuehling #include "soc15.h" 48d5a114a6SFelix Kuehling #include "soc15d.h" 49d5a114a6SFelix Kuehling 50d5a114a6SFelix Kuehling /* HACK: MMHUB and GC both have VM-related register with the same 51d5a114a6SFelix Kuehling * names but different offsets. Define the MMHUB register we need here 52d5a114a6SFelix Kuehling * with a prefix. A proper solution would be to move the functions 53d5a114a6SFelix Kuehling * programming these registers into gfx_v9_0.c and mmhub_v1_0.c 54d5a114a6SFelix Kuehling * respectively. 55d5a114a6SFelix Kuehling */ 56d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ 0x06f3 57d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_REQ_BASE_IDX 0 58d5a114a6SFelix Kuehling 59d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK 0x0705 60d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ACK_BASE_IDX 0 61d5a114a6SFelix Kuehling 62d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x072b 63d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 0 64d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x072c 65d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 0 66d5a114a6SFelix Kuehling 67d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x074b 68d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 0 69d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x074c 70d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 0 71d5a114a6SFelix Kuehling 72d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x076b 73d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 0 74d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x076c 75d5a114a6SFelix Kuehling #define mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 0 76d5a114a6SFelix Kuehling 77d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x0727 78d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 0 79d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x0728 80d5a114a6SFelix Kuehling #define mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 0 81d5a114a6SFelix Kuehling 82d5a114a6SFelix Kuehling #define V9_PIPE_PER_MEC (4) 83d5a114a6SFelix Kuehling #define V9_QUEUES_PER_PIPE_MEC (8) 84d5a114a6SFelix Kuehling 85d5a114a6SFelix Kuehling enum hqd_dequeue_request_type { 86d5a114a6SFelix Kuehling NO_ACTION = 0, 87d5a114a6SFelix Kuehling DRAIN_PIPE, 88d5a114a6SFelix Kuehling RESET_WAVES 89d5a114a6SFelix Kuehling }; 90d5a114a6SFelix Kuehling 91d5a114a6SFelix Kuehling /* 92d5a114a6SFelix Kuehling * Register access functions 93d5a114a6SFelix Kuehling */ 94d5a114a6SFelix Kuehling 95d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 96d5a114a6SFelix Kuehling uint32_t sh_mem_config, 97d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 98d5a114a6SFelix Kuehling uint32_t sh_mem_bases); 99d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 100d5a114a6SFelix Kuehling unsigned int vmid); 101d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 102d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 103d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 104d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 105d5a114a6SFelix Kuehling struct mm_struct *mm); 106d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 107d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 108d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 109d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 110d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm); 111d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 112d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 113d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs); 114d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 115d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id); 116d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 117d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 118d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 119d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 120d5a114a6SFelix Kuehling uint32_t queue_id); 121d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 122d5a114a6SFelix Kuehling unsigned int utimeout); 123d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd); 124d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 125d5a114a6SFelix Kuehling unsigned int watch_point_id, 126d5a114a6SFelix Kuehling uint32_t cntl_val, 127d5a114a6SFelix Kuehling uint32_t addr_hi, 128d5a114a6SFelix Kuehling uint32_t addr_lo); 129d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 130d5a114a6SFelix Kuehling uint32_t gfx_index_val, 131d5a114a6SFelix Kuehling uint32_t sq_cmd); 132d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 133d5a114a6SFelix Kuehling unsigned int watch_point_id, 134d5a114a6SFelix Kuehling unsigned int reg_offset); 135d5a114a6SFelix Kuehling 136d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 137d5a114a6SFelix Kuehling uint8_t vmid); 138d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 139d5a114a6SFelix Kuehling uint8_t vmid); 140d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 141d5a114a6SFelix Kuehling uint32_t page_table_base); 142d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 143d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 144d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid); 145d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 146d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 147d5a114a6SFelix Kuehling 148d5a114a6SFelix Kuehling /* Because of REG_GET_FIELD() being used, we put this function in the 149d5a114a6SFelix Kuehling * asic specific file. 150d5a114a6SFelix Kuehling */ 151d5a114a6SFelix Kuehling static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 152d5a114a6SFelix Kuehling struct tile_config *config) 153d5a114a6SFelix Kuehling { 154d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 155d5a114a6SFelix Kuehling 156d5a114a6SFelix Kuehling config->gb_addr_config = adev->gfx.config.gb_addr_config; 157d5a114a6SFelix Kuehling 158d5a114a6SFelix Kuehling config->tile_config_ptr = adev->gfx.config.tile_mode_array; 159d5a114a6SFelix Kuehling config->num_tile_configs = 160d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.tile_mode_array); 161d5a114a6SFelix Kuehling config->macro_tile_config_ptr = 162d5a114a6SFelix Kuehling adev->gfx.config.macrotile_mode_array; 163d5a114a6SFelix Kuehling config->num_macro_tile_configs = 164d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 165d5a114a6SFelix Kuehling 166d5a114a6SFelix Kuehling return 0; 167d5a114a6SFelix Kuehling } 168d5a114a6SFelix Kuehling 169d5a114a6SFelix Kuehling static const struct kfd2kgd_calls kfd2kgd = { 170d5a114a6SFelix Kuehling .init_gtt_mem_allocation = alloc_gtt_mem, 171d5a114a6SFelix Kuehling .free_gtt_mem = free_gtt_mem, 172d5a114a6SFelix Kuehling .get_local_mem_info = get_local_mem_info, 173d5a114a6SFelix Kuehling .get_gpu_clock_counter = get_gpu_clock_counter, 174d5a114a6SFelix Kuehling .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 175d5a114a6SFelix Kuehling .alloc_pasid = amdgpu_pasid_alloc, 176d5a114a6SFelix Kuehling .free_pasid = amdgpu_pasid_free, 177d5a114a6SFelix Kuehling .program_sh_mem_settings = kgd_program_sh_mem_settings, 178d5a114a6SFelix Kuehling .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 179d5a114a6SFelix Kuehling .init_interrupts = kgd_init_interrupts, 180d5a114a6SFelix Kuehling .hqd_load = kgd_hqd_load, 181d5a114a6SFelix Kuehling .hqd_sdma_load = kgd_hqd_sdma_load, 182d5a114a6SFelix Kuehling .hqd_dump = kgd_hqd_dump, 183d5a114a6SFelix Kuehling .hqd_sdma_dump = kgd_hqd_sdma_dump, 184d5a114a6SFelix Kuehling .hqd_is_occupied = kgd_hqd_is_occupied, 185d5a114a6SFelix Kuehling .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 186d5a114a6SFelix Kuehling .hqd_destroy = kgd_hqd_destroy, 187d5a114a6SFelix Kuehling .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 188d5a114a6SFelix Kuehling .address_watch_disable = kgd_address_watch_disable, 189d5a114a6SFelix Kuehling .address_watch_execute = kgd_address_watch_execute, 190d5a114a6SFelix Kuehling .wave_control_execute = kgd_wave_control_execute, 191d5a114a6SFelix Kuehling .address_watch_get_offset = kgd_address_watch_get_offset, 192d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_pasid = 193d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_pasid, 194d5a114a6SFelix Kuehling .get_atc_vmid_pasid_mapping_valid = 195d5a114a6SFelix Kuehling get_atc_vmid_pasid_mapping_valid, 196d5a114a6SFelix Kuehling .get_fw_version = get_fw_version, 197d5a114a6SFelix Kuehling .set_scratch_backing_va = set_scratch_backing_va, 198d5a114a6SFelix Kuehling .get_tile_config = amdgpu_amdkfd_get_tile_config, 199d5a114a6SFelix Kuehling .get_cu_info = get_cu_info, 200d5a114a6SFelix Kuehling .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 201d5a114a6SFelix Kuehling .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 202d5a114a6SFelix Kuehling .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm, 203d5a114a6SFelix Kuehling .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 204bf47afbaSOak Zeng .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm, 205d5a114a6SFelix Kuehling .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 206d5a114a6SFelix Kuehling .set_vm_context_page_table_base = set_vm_context_page_table_base, 207d5a114a6SFelix Kuehling .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 208d5a114a6SFelix Kuehling .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 209d5a114a6SFelix Kuehling .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 210d5a114a6SFelix Kuehling .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 211d5a114a6SFelix Kuehling .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 212d5a114a6SFelix Kuehling .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 213d5a114a6SFelix Kuehling .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 214d5a114a6SFelix Kuehling .invalidate_tlbs = invalidate_tlbs, 215d5a114a6SFelix Kuehling .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 216d5a114a6SFelix Kuehling .submit_ib = amdgpu_amdkfd_submit_ib, 21701c097dbSFelix Kuehling .gpu_recover = amdgpu_amdkfd_gpu_reset, 21801c097dbSFelix Kuehling .set_compute_idle = amdgpu_amdkfd_set_compute_idle 219d5a114a6SFelix Kuehling }; 220d5a114a6SFelix Kuehling 221d5a114a6SFelix Kuehling struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 222d5a114a6SFelix Kuehling { 223d5a114a6SFelix Kuehling return (struct kfd2kgd_calls *)&kfd2kgd; 224d5a114a6SFelix Kuehling } 225d5a114a6SFelix Kuehling 226d5a114a6SFelix Kuehling static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 227d5a114a6SFelix Kuehling { 228d5a114a6SFelix Kuehling return (struct amdgpu_device *)kgd; 229d5a114a6SFelix Kuehling } 230d5a114a6SFelix Kuehling 231d5a114a6SFelix Kuehling static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 232d5a114a6SFelix Kuehling uint32_t queue, uint32_t vmid) 233d5a114a6SFelix Kuehling { 234d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 235d5a114a6SFelix Kuehling 236d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 237d5a114a6SFelix Kuehling soc15_grbm_select(adev, mec, pipe, queue, vmid); 238d5a114a6SFelix Kuehling } 239d5a114a6SFelix Kuehling 240d5a114a6SFelix Kuehling static void unlock_srbm(struct kgd_dev *kgd) 241d5a114a6SFelix Kuehling { 242d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 243d5a114a6SFelix Kuehling 244d5a114a6SFelix Kuehling soc15_grbm_select(adev, 0, 0, 0, 0); 245d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 246d5a114a6SFelix Kuehling } 247d5a114a6SFelix Kuehling 248d5a114a6SFelix Kuehling static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 249d5a114a6SFelix Kuehling uint32_t queue_id) 250d5a114a6SFelix Kuehling { 251d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 252d5a114a6SFelix Kuehling 253d5a114a6SFelix Kuehling uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 254d5a114a6SFelix Kuehling uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 255d5a114a6SFelix Kuehling 256d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, queue_id, 0); 257d5a114a6SFelix Kuehling } 258d5a114a6SFelix Kuehling 259d5a114a6SFelix Kuehling static uint32_t get_queue_mask(struct amdgpu_device *adev, 260d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 261d5a114a6SFelix Kuehling { 262d5a114a6SFelix Kuehling unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 263d5a114a6SFelix Kuehling queue_id) & 31; 264d5a114a6SFelix Kuehling 265d5a114a6SFelix Kuehling return ((uint32_t)1) << bit; 266d5a114a6SFelix Kuehling } 267d5a114a6SFelix Kuehling 268d5a114a6SFelix Kuehling static void release_queue(struct kgd_dev *kgd) 269d5a114a6SFelix Kuehling { 270d5a114a6SFelix Kuehling unlock_srbm(kgd); 271d5a114a6SFelix Kuehling } 272d5a114a6SFelix Kuehling 273d5a114a6SFelix Kuehling static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 274d5a114a6SFelix Kuehling uint32_t sh_mem_config, 275d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, 276d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_limit, 277d5a114a6SFelix Kuehling uint32_t sh_mem_bases) 278d5a114a6SFelix Kuehling { 279d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 280d5a114a6SFelix Kuehling 281d5a114a6SFelix Kuehling lock_srbm(kgd, 0, 0, 0, vmid); 282d5a114a6SFelix Kuehling 283d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 284d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 285d5a114a6SFelix Kuehling /* APE1 no longer exists on GFX9 */ 286d5a114a6SFelix Kuehling 287d5a114a6SFelix Kuehling unlock_srbm(kgd); 288d5a114a6SFelix Kuehling } 289d5a114a6SFelix Kuehling 290d5a114a6SFelix Kuehling static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 291d5a114a6SFelix Kuehling unsigned int vmid) 292d5a114a6SFelix Kuehling { 293d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 294d5a114a6SFelix Kuehling 295d5a114a6SFelix Kuehling /* 296d5a114a6SFelix Kuehling * We have to assume that there is no outstanding mapping. 297d5a114a6SFelix Kuehling * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 298d5a114a6SFelix Kuehling * a mapping is in progress or because a mapping finished 299d5a114a6SFelix Kuehling * and the SW cleared it. 300d5a114a6SFelix Kuehling * So the protocol is to always wait & clear. 301d5a114a6SFelix Kuehling */ 302d5a114a6SFelix Kuehling uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 303d5a114a6SFelix Kuehling ATC_VMID0_PASID_MAPPING__VALID_MASK; 304d5a114a6SFelix Kuehling 305d5a114a6SFelix Kuehling /* 306d5a114a6SFelix Kuehling * need to do this twice, once for gfx and once for mmhub 307d5a114a6SFelix Kuehling * for ATC add 16 to VMID for mmhub, for IH different registers. 308d5a114a6SFelix Kuehling * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 309d5a114a6SFelix Kuehling */ 310d5a114a6SFelix Kuehling 311d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 312d5a114a6SFelix Kuehling pasid_mapping); 313d5a114a6SFelix Kuehling 314d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 315d5a114a6SFelix Kuehling ATHUB, 0, 316d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 317d5a114a6SFelix Kuehling (1U << vmid))) 318d5a114a6SFelix Kuehling cpu_relax(); 319d5a114a6SFelix Kuehling 320d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 321d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 322d5a114a6SFelix Kuehling 1U << vmid); 323d5a114a6SFelix Kuehling 324d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 325d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 326d5a114a6SFelix Kuehling pasid_mapping); 327d5a114a6SFelix Kuehling 328d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 329d5a114a6SFelix Kuehling pasid_mapping); 330d5a114a6SFelix Kuehling 331d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 332d5a114a6SFelix Kuehling ATHUB, 0, 333d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 334d5a114a6SFelix Kuehling (1U << (vmid + 16)))) 335d5a114a6SFelix Kuehling cpu_relax(); 336d5a114a6SFelix Kuehling 337d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 338d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 339d5a114a6SFelix Kuehling 1U << (vmid + 16)); 340d5a114a6SFelix Kuehling 341d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 342d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 343d5a114a6SFelix Kuehling pasid_mapping); 344d5a114a6SFelix Kuehling return 0; 345d5a114a6SFelix Kuehling } 346d5a114a6SFelix Kuehling 347d5a114a6SFelix Kuehling /* TODO - RING0 form of field is obsolete, seems to date back to SI 348d5a114a6SFelix Kuehling * but still works 349d5a114a6SFelix Kuehling */ 350d5a114a6SFelix Kuehling 351d5a114a6SFelix Kuehling static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 352d5a114a6SFelix Kuehling { 353d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 354d5a114a6SFelix Kuehling uint32_t mec; 355d5a114a6SFelix Kuehling uint32_t pipe; 356d5a114a6SFelix Kuehling 357d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 358d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 359d5a114a6SFelix Kuehling 360d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, 0, 0); 361d5a114a6SFelix Kuehling 362d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 363d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 364d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 365d5a114a6SFelix Kuehling 366d5a114a6SFelix Kuehling unlock_srbm(kgd); 367d5a114a6SFelix Kuehling 368d5a114a6SFelix Kuehling return 0; 369d5a114a6SFelix Kuehling } 370d5a114a6SFelix Kuehling 371d5a114a6SFelix Kuehling static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 372d5a114a6SFelix Kuehling unsigned int engine_id, 373d5a114a6SFelix Kuehling unsigned int queue_id) 374d5a114a6SFelix Kuehling { 375d5a114a6SFelix Kuehling uint32_t base[2] = { 376d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, 377d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 378d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, 379d5a114a6SFelix Kuehling mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 380d5a114a6SFelix Kuehling }; 381d5a114a6SFelix Kuehling uint32_t retval; 382d5a114a6SFelix Kuehling 383d5a114a6SFelix Kuehling retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 384d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL); 385d5a114a6SFelix Kuehling 386d5a114a6SFelix Kuehling pr_debug("sdma base address: 0x%x\n", retval); 387d5a114a6SFelix Kuehling 388d5a114a6SFelix Kuehling return retval; 389d5a114a6SFelix Kuehling } 390d5a114a6SFelix Kuehling 391d5a114a6SFelix Kuehling static inline struct v9_mqd *get_mqd(void *mqd) 392d5a114a6SFelix Kuehling { 393d5a114a6SFelix Kuehling return (struct v9_mqd *)mqd; 394d5a114a6SFelix Kuehling } 395d5a114a6SFelix Kuehling 396d5a114a6SFelix Kuehling static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 397d5a114a6SFelix Kuehling { 398d5a114a6SFelix Kuehling return (struct v9_sdma_mqd *)mqd; 399d5a114a6SFelix Kuehling } 400d5a114a6SFelix Kuehling 401d5a114a6SFelix Kuehling static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 402d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 403d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 404d5a114a6SFelix Kuehling struct mm_struct *mm) 405d5a114a6SFelix Kuehling { 406d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 407d5a114a6SFelix Kuehling struct v9_mqd *m; 408d5a114a6SFelix Kuehling uint32_t *mqd_hqd; 409d5a114a6SFelix Kuehling uint32_t reg, hqd_base, data; 410d5a114a6SFelix Kuehling 411d5a114a6SFelix Kuehling m = get_mqd(mqd); 412d5a114a6SFelix Kuehling 413d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 414d5a114a6SFelix Kuehling 415d5a114a6SFelix Kuehling /* HIQ is set during driver init period with vmid set to 0*/ 416d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) { 417d5a114a6SFelix Kuehling uint32_t value, mec, pipe; 418d5a114a6SFelix Kuehling 419d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 420d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 421d5a114a6SFelix Kuehling 422d5a114a6SFelix Kuehling pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 423d5a114a6SFelix Kuehling mec, pipe, queue_id); 424d5a114a6SFelix Kuehling value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 425d5a114a6SFelix Kuehling value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 426d5a114a6SFelix Kuehling ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 427d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 428d5a114a6SFelix Kuehling } 429d5a114a6SFelix Kuehling 430d5a114a6SFelix Kuehling /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 431d5a114a6SFelix Kuehling mqd_hqd = &m->cp_mqd_base_addr_lo; 432d5a114a6SFelix Kuehling hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 433d5a114a6SFelix Kuehling 434d5a114a6SFelix Kuehling for (reg = hqd_base; 435d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 436d5a114a6SFelix Kuehling WREG32(reg, mqd_hqd[reg - hqd_base]); 437d5a114a6SFelix Kuehling 438d5a114a6SFelix Kuehling 439d5a114a6SFelix Kuehling /* Activate doorbell logic before triggering WPTR poll. */ 440d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 441d5a114a6SFelix Kuehling CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 442d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 443d5a114a6SFelix Kuehling 444d5a114a6SFelix Kuehling if (wptr) { 445d5a114a6SFelix Kuehling /* Don't read wptr with get_user because the user 446d5a114a6SFelix Kuehling * context may not be accessible (if this function 447d5a114a6SFelix Kuehling * runs in a work queue). Instead trigger a one-shot 448d5a114a6SFelix Kuehling * polling read from memory in the CP. This assumes 449d5a114a6SFelix Kuehling * that wptr is GPU-accessible in the queue's VMID via 450d5a114a6SFelix Kuehling * ATC or SVM. WPTR==RPTR before starting the poll so 451d5a114a6SFelix Kuehling * the CP starts fetching new commands from the right 452d5a114a6SFelix Kuehling * place. 453d5a114a6SFelix Kuehling * 454d5a114a6SFelix Kuehling * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 455d5a114a6SFelix Kuehling * tricky. Assume that the queue didn't overflow. The 456d5a114a6SFelix Kuehling * number of valid bits in the 32-bit RPTR depends on 457d5a114a6SFelix Kuehling * the queue size. The remaining bits are taken from 458d5a114a6SFelix Kuehling * the saved 64-bit WPTR. If the WPTR wrapped, add the 459d5a114a6SFelix Kuehling * queue size. 460d5a114a6SFelix Kuehling */ 461d5a114a6SFelix Kuehling uint32_t queue_size = 462d5a114a6SFelix Kuehling 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 463d5a114a6SFelix Kuehling CP_HQD_PQ_CONTROL, QUEUE_SIZE); 464d5a114a6SFelix Kuehling uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 465d5a114a6SFelix Kuehling 466d5a114a6SFelix Kuehling if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 467d5a114a6SFelix Kuehling guessed_wptr += queue_size; 468d5a114a6SFelix Kuehling guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 469d5a114a6SFelix Kuehling guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 470d5a114a6SFelix Kuehling 471d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 472d5a114a6SFelix Kuehling lower_32_bits(guessed_wptr)); 473d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 474d5a114a6SFelix Kuehling upper_32_bits(guessed_wptr)); 475d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 476ebe1d22bSArnd Bergmann lower_32_bits((uintptr_t)wptr)); 477d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 478ebe1d22bSArnd Bergmann upper_32_bits((uintptr_t)wptr)); 479d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 480d5a114a6SFelix Kuehling get_queue_mask(adev, pipe_id, queue_id)); 481d5a114a6SFelix Kuehling } 482d5a114a6SFelix Kuehling 483d5a114a6SFelix Kuehling /* Start the EOP fetcher */ 484d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 485d5a114a6SFelix Kuehling REG_SET_FIELD(m->cp_hqd_eop_rptr, 486d5a114a6SFelix Kuehling CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 487d5a114a6SFelix Kuehling 488d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 489d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 490d5a114a6SFelix Kuehling 491d5a114a6SFelix Kuehling release_queue(kgd); 492d5a114a6SFelix Kuehling 493d5a114a6SFelix Kuehling return 0; 494d5a114a6SFelix Kuehling } 495d5a114a6SFelix Kuehling 496d5a114a6SFelix Kuehling static int kgd_hqd_dump(struct kgd_dev *kgd, 497d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 498d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 499d5a114a6SFelix Kuehling { 500d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 501d5a114a6SFelix Kuehling uint32_t i = 0, reg; 502d5a114a6SFelix Kuehling #define HQD_N_REGS 56 503d5a114a6SFelix Kuehling #define DUMP_REG(addr) do { \ 504d5a114a6SFelix Kuehling if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 505d5a114a6SFelix Kuehling break; \ 506d5a114a6SFelix Kuehling (*dump)[i][0] = (addr) << 2; \ 507d5a114a6SFelix Kuehling (*dump)[i++][1] = RREG32(addr); \ 508d5a114a6SFelix Kuehling } while (0) 509d5a114a6SFelix Kuehling 5106da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 511d5a114a6SFelix Kuehling if (*dump == NULL) 512d5a114a6SFelix Kuehling return -ENOMEM; 513d5a114a6SFelix Kuehling 514d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 515d5a114a6SFelix Kuehling 516d5a114a6SFelix Kuehling for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 517d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 518d5a114a6SFelix Kuehling DUMP_REG(reg); 519d5a114a6SFelix Kuehling 520d5a114a6SFelix Kuehling release_queue(kgd); 521d5a114a6SFelix Kuehling 522d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 523d5a114a6SFelix Kuehling *n_regs = i; 524d5a114a6SFelix Kuehling 525d5a114a6SFelix Kuehling return 0; 526d5a114a6SFelix Kuehling } 527d5a114a6SFelix Kuehling 528d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 529d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm) 530d5a114a6SFelix Kuehling { 531d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 532d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 533d5a114a6SFelix Kuehling uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 534d5a114a6SFelix Kuehling unsigned long end_jiffies; 535d5a114a6SFelix Kuehling uint32_t data; 536d5a114a6SFelix Kuehling uint64_t data64; 537d5a114a6SFelix Kuehling uint64_t __user *wptr64 = (uint64_t __user *)wptr; 538d5a114a6SFelix Kuehling 539d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 540d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 541d5a114a6SFelix Kuehling m->sdma_queue_id); 542d5a114a6SFelix Kuehling sdmax_gfx_context_cntl = m->sdma_engine_id ? 543d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 544d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 545d5a114a6SFelix Kuehling 546d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 547d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 548d5a114a6SFelix Kuehling 549d5a114a6SFelix Kuehling end_jiffies = msecs_to_jiffies(2000) + jiffies; 550d5a114a6SFelix Kuehling while (true) { 551d5a114a6SFelix Kuehling data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 552d5a114a6SFelix Kuehling if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 553d5a114a6SFelix Kuehling break; 554d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 555d5a114a6SFelix Kuehling return -ETIME; 556d5a114a6SFelix Kuehling usleep_range(500, 1000); 557d5a114a6SFelix Kuehling } 558d5a114a6SFelix Kuehling data = RREG32(sdmax_gfx_context_cntl); 559d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 560d5a114a6SFelix Kuehling RESUME_CTX, 0); 561d5a114a6SFelix Kuehling WREG32(sdmax_gfx_context_cntl, data); 562d5a114a6SFelix Kuehling 563d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 564d5a114a6SFelix Kuehling m->sdmax_rlcx_doorbell_offset); 565d5a114a6SFelix Kuehling 566d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 567d5a114a6SFelix Kuehling ENABLE, 1); 568d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 569d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 570d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 571d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 572d5a114a6SFelix Kuehling 573d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 574d5a114a6SFelix Kuehling if (read_user_wptr(mm, wptr64, data64)) { 575d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 576d5a114a6SFelix Kuehling lower_32_bits(data64)); 577d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 578d5a114a6SFelix Kuehling upper_32_bits(data64)); 579d5a114a6SFelix Kuehling } else { 580d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 581d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr); 582d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 583d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 584d5a114a6SFelix Kuehling } 585d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 586d5a114a6SFelix Kuehling 587d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 588d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 589d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_base_hi); 590d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 591d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_lo); 592d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 593d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_hi); 594d5a114a6SFelix Kuehling 595d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 596d5a114a6SFelix Kuehling RB_ENABLE, 1); 597d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 598d5a114a6SFelix Kuehling 599d5a114a6SFelix Kuehling return 0; 600d5a114a6SFelix Kuehling } 601d5a114a6SFelix Kuehling 602d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 603d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 604d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 605d5a114a6SFelix Kuehling { 606d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 607d5a114a6SFelix Kuehling uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 608d5a114a6SFelix Kuehling uint32_t i = 0, reg; 609d5a114a6SFelix Kuehling #undef HQD_N_REGS 610d5a114a6SFelix Kuehling #define HQD_N_REGS (19+6+7+10) 611d5a114a6SFelix Kuehling 6126da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 613d5a114a6SFelix Kuehling if (*dump == NULL) 614d5a114a6SFelix Kuehling return -ENOMEM; 615d5a114a6SFelix Kuehling 616d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 617d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 618d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 619d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 620d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 621d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 622d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 623d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 624d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 625d5a114a6SFelix Kuehling DUMP_REG(sdma_base_addr + reg); 626d5a114a6SFelix Kuehling 627d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 628d5a114a6SFelix Kuehling *n_regs = i; 629d5a114a6SFelix Kuehling 630d5a114a6SFelix Kuehling return 0; 631d5a114a6SFelix Kuehling } 632d5a114a6SFelix Kuehling 633d5a114a6SFelix Kuehling static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 634d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 635d5a114a6SFelix Kuehling { 636d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 637d5a114a6SFelix Kuehling uint32_t act; 638d5a114a6SFelix Kuehling bool retval = false; 639d5a114a6SFelix Kuehling uint32_t low, high; 640d5a114a6SFelix Kuehling 641d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 642d5a114a6SFelix Kuehling act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 643d5a114a6SFelix Kuehling if (act) { 644d5a114a6SFelix Kuehling low = lower_32_bits(queue_address >> 8); 645d5a114a6SFelix Kuehling high = upper_32_bits(queue_address >> 8); 646d5a114a6SFelix Kuehling 647d5a114a6SFelix Kuehling if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 648d5a114a6SFelix Kuehling high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 649d5a114a6SFelix Kuehling retval = true; 650d5a114a6SFelix Kuehling } 651d5a114a6SFelix Kuehling release_queue(kgd); 652d5a114a6SFelix Kuehling return retval; 653d5a114a6SFelix Kuehling } 654d5a114a6SFelix Kuehling 655d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 656d5a114a6SFelix Kuehling { 657d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 658d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 659d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 660d5a114a6SFelix Kuehling uint32_t sdma_rlc_rb_cntl; 661d5a114a6SFelix Kuehling 662d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 663d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 664d5a114a6SFelix Kuehling m->sdma_queue_id); 665d5a114a6SFelix Kuehling 666d5a114a6SFelix Kuehling sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 667d5a114a6SFelix Kuehling 668d5a114a6SFelix Kuehling if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 669d5a114a6SFelix Kuehling return true; 670d5a114a6SFelix Kuehling 671d5a114a6SFelix Kuehling return false; 672d5a114a6SFelix Kuehling } 673d5a114a6SFelix Kuehling 674d5a114a6SFelix Kuehling static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 675d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 676d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 677d5a114a6SFelix Kuehling uint32_t queue_id) 678d5a114a6SFelix Kuehling { 679d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 680d5a114a6SFelix Kuehling enum hqd_dequeue_request_type type; 681d5a114a6SFelix Kuehling unsigned long end_jiffies; 682d5a114a6SFelix Kuehling uint32_t temp; 683d5a114a6SFelix Kuehling struct v9_mqd *m = get_mqd(mqd); 684d5a114a6SFelix Kuehling 6851b0bfcffSShaoyun Liu if (adev->in_gpu_reset) 6861b0bfcffSShaoyun Liu return -EIO; 6871b0bfcffSShaoyun Liu 688d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 689d5a114a6SFelix Kuehling 690d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) 691d5a114a6SFelix Kuehling WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 692d5a114a6SFelix Kuehling 693d5a114a6SFelix Kuehling switch (reset_type) { 694d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 695d5a114a6SFelix Kuehling type = DRAIN_PIPE; 696d5a114a6SFelix Kuehling break; 697d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 698d5a114a6SFelix Kuehling type = RESET_WAVES; 699d5a114a6SFelix Kuehling break; 700d5a114a6SFelix Kuehling default: 701d5a114a6SFelix Kuehling type = DRAIN_PIPE; 702d5a114a6SFelix Kuehling break; 703d5a114a6SFelix Kuehling } 704d5a114a6SFelix Kuehling 705d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 706d5a114a6SFelix Kuehling 707d5a114a6SFelix Kuehling end_jiffies = (utimeout * HZ / 1000) + jiffies; 708d5a114a6SFelix Kuehling while (true) { 709d5a114a6SFelix Kuehling temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 710d5a114a6SFelix Kuehling if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 711d5a114a6SFelix Kuehling break; 712d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) { 713d5a114a6SFelix Kuehling pr_err("cp queue preemption time out.\n"); 714d5a114a6SFelix Kuehling release_queue(kgd); 715d5a114a6SFelix Kuehling return -ETIME; 716d5a114a6SFelix Kuehling } 717d5a114a6SFelix Kuehling usleep_range(500, 1000); 718d5a114a6SFelix Kuehling } 719d5a114a6SFelix Kuehling 720d5a114a6SFelix Kuehling release_queue(kgd); 721d5a114a6SFelix Kuehling return 0; 722d5a114a6SFelix Kuehling } 723d5a114a6SFelix Kuehling 724d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 725d5a114a6SFelix Kuehling unsigned int utimeout) 726d5a114a6SFelix Kuehling { 727d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 728d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 729d5a114a6SFelix Kuehling uint32_t sdma_base_addr; 730d5a114a6SFelix Kuehling uint32_t temp; 731d5a114a6SFelix Kuehling unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 732d5a114a6SFelix Kuehling 733d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 734d5a114a6SFelix Kuehling sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 735d5a114a6SFelix Kuehling m->sdma_queue_id); 736d5a114a6SFelix Kuehling 737d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 738d5a114a6SFelix Kuehling temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 739d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 740d5a114a6SFelix Kuehling 741d5a114a6SFelix Kuehling while (true) { 742d5a114a6SFelix Kuehling temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 743d5a114a6SFelix Kuehling if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 744d5a114a6SFelix Kuehling break; 745d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) 746d5a114a6SFelix Kuehling return -ETIME; 747d5a114a6SFelix Kuehling usleep_range(500, 1000); 748d5a114a6SFelix Kuehling } 749d5a114a6SFelix Kuehling 750d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 751d5a114a6SFelix Kuehling WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 752d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 753d5a114a6SFelix Kuehling SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 754d5a114a6SFelix Kuehling 755d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 756d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi = 757d5a114a6SFelix Kuehling RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 758d5a114a6SFelix Kuehling 759d5a114a6SFelix Kuehling return 0; 760d5a114a6SFelix Kuehling } 761d5a114a6SFelix Kuehling 762d5a114a6SFelix Kuehling static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 763d5a114a6SFelix Kuehling uint8_t vmid) 764d5a114a6SFelix Kuehling { 765d5a114a6SFelix Kuehling uint32_t reg; 766d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 767d5a114a6SFelix Kuehling 768d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 769d5a114a6SFelix Kuehling + vmid); 770d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 771d5a114a6SFelix Kuehling } 772d5a114a6SFelix Kuehling 773d5a114a6SFelix Kuehling static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 774d5a114a6SFelix Kuehling uint8_t vmid) 775d5a114a6SFelix Kuehling { 776d5a114a6SFelix Kuehling uint32_t reg; 777d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 778d5a114a6SFelix Kuehling 779d5a114a6SFelix Kuehling reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 780d5a114a6SFelix Kuehling + vmid); 781d5a114a6SFelix Kuehling return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 782d5a114a6SFelix Kuehling } 783d5a114a6SFelix Kuehling 784d5a114a6SFelix Kuehling static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 785d5a114a6SFelix Kuehling { 786d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 787d5a114a6SFelix Kuehling uint32_t req = (1 << vmid) | 788d5a114a6SFelix Kuehling (0 << VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT) | /* legacy */ 789d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK | 790d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK | 791d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK | 792d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK | 793d5a114a6SFelix Kuehling VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK; 794d5a114a6SFelix Kuehling 795d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 796d5a114a6SFelix Kuehling 797d5a114a6SFelix Kuehling /* Use legacy mode tlb invalidation. 798d5a114a6SFelix Kuehling * 799d5a114a6SFelix Kuehling * Currently on Raven the code below is broken for anything but 800d5a114a6SFelix Kuehling * legacy mode due to a MMHUB power gating problem. A workaround 801d5a114a6SFelix Kuehling * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 802d5a114a6SFelix Kuehling * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 803d5a114a6SFelix Kuehling * bit. 804d5a114a6SFelix Kuehling * 805d5a114a6SFelix Kuehling * TODO 1: agree on the right set of invalidation registers for 806d5a114a6SFelix Kuehling * KFD use. Use the last one for now. Invalidate both GC and 807d5a114a6SFelix Kuehling * MMHUB. 808d5a114a6SFelix Kuehling * 809d5a114a6SFelix Kuehling * TODO 2: support range-based invalidation, requires kfg2kgd 810d5a114a6SFelix Kuehling * interface change 811d5a114a6SFelix Kuehling */ 812d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 813d5a114a6SFelix Kuehling 0xffffffff); 814d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 815d5a114a6SFelix Kuehling 0x0000001f); 816d5a114a6SFelix Kuehling 817d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 818d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_LO32), 819d5a114a6SFelix Kuehling 0xffffffff); 820d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, 821d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ADDR_RANGE_HI32), 822d5a114a6SFelix Kuehling 0x0000001f); 823d5a114a6SFelix Kuehling 824d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_REQ), req); 825d5a114a6SFelix Kuehling 826d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_INVALIDATE_ENG16_REQ), 827d5a114a6SFelix Kuehling req); 828d5a114a6SFelix Kuehling 829d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG16_ACK)) & 830d5a114a6SFelix Kuehling (1 << vmid))) 831d5a114a6SFelix Kuehling cpu_relax(); 832d5a114a6SFelix Kuehling 833d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET(MMHUB, 0, 834d5a114a6SFelix Kuehling mmMMHUB_VM_INVALIDATE_ENG16_ACK)) & 835d5a114a6SFelix Kuehling (1 << vmid))) 836d5a114a6SFelix Kuehling cpu_relax(); 837d5a114a6SFelix Kuehling 838d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 839d5a114a6SFelix Kuehling 840d5a114a6SFelix Kuehling } 841d5a114a6SFelix Kuehling 842d5a114a6SFelix Kuehling static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 843d5a114a6SFelix Kuehling { 844d5a114a6SFelix Kuehling signed long r; 845d5a114a6SFelix Kuehling uint32_t seq; 846d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 847d5a114a6SFelix Kuehling 848d5a114a6SFelix Kuehling spin_lock(&adev->gfx.kiq.ring_lock); 849d5a114a6SFelix Kuehling amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 850d5a114a6SFelix Kuehling amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 851d5a114a6SFelix Kuehling amdgpu_ring_write(ring, 852d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 853d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 854d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_PASID(pasid) | 855d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(0)); /* legacy */ 856d5a114a6SFelix Kuehling amdgpu_fence_emit_polling(ring, &seq); 857d5a114a6SFelix Kuehling amdgpu_ring_commit(ring); 858d5a114a6SFelix Kuehling spin_unlock(&adev->gfx.kiq.ring_lock); 859d5a114a6SFelix Kuehling 860d5a114a6SFelix Kuehling r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 861d5a114a6SFelix Kuehling if (r < 1) { 862d5a114a6SFelix Kuehling DRM_ERROR("wait for kiq fence error: %ld.\n", r); 863d5a114a6SFelix Kuehling return -ETIME; 864d5a114a6SFelix Kuehling } 865d5a114a6SFelix Kuehling 866d5a114a6SFelix Kuehling return 0; 867d5a114a6SFelix Kuehling } 868d5a114a6SFelix Kuehling 869d5a114a6SFelix Kuehling static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 870d5a114a6SFelix Kuehling { 871d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 872d5a114a6SFelix Kuehling int vmid; 873d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 874d5a114a6SFelix Kuehling 875bff418a2SShaoyun Liu if (adev->in_gpu_reset) 876bff418a2SShaoyun Liu return -EIO; 877bff418a2SShaoyun Liu 878d5a114a6SFelix Kuehling if (ring->ready) 879d5a114a6SFelix Kuehling return invalidate_tlbs_with_kiq(adev, pasid); 880d5a114a6SFelix Kuehling 881d5a114a6SFelix Kuehling for (vmid = 0; vmid < 16; vmid++) { 882d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 883d5a114a6SFelix Kuehling continue; 884d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 885d5a114a6SFelix Kuehling if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 886d5a114a6SFelix Kuehling == pasid) { 887d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 888d5a114a6SFelix Kuehling break; 889d5a114a6SFelix Kuehling } 890d5a114a6SFelix Kuehling } 891d5a114a6SFelix Kuehling } 892d5a114a6SFelix Kuehling 893d5a114a6SFelix Kuehling return 0; 894d5a114a6SFelix Kuehling } 895d5a114a6SFelix Kuehling 896d5a114a6SFelix Kuehling static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 897d5a114a6SFelix Kuehling { 898d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 899d5a114a6SFelix Kuehling 900d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 901d5a114a6SFelix Kuehling pr_err("non kfd vmid %d\n", vmid); 902d5a114a6SFelix Kuehling return 0; 903d5a114a6SFelix Kuehling } 904d5a114a6SFelix Kuehling 905d5a114a6SFelix Kuehling write_vmid_invalidate_request(kgd, vmid); 906d5a114a6SFelix Kuehling return 0; 907d5a114a6SFelix Kuehling } 908d5a114a6SFelix Kuehling 909d5a114a6SFelix Kuehling static int kgd_address_watch_disable(struct kgd_dev *kgd) 910d5a114a6SFelix Kuehling { 911d5a114a6SFelix Kuehling return 0; 912d5a114a6SFelix Kuehling } 913d5a114a6SFelix Kuehling 914d5a114a6SFelix Kuehling static int kgd_address_watch_execute(struct kgd_dev *kgd, 915d5a114a6SFelix Kuehling unsigned int watch_point_id, 916d5a114a6SFelix Kuehling uint32_t cntl_val, 917d5a114a6SFelix Kuehling uint32_t addr_hi, 918d5a114a6SFelix Kuehling uint32_t addr_lo) 919d5a114a6SFelix Kuehling { 920d5a114a6SFelix Kuehling return 0; 921d5a114a6SFelix Kuehling } 922d5a114a6SFelix Kuehling 923d5a114a6SFelix Kuehling static int kgd_wave_control_execute(struct kgd_dev *kgd, 924d5a114a6SFelix Kuehling uint32_t gfx_index_val, 925d5a114a6SFelix Kuehling uint32_t sq_cmd) 926d5a114a6SFelix Kuehling { 927d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 928d5a114a6SFelix Kuehling uint32_t data = 0; 929d5a114a6SFelix Kuehling 930d5a114a6SFelix Kuehling mutex_lock(&adev->grbm_idx_mutex); 931d5a114a6SFelix Kuehling 932d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 933d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 934d5a114a6SFelix Kuehling 935d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 936d5a114a6SFelix Kuehling INSTANCE_BROADCAST_WRITES, 1); 937d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 938d5a114a6SFelix Kuehling SH_BROADCAST_WRITES, 1); 939d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 940d5a114a6SFelix Kuehling SE_BROADCAST_WRITES, 1); 941d5a114a6SFelix Kuehling 942d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 943d5a114a6SFelix Kuehling mutex_unlock(&adev->grbm_idx_mutex); 944d5a114a6SFelix Kuehling 945d5a114a6SFelix Kuehling return 0; 946d5a114a6SFelix Kuehling } 947d5a114a6SFelix Kuehling 948d5a114a6SFelix Kuehling static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 949d5a114a6SFelix Kuehling unsigned int watch_point_id, 950d5a114a6SFelix Kuehling unsigned int reg_offset) 951d5a114a6SFelix Kuehling { 952d5a114a6SFelix Kuehling return 0; 953d5a114a6SFelix Kuehling } 954d5a114a6SFelix Kuehling 955d5a114a6SFelix Kuehling static void set_scratch_backing_va(struct kgd_dev *kgd, 956d5a114a6SFelix Kuehling uint64_t va, uint32_t vmid) 957d5a114a6SFelix Kuehling { 958d5a114a6SFelix Kuehling /* No longer needed on GFXv9. The scratch base address is 959d5a114a6SFelix Kuehling * passed to the shader by the CP. It's the user mode driver's 960d5a114a6SFelix Kuehling * responsibility. 961d5a114a6SFelix Kuehling */ 962d5a114a6SFelix Kuehling } 963d5a114a6SFelix Kuehling 964d5a114a6SFelix Kuehling /* FIXME: Does this need to be ASIC-specific code? */ 965d5a114a6SFelix Kuehling static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 966d5a114a6SFelix Kuehling { 967d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 968d5a114a6SFelix Kuehling const union amdgpu_firmware_header *hdr; 969d5a114a6SFelix Kuehling 970d5a114a6SFelix Kuehling switch (type) { 971d5a114a6SFelix Kuehling case KGD_ENGINE_PFP: 972d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.pfp_fw->data; 973d5a114a6SFelix Kuehling break; 974d5a114a6SFelix Kuehling 975d5a114a6SFelix Kuehling case KGD_ENGINE_ME: 976d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.me_fw->data; 977d5a114a6SFelix Kuehling break; 978d5a114a6SFelix Kuehling 979d5a114a6SFelix Kuehling case KGD_ENGINE_CE: 980d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.ce_fw->data; 981d5a114a6SFelix Kuehling break; 982d5a114a6SFelix Kuehling 983d5a114a6SFelix Kuehling case KGD_ENGINE_MEC1: 984d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec_fw->data; 985d5a114a6SFelix Kuehling break; 986d5a114a6SFelix Kuehling 987d5a114a6SFelix Kuehling case KGD_ENGINE_MEC2: 988d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.mec2_fw->data; 989d5a114a6SFelix Kuehling break; 990d5a114a6SFelix Kuehling 991d5a114a6SFelix Kuehling case KGD_ENGINE_RLC: 992d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->gfx.rlc_fw->data; 993d5a114a6SFelix Kuehling break; 994d5a114a6SFelix Kuehling 995d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA1: 996d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[0].fw->data; 997d5a114a6SFelix Kuehling break; 998d5a114a6SFelix Kuehling 999d5a114a6SFelix Kuehling case KGD_ENGINE_SDMA2: 1000d5a114a6SFelix Kuehling hdr = (const union amdgpu_firmware_header *)adev->sdma.instance[1].fw->data; 1001d5a114a6SFelix Kuehling break; 1002d5a114a6SFelix Kuehling 1003d5a114a6SFelix Kuehling default: 1004d5a114a6SFelix Kuehling return 0; 1005d5a114a6SFelix Kuehling } 1006d5a114a6SFelix Kuehling 1007d5a114a6SFelix Kuehling if (hdr == NULL) 1008d5a114a6SFelix Kuehling return 0; 1009d5a114a6SFelix Kuehling 1010d5a114a6SFelix Kuehling /* Only 12 bit in use*/ 1011d5a114a6SFelix Kuehling return hdr->common.ucode_version; 1012d5a114a6SFelix Kuehling } 1013d5a114a6SFelix Kuehling 1014d5a114a6SFelix Kuehling static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 1015d5a114a6SFelix Kuehling uint32_t page_table_base) 1016d5a114a6SFelix Kuehling { 1017d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 1018d5a114a6SFelix Kuehling uint64_t base = (uint64_t)page_table_base << PAGE_SHIFT | 1019d5a114a6SFelix Kuehling AMDGPU_PTE_VALID; 1020d5a114a6SFelix Kuehling 1021d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 1022d5a114a6SFelix Kuehling pr_err("trying to set page table base for wrong VMID %u\n", 1023d5a114a6SFelix Kuehling vmid); 1024d5a114a6SFelix Kuehling return; 1025d5a114a6SFelix Kuehling } 1026d5a114a6SFelix Kuehling 1027d5a114a6SFelix Kuehling /* TODO: take advantage of per-process address space size. For 1028d5a114a6SFelix Kuehling * now, all processes share the same address space size, like 1029d5a114a6SFelix Kuehling * on GFX8 and older. 1030d5a114a6SFelix Kuehling */ 1031d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1032d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1033d5a114a6SFelix Kuehling 1034d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1035d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1036d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1037d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1038d5a114a6SFelix Kuehling 1039d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1040d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMMHUB_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1041d5a114a6SFelix Kuehling 1042d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 1043d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 1044d5a114a6SFelix Kuehling 1045d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 1046d5a114a6SFelix Kuehling lower_32_bits(adev->vm_manager.max_pfn - 1)); 1047d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 1048d5a114a6SFelix Kuehling upper_32_bits(adev->vm_manager.max_pfn - 1)); 1049d5a114a6SFelix Kuehling 1050d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 1051d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 1052d5a114a6SFelix Kuehling } 1053