1d5a114a6SFelix Kuehling /* 2d5a114a6SFelix Kuehling * Copyright 2014-2018 Advanced Micro Devices, Inc. 3d5a114a6SFelix Kuehling * 4d5a114a6SFelix Kuehling * Permission is hereby granted, free of charge, to any person obtaining a 5d5a114a6SFelix Kuehling * copy of this software and associated documentation files (the "Software"), 6d5a114a6SFelix Kuehling * to deal in the Software without restriction, including without limitation 7d5a114a6SFelix Kuehling * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d5a114a6SFelix Kuehling * and/or sell copies of the Software, and to permit persons to whom the 9d5a114a6SFelix Kuehling * Software is furnished to do so, subject to the following conditions: 10d5a114a6SFelix Kuehling * 11d5a114a6SFelix Kuehling * The above copyright notice and this permission notice shall be included in 12d5a114a6SFelix Kuehling * all copies or substantial portions of the Software. 13d5a114a6SFelix Kuehling * 14d5a114a6SFelix Kuehling * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d5a114a6SFelix Kuehling * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d5a114a6SFelix Kuehling * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d5a114a6SFelix Kuehling * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d5a114a6SFelix Kuehling * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d5a114a6SFelix Kuehling * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d5a114a6SFelix Kuehling * OTHER DEALINGS IN THE SOFTWARE. 21d5a114a6SFelix Kuehling */ 225634e38cSKuehling, Felix #include <linux/mmu_context.h> 23fdf2f6c5SSam Ravnborg 24d5a114a6SFelix Kuehling #include "amdgpu.h" 25d5a114a6SFelix Kuehling #include "amdgpu_amdkfd.h" 26d5a114a6SFelix Kuehling #include "gc/gc_9_0_offset.h" 27d5a114a6SFelix Kuehling #include "gc/gc_9_0_sh_mask.h" 28d5a114a6SFelix Kuehling #include "vega10_enum.h" 29d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_offset.h" 30d5a114a6SFelix Kuehling #include "sdma0/sdma0_4_0_sh_mask.h" 31d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_offset.h" 32d5a114a6SFelix Kuehling #include "sdma1/sdma1_4_0_sh_mask.h" 33d5a114a6SFelix Kuehling #include "athub/athub_1_0_offset.h" 34d5a114a6SFelix Kuehling #include "athub/athub_1_0_sh_mask.h" 35d5a114a6SFelix Kuehling #include "oss/osssys_4_0_offset.h" 36d5a114a6SFelix Kuehling #include "oss/osssys_4_0_sh_mask.h" 37d5a114a6SFelix Kuehling #include "soc15_common.h" 38d5a114a6SFelix Kuehling #include "v9_structs.h" 39d5a114a6SFelix Kuehling #include "soc15.h" 40d5a114a6SFelix Kuehling #include "soc15d.h" 41e4312d45SAlex Deucher #include "mmhub_v1_0.h" 42e4312d45SAlex Deucher #include "gfxhub_v1_0.h" 43d5a114a6SFelix Kuehling 44d5a114a6SFelix Kuehling 45d5a114a6SFelix Kuehling enum hqd_dequeue_request_type { 46d5a114a6SFelix Kuehling NO_ACTION = 0, 47d5a114a6SFelix Kuehling DRAIN_PIPE, 48d5a114a6SFelix Kuehling RESET_WAVES 49d5a114a6SFelix Kuehling }; 50d5a114a6SFelix Kuehling 51d5a114a6SFelix Kuehling 52d5a114a6SFelix Kuehling /* Because of REG_GET_FIELD() being used, we put this function in the 53d5a114a6SFelix Kuehling * asic specific file. 54d5a114a6SFelix Kuehling */ 553e205a08SOak Zeng int kgd_gfx_v9_get_tile_config(struct kgd_dev *kgd, 56d5a114a6SFelix Kuehling struct tile_config *config) 57d5a114a6SFelix Kuehling { 58d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 59d5a114a6SFelix Kuehling 60d5a114a6SFelix Kuehling config->gb_addr_config = adev->gfx.config.gb_addr_config; 61d5a114a6SFelix Kuehling 62d5a114a6SFelix Kuehling config->tile_config_ptr = adev->gfx.config.tile_mode_array; 63d5a114a6SFelix Kuehling config->num_tile_configs = 64d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.tile_mode_array); 65d5a114a6SFelix Kuehling config->macro_tile_config_ptr = 66d5a114a6SFelix Kuehling adev->gfx.config.macrotile_mode_array; 67d5a114a6SFelix Kuehling config->num_macro_tile_configs = 68d5a114a6SFelix Kuehling ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 69d5a114a6SFelix Kuehling 70d5a114a6SFelix Kuehling return 0; 71d5a114a6SFelix Kuehling } 72d5a114a6SFelix Kuehling 73d5a114a6SFelix Kuehling static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 74d5a114a6SFelix Kuehling { 75d5a114a6SFelix Kuehling return (struct amdgpu_device *)kgd; 76d5a114a6SFelix Kuehling } 77d5a114a6SFelix Kuehling 78d5a114a6SFelix Kuehling static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 79d5a114a6SFelix Kuehling uint32_t queue, uint32_t vmid) 80d5a114a6SFelix Kuehling { 81d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 82d5a114a6SFelix Kuehling 83d5a114a6SFelix Kuehling mutex_lock(&adev->srbm_mutex); 84d5a114a6SFelix Kuehling soc15_grbm_select(adev, mec, pipe, queue, vmid); 85d5a114a6SFelix Kuehling } 86d5a114a6SFelix Kuehling 87d5a114a6SFelix Kuehling static void unlock_srbm(struct kgd_dev *kgd) 88d5a114a6SFelix Kuehling { 89d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 90d5a114a6SFelix Kuehling 91d5a114a6SFelix Kuehling soc15_grbm_select(adev, 0, 0, 0, 0); 92d5a114a6SFelix Kuehling mutex_unlock(&adev->srbm_mutex); 93d5a114a6SFelix Kuehling } 94d5a114a6SFelix Kuehling 95d5a114a6SFelix Kuehling static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 96d5a114a6SFelix Kuehling uint32_t queue_id) 97d5a114a6SFelix Kuehling { 98d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 99d5a114a6SFelix Kuehling 100d5a114a6SFelix Kuehling uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 101d5a114a6SFelix Kuehling uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 102d5a114a6SFelix Kuehling 103d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, queue_id, 0); 104d5a114a6SFelix Kuehling } 105d5a114a6SFelix Kuehling 106d5a114a6SFelix Kuehling static uint32_t get_queue_mask(struct amdgpu_device *adev, 107d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 108d5a114a6SFelix Kuehling { 109d5a114a6SFelix Kuehling unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 110d5a114a6SFelix Kuehling queue_id) & 31; 111d5a114a6SFelix Kuehling 112d5a114a6SFelix Kuehling return ((uint32_t)1) << bit; 113d5a114a6SFelix Kuehling } 114d5a114a6SFelix Kuehling 115d5a114a6SFelix Kuehling static void release_queue(struct kgd_dev *kgd) 116d5a114a6SFelix Kuehling { 117d5a114a6SFelix Kuehling unlock_srbm(kgd); 118d5a114a6SFelix Kuehling } 119d5a114a6SFelix Kuehling 1203e205a08SOak Zeng void kgd_gfx_v9_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 121d5a114a6SFelix Kuehling uint32_t sh_mem_config, 122d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_base, 123d5a114a6SFelix Kuehling uint32_t sh_mem_ape1_limit, 124d5a114a6SFelix Kuehling uint32_t sh_mem_bases) 125d5a114a6SFelix Kuehling { 126d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 127d5a114a6SFelix Kuehling 128d5a114a6SFelix Kuehling lock_srbm(kgd, 0, 0, 0, vmid); 129d5a114a6SFelix Kuehling 1301bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 1311bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 132d5a114a6SFelix Kuehling /* APE1 no longer exists on GFX9 */ 133d5a114a6SFelix Kuehling 134d5a114a6SFelix Kuehling unlock_srbm(kgd); 135d5a114a6SFelix Kuehling } 136d5a114a6SFelix Kuehling 1373e205a08SOak Zeng int kgd_gfx_v9_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 138d5a114a6SFelix Kuehling unsigned int vmid) 139d5a114a6SFelix Kuehling { 140d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 141d5a114a6SFelix Kuehling 142d5a114a6SFelix Kuehling /* 143d5a114a6SFelix Kuehling * We have to assume that there is no outstanding mapping. 144d5a114a6SFelix Kuehling * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 145d5a114a6SFelix Kuehling * a mapping is in progress or because a mapping finished 146d5a114a6SFelix Kuehling * and the SW cleared it. 147d5a114a6SFelix Kuehling * So the protocol is to always wait & clear. 148d5a114a6SFelix Kuehling */ 149d5a114a6SFelix Kuehling uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 150d5a114a6SFelix Kuehling ATC_VMID0_PASID_MAPPING__VALID_MASK; 151d5a114a6SFelix Kuehling 152d5a114a6SFelix Kuehling /* 153d5a114a6SFelix Kuehling * need to do this twice, once for gfx and once for mmhub 154d5a114a6SFelix Kuehling * for ATC add 16 to VMID for mmhub, for IH different registers. 155d5a114a6SFelix Kuehling * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 156d5a114a6SFelix Kuehling */ 157d5a114a6SFelix Kuehling 158d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 159d5a114a6SFelix Kuehling pasid_mapping); 160d5a114a6SFelix Kuehling 161d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 162d5a114a6SFelix Kuehling ATHUB, 0, 163d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 164d5a114a6SFelix Kuehling (1U << vmid))) 165d5a114a6SFelix Kuehling cpu_relax(); 166d5a114a6SFelix Kuehling 167d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 168d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 169d5a114a6SFelix Kuehling 1U << vmid); 170d5a114a6SFelix Kuehling 171d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 172d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 173d5a114a6SFelix Kuehling pasid_mapping); 174d5a114a6SFelix Kuehling 175d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid, 176d5a114a6SFelix Kuehling pasid_mapping); 177d5a114a6SFelix Kuehling 178d5a114a6SFelix Kuehling while (!(RREG32(SOC15_REG_OFFSET( 179d5a114a6SFelix Kuehling ATHUB, 0, 180d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 181d5a114a6SFelix Kuehling (1U << (vmid + 16)))) 182d5a114a6SFelix Kuehling cpu_relax(); 183d5a114a6SFelix Kuehling 184d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(ATHUB, 0, 185d5a114a6SFelix Kuehling mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 186d5a114a6SFelix Kuehling 1U << (vmid + 16)); 187d5a114a6SFelix Kuehling 188d5a114a6SFelix Kuehling /* Mapping vmid to pasid also for IH block */ 189d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid, 190d5a114a6SFelix Kuehling pasid_mapping); 191d5a114a6SFelix Kuehling return 0; 192d5a114a6SFelix Kuehling } 193d5a114a6SFelix Kuehling 194d5a114a6SFelix Kuehling /* TODO - RING0 form of field is obsolete, seems to date back to SI 195d5a114a6SFelix Kuehling * but still works 196d5a114a6SFelix Kuehling */ 197d5a114a6SFelix Kuehling 1983e205a08SOak Zeng int kgd_gfx_v9_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 199d5a114a6SFelix Kuehling { 200d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 201d5a114a6SFelix Kuehling uint32_t mec; 202d5a114a6SFelix Kuehling uint32_t pipe; 203d5a114a6SFelix Kuehling 204d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 205d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 206d5a114a6SFelix Kuehling 207d5a114a6SFelix Kuehling lock_srbm(kgd, mec, pipe, 0, 0); 208d5a114a6SFelix Kuehling 209d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 210d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 211d5a114a6SFelix Kuehling CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 212d5a114a6SFelix Kuehling 213d5a114a6SFelix Kuehling unlock_srbm(kgd); 214d5a114a6SFelix Kuehling 215d5a114a6SFelix Kuehling return 0; 216d5a114a6SFelix Kuehling } 217d5a114a6SFelix Kuehling 218b55a8b8bSYong Zhao static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 219d5a114a6SFelix Kuehling unsigned int engine_id, 220d5a114a6SFelix Kuehling unsigned int queue_id) 221d5a114a6SFelix Kuehling { 222b55a8b8bSYong Zhao uint32_t sdma_engine_reg_base[2] = { 223d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA0, 0, 224d5a114a6SFelix Kuehling mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 225d5a114a6SFelix Kuehling SOC15_REG_OFFSET(SDMA1, 0, 226d5a114a6SFelix Kuehling mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL 227d5a114a6SFelix Kuehling }; 228b55a8b8bSYong Zhao uint32_t retval = sdma_engine_reg_base[engine_id] 229b55a8b8bSYong Zhao + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 230d5a114a6SFelix Kuehling 231b55a8b8bSYong Zhao pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 232b55a8b8bSYong Zhao queue_id, retval); 233d5a114a6SFelix Kuehling 234d5a114a6SFelix Kuehling return retval; 235d5a114a6SFelix Kuehling } 236d5a114a6SFelix Kuehling 237d5a114a6SFelix Kuehling static inline struct v9_mqd *get_mqd(void *mqd) 238d5a114a6SFelix Kuehling { 239d5a114a6SFelix Kuehling return (struct v9_mqd *)mqd; 240d5a114a6SFelix Kuehling } 241d5a114a6SFelix Kuehling 242d5a114a6SFelix Kuehling static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 243d5a114a6SFelix Kuehling { 244d5a114a6SFelix Kuehling return (struct v9_sdma_mqd *)mqd; 245d5a114a6SFelix Kuehling } 246d5a114a6SFelix Kuehling 2473e205a08SOak Zeng int kgd_gfx_v9_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 248d5a114a6SFelix Kuehling uint32_t queue_id, uint32_t __user *wptr, 249d5a114a6SFelix Kuehling uint32_t wptr_shift, uint32_t wptr_mask, 250d5a114a6SFelix Kuehling struct mm_struct *mm) 251d5a114a6SFelix Kuehling { 252d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 253d5a114a6SFelix Kuehling struct v9_mqd *m; 254d5a114a6SFelix Kuehling uint32_t *mqd_hqd; 255d5a114a6SFelix Kuehling uint32_t reg, hqd_base, data; 256d5a114a6SFelix Kuehling 257d5a114a6SFelix Kuehling m = get_mqd(mqd); 258d5a114a6SFelix Kuehling 259d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 260d5a114a6SFelix Kuehling 261d5a114a6SFelix Kuehling /* HIQ is set during driver init period with vmid set to 0*/ 262d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) { 263d5a114a6SFelix Kuehling uint32_t value, mec, pipe; 264d5a114a6SFelix Kuehling 265d5a114a6SFelix Kuehling mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 266d5a114a6SFelix Kuehling pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 267d5a114a6SFelix Kuehling 268d5a114a6SFelix Kuehling pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 269d5a114a6SFelix Kuehling mec, pipe, queue_id); 270d5a114a6SFelix Kuehling value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 271d5a114a6SFelix Kuehling value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 272d5a114a6SFelix Kuehling ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 2731bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 274d5a114a6SFelix Kuehling } 275d5a114a6SFelix Kuehling 276d5a114a6SFelix Kuehling /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 277d5a114a6SFelix Kuehling mqd_hqd = &m->cp_mqd_base_addr_lo; 278d5a114a6SFelix Kuehling hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 279d5a114a6SFelix Kuehling 280d5a114a6SFelix Kuehling for (reg = hqd_base; 281d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 2821bff7f6cSTrigger Huang WREG32_RLC(reg, mqd_hqd[reg - hqd_base]); 283d5a114a6SFelix Kuehling 284d5a114a6SFelix Kuehling 285d5a114a6SFelix Kuehling /* Activate doorbell logic before triggering WPTR poll. */ 286d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 287d5a114a6SFelix Kuehling CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 2881bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 289d5a114a6SFelix Kuehling 290d5a114a6SFelix Kuehling if (wptr) { 291d5a114a6SFelix Kuehling /* Don't read wptr with get_user because the user 292d5a114a6SFelix Kuehling * context may not be accessible (if this function 293d5a114a6SFelix Kuehling * runs in a work queue). Instead trigger a one-shot 294d5a114a6SFelix Kuehling * polling read from memory in the CP. This assumes 295d5a114a6SFelix Kuehling * that wptr is GPU-accessible in the queue's VMID via 296d5a114a6SFelix Kuehling * ATC or SVM. WPTR==RPTR before starting the poll so 297d5a114a6SFelix Kuehling * the CP starts fetching new commands from the right 298d5a114a6SFelix Kuehling * place. 299d5a114a6SFelix Kuehling * 300d5a114a6SFelix Kuehling * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 301d5a114a6SFelix Kuehling * tricky. Assume that the queue didn't overflow. The 302d5a114a6SFelix Kuehling * number of valid bits in the 32-bit RPTR depends on 303d5a114a6SFelix Kuehling * the queue size. The remaining bits are taken from 304d5a114a6SFelix Kuehling * the saved 64-bit WPTR. If the WPTR wrapped, add the 305d5a114a6SFelix Kuehling * queue size. 306d5a114a6SFelix Kuehling */ 307d5a114a6SFelix Kuehling uint32_t queue_size = 308d5a114a6SFelix Kuehling 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 309d5a114a6SFelix Kuehling CP_HQD_PQ_CONTROL, QUEUE_SIZE); 310d5a114a6SFelix Kuehling uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 311d5a114a6SFelix Kuehling 312d5a114a6SFelix Kuehling if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 313d5a114a6SFelix Kuehling guessed_wptr += queue_size; 314d5a114a6SFelix Kuehling guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 315d5a114a6SFelix Kuehling guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 316d5a114a6SFelix Kuehling 3171bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 318d5a114a6SFelix Kuehling lower_32_bits(guessed_wptr)); 3191bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 320d5a114a6SFelix Kuehling upper_32_bits(guessed_wptr)); 3211bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 322ebe1d22bSArnd Bergmann lower_32_bits((uintptr_t)wptr)); 3231bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 324ebe1d22bSArnd Bergmann upper_32_bits((uintptr_t)wptr)); 325d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 326d5a114a6SFelix Kuehling get_queue_mask(adev, pipe_id, queue_id)); 327d5a114a6SFelix Kuehling } 328d5a114a6SFelix Kuehling 329d5a114a6SFelix Kuehling /* Start the EOP fetcher */ 3301bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 331d5a114a6SFelix Kuehling REG_SET_FIELD(m->cp_hqd_eop_rptr, 332d5a114a6SFelix Kuehling CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 333d5a114a6SFelix Kuehling 334d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 3351bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 336d5a114a6SFelix Kuehling 337d5a114a6SFelix Kuehling release_queue(kgd); 338d5a114a6SFelix Kuehling 339d5a114a6SFelix Kuehling return 0; 340d5a114a6SFelix Kuehling } 341d5a114a6SFelix Kuehling 3423e205a08SOak Zeng int kgd_gfx_v9_hqd_dump(struct kgd_dev *kgd, 343d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id, 344d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 345d5a114a6SFelix Kuehling { 346d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 347d5a114a6SFelix Kuehling uint32_t i = 0, reg; 348d5a114a6SFelix Kuehling #define HQD_N_REGS 56 349d5a114a6SFelix Kuehling #define DUMP_REG(addr) do { \ 350d5a114a6SFelix Kuehling if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 351d5a114a6SFelix Kuehling break; \ 352d5a114a6SFelix Kuehling (*dump)[i][0] = (addr) << 2; \ 353d5a114a6SFelix Kuehling (*dump)[i++][1] = RREG32(addr); \ 354d5a114a6SFelix Kuehling } while (0) 355d5a114a6SFelix Kuehling 3566da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 357d5a114a6SFelix Kuehling if (*dump == NULL) 358d5a114a6SFelix Kuehling return -ENOMEM; 359d5a114a6SFelix Kuehling 360d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 361d5a114a6SFelix Kuehling 362d5a114a6SFelix Kuehling for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 363d5a114a6SFelix Kuehling reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 364d5a114a6SFelix Kuehling DUMP_REG(reg); 365d5a114a6SFelix Kuehling 366d5a114a6SFelix Kuehling release_queue(kgd); 367d5a114a6SFelix Kuehling 368d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 369d5a114a6SFelix Kuehling *n_regs = i; 370d5a114a6SFelix Kuehling 371d5a114a6SFelix Kuehling return 0; 372d5a114a6SFelix Kuehling } 373d5a114a6SFelix Kuehling 374d5a114a6SFelix Kuehling static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 375d5a114a6SFelix Kuehling uint32_t __user *wptr, struct mm_struct *mm) 376d5a114a6SFelix Kuehling { 377d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 378d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 379b55a8b8bSYong Zhao uint32_t sdma_rlc_reg_offset; 380d5a114a6SFelix Kuehling unsigned long end_jiffies; 381d5a114a6SFelix Kuehling uint32_t data; 382d5a114a6SFelix Kuehling uint64_t data64; 383d5a114a6SFelix Kuehling uint64_t __user *wptr64 = (uint64_t __user *)wptr; 384d5a114a6SFelix Kuehling 385d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 386b55a8b8bSYong Zhao sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 387d5a114a6SFelix Kuehling m->sdma_queue_id); 388d5a114a6SFelix Kuehling 389b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 390d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 391d5a114a6SFelix Kuehling 392d5a114a6SFelix Kuehling end_jiffies = msecs_to_jiffies(2000) + jiffies; 393d5a114a6SFelix Kuehling while (true) { 394b55a8b8bSYong Zhao data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 395d5a114a6SFelix Kuehling if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 396d5a114a6SFelix Kuehling break; 397812330ebSYong Zhao if (time_after(jiffies, end_jiffies)) { 398812330ebSYong Zhao pr_err("SDMA RLC not idle in %s\n", __func__); 399d5a114a6SFelix Kuehling return -ETIME; 400812330ebSYong Zhao } 401d5a114a6SFelix Kuehling usleep_range(500, 1000); 402d5a114a6SFelix Kuehling } 403d5a114a6SFelix Kuehling 404b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 405d5a114a6SFelix Kuehling m->sdmax_rlcx_doorbell_offset); 406d5a114a6SFelix Kuehling 407d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 408d5a114a6SFelix Kuehling ENABLE, 1); 409b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 410b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 411b55a8b8bSYong Zhao m->sdmax_rlcx_rb_rptr); 412b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 413d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 414d5a114a6SFelix Kuehling 415b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 416d5a114a6SFelix Kuehling if (read_user_wptr(mm, wptr64, data64)) { 417b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 418d5a114a6SFelix Kuehling lower_32_bits(data64)); 419b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 420d5a114a6SFelix Kuehling upper_32_bits(data64)); 421d5a114a6SFelix Kuehling } else { 422b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 423d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr); 424b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 425d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi); 426d5a114a6SFelix Kuehling } 427b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 428d5a114a6SFelix Kuehling 429b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 430b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 431d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_base_hi); 432b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 433d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_lo); 434b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 435d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_addr_hi); 436d5a114a6SFelix Kuehling 437d5a114a6SFelix Kuehling data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 438d5a114a6SFelix Kuehling RB_ENABLE, 1); 439b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 440d5a114a6SFelix Kuehling 441d5a114a6SFelix Kuehling return 0; 442d5a114a6SFelix Kuehling } 443d5a114a6SFelix Kuehling 444d5a114a6SFelix Kuehling static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 445d5a114a6SFelix Kuehling uint32_t engine_id, uint32_t queue_id, 446d5a114a6SFelix Kuehling uint32_t (**dump)[2], uint32_t *n_regs) 447d5a114a6SFelix Kuehling { 448d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 449b55a8b8bSYong Zhao uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 450b55a8b8bSYong Zhao engine_id, queue_id); 451d5a114a6SFelix Kuehling uint32_t i = 0, reg; 452d5a114a6SFelix Kuehling #undef HQD_N_REGS 453d5a114a6SFelix Kuehling #define HQD_N_REGS (19+6+7+10) 454d5a114a6SFelix Kuehling 4556da2ec56SKees Cook *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 456d5a114a6SFelix Kuehling if (*dump == NULL) 457d5a114a6SFelix Kuehling return -ENOMEM; 458d5a114a6SFelix Kuehling 459d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 460b55a8b8bSYong Zhao DUMP_REG(sdma_rlc_reg_offset + reg); 461d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 462b55a8b8bSYong Zhao DUMP_REG(sdma_rlc_reg_offset + reg); 463d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 464d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 465b55a8b8bSYong Zhao DUMP_REG(sdma_rlc_reg_offset + reg); 466d5a114a6SFelix Kuehling for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 467d5a114a6SFelix Kuehling reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 468b55a8b8bSYong Zhao DUMP_REG(sdma_rlc_reg_offset + reg); 469d5a114a6SFelix Kuehling 470d5a114a6SFelix Kuehling WARN_ON_ONCE(i != HQD_N_REGS); 471d5a114a6SFelix Kuehling *n_regs = i; 472d5a114a6SFelix Kuehling 473d5a114a6SFelix Kuehling return 0; 474d5a114a6SFelix Kuehling } 475d5a114a6SFelix Kuehling 4763e205a08SOak Zeng bool kgd_gfx_v9_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 477d5a114a6SFelix Kuehling uint32_t pipe_id, uint32_t queue_id) 478d5a114a6SFelix Kuehling { 479d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 480d5a114a6SFelix Kuehling uint32_t act; 481d5a114a6SFelix Kuehling bool retval = false; 482d5a114a6SFelix Kuehling uint32_t low, high; 483d5a114a6SFelix Kuehling 484d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 485d5a114a6SFelix Kuehling act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 486d5a114a6SFelix Kuehling if (act) { 487d5a114a6SFelix Kuehling low = lower_32_bits(queue_address >> 8); 488d5a114a6SFelix Kuehling high = upper_32_bits(queue_address >> 8); 489d5a114a6SFelix Kuehling 490d5a114a6SFelix Kuehling if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 491d5a114a6SFelix Kuehling high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 492d5a114a6SFelix Kuehling retval = true; 493d5a114a6SFelix Kuehling } 494d5a114a6SFelix Kuehling release_queue(kgd); 495d5a114a6SFelix Kuehling return retval; 496d5a114a6SFelix Kuehling } 497d5a114a6SFelix Kuehling 498d5a114a6SFelix Kuehling static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 499d5a114a6SFelix Kuehling { 500d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 501d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 502b55a8b8bSYong Zhao uint32_t sdma_rlc_reg_offset; 503d5a114a6SFelix Kuehling uint32_t sdma_rlc_rb_cntl; 504d5a114a6SFelix Kuehling 505d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 506b55a8b8bSYong Zhao sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 507d5a114a6SFelix Kuehling m->sdma_queue_id); 508d5a114a6SFelix Kuehling 509b55a8b8bSYong Zhao sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 510d5a114a6SFelix Kuehling 511d5a114a6SFelix Kuehling if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 512d5a114a6SFelix Kuehling return true; 513d5a114a6SFelix Kuehling 514d5a114a6SFelix Kuehling return false; 515d5a114a6SFelix Kuehling } 516d5a114a6SFelix Kuehling 5173e205a08SOak Zeng int kgd_gfx_v9_hqd_destroy(struct kgd_dev *kgd, void *mqd, 518d5a114a6SFelix Kuehling enum kfd_preempt_type reset_type, 519d5a114a6SFelix Kuehling unsigned int utimeout, uint32_t pipe_id, 520d5a114a6SFelix Kuehling uint32_t queue_id) 521d5a114a6SFelix Kuehling { 522d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 523d5a114a6SFelix Kuehling enum hqd_dequeue_request_type type; 524d5a114a6SFelix Kuehling unsigned long end_jiffies; 525d5a114a6SFelix Kuehling uint32_t temp; 526d5a114a6SFelix Kuehling struct v9_mqd *m = get_mqd(mqd); 527d5a114a6SFelix Kuehling 5281b0bfcffSShaoyun Liu if (adev->in_gpu_reset) 5291b0bfcffSShaoyun Liu return -EIO; 5301b0bfcffSShaoyun Liu 531d5a114a6SFelix Kuehling acquire_queue(kgd, pipe_id, queue_id); 532d5a114a6SFelix Kuehling 533d5a114a6SFelix Kuehling if (m->cp_hqd_vmid == 0) 5341bff7f6cSTrigger Huang WREG32_FIELD15_RLC(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 535d5a114a6SFelix Kuehling 536d5a114a6SFelix Kuehling switch (reset_type) { 537d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 538d5a114a6SFelix Kuehling type = DRAIN_PIPE; 539d5a114a6SFelix Kuehling break; 540d5a114a6SFelix Kuehling case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 541d5a114a6SFelix Kuehling type = RESET_WAVES; 542d5a114a6SFelix Kuehling break; 543d5a114a6SFelix Kuehling default: 544d5a114a6SFelix Kuehling type = DRAIN_PIPE; 545d5a114a6SFelix Kuehling break; 546d5a114a6SFelix Kuehling } 547d5a114a6SFelix Kuehling 5481bff7f6cSTrigger Huang WREG32_RLC(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 549d5a114a6SFelix Kuehling 550d5a114a6SFelix Kuehling end_jiffies = (utimeout * HZ / 1000) + jiffies; 551d5a114a6SFelix Kuehling while (true) { 552d5a114a6SFelix Kuehling temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 553d5a114a6SFelix Kuehling if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 554d5a114a6SFelix Kuehling break; 555d5a114a6SFelix Kuehling if (time_after(jiffies, end_jiffies)) { 556d5a114a6SFelix Kuehling pr_err("cp queue preemption time out.\n"); 557d5a114a6SFelix Kuehling release_queue(kgd); 558d5a114a6SFelix Kuehling return -ETIME; 559d5a114a6SFelix Kuehling } 560d5a114a6SFelix Kuehling usleep_range(500, 1000); 561d5a114a6SFelix Kuehling } 562d5a114a6SFelix Kuehling 563d5a114a6SFelix Kuehling release_queue(kgd); 564d5a114a6SFelix Kuehling return 0; 565d5a114a6SFelix Kuehling } 566d5a114a6SFelix Kuehling 567d5a114a6SFelix Kuehling static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 568d5a114a6SFelix Kuehling unsigned int utimeout) 569d5a114a6SFelix Kuehling { 570d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 571d5a114a6SFelix Kuehling struct v9_sdma_mqd *m; 572b55a8b8bSYong Zhao uint32_t sdma_rlc_reg_offset; 573d5a114a6SFelix Kuehling uint32_t temp; 574d5a114a6SFelix Kuehling unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 575d5a114a6SFelix Kuehling 576d5a114a6SFelix Kuehling m = get_sdma_mqd(mqd); 577b55a8b8bSYong Zhao sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 578d5a114a6SFelix Kuehling m->sdma_queue_id); 579d5a114a6SFelix Kuehling 580b55a8b8bSYong Zhao temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 581d5a114a6SFelix Kuehling temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 582b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 583d5a114a6SFelix Kuehling 584d5a114a6SFelix Kuehling while (true) { 585b55a8b8bSYong Zhao temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 586d5a114a6SFelix Kuehling if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 587d5a114a6SFelix Kuehling break; 588812330ebSYong Zhao if (time_after(jiffies, end_jiffies)) { 589812330ebSYong Zhao pr_err("SDMA RLC not idle in %s\n", __func__); 590d5a114a6SFelix Kuehling return -ETIME; 591812330ebSYong Zhao } 592d5a114a6SFelix Kuehling usleep_range(500, 1000); 593d5a114a6SFelix Kuehling } 594d5a114a6SFelix Kuehling 595b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 596b55a8b8bSYong Zhao WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 597b55a8b8bSYong Zhao RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 598d5a114a6SFelix Kuehling SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 599d5a114a6SFelix Kuehling 600b55a8b8bSYong Zhao m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 601d5a114a6SFelix Kuehling m->sdmax_rlcx_rb_rptr_hi = 602b55a8b8bSYong Zhao RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 603d5a114a6SFelix Kuehling 604d5a114a6SFelix Kuehling return 0; 605d5a114a6SFelix Kuehling } 606d5a114a6SFelix Kuehling 60756fc40abSYong Zhao bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 60856fc40abSYong Zhao uint8_t vmid, uint16_t *p_pasid) 609d5a114a6SFelix Kuehling { 61056fc40abSYong Zhao uint32_t value; 611d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 612d5a114a6SFelix Kuehling 61356fc40abSYong Zhao value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 614d5a114a6SFelix Kuehling + vmid); 61556fc40abSYong Zhao *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 616d5a114a6SFelix Kuehling 61756fc40abSYong Zhao return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 618d5a114a6SFelix Kuehling } 619d5a114a6SFelix Kuehling 620e14ba95bSshaoyunl static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid, 621e14ba95bSshaoyunl uint32_t flush_type) 622d5a114a6SFelix Kuehling { 623d5a114a6SFelix Kuehling signed long r; 624d5a114a6SFelix Kuehling uint32_t seq; 625d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 626d5a114a6SFelix Kuehling 627d5a114a6SFelix Kuehling spin_lock(&adev->gfx.kiq.ring_lock); 628d5a114a6SFelix Kuehling amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 629d5a114a6SFelix Kuehling amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 630d5a114a6SFelix Kuehling amdgpu_ring_write(ring, 631d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 632d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_ALL_HUB(1) | 633d5a114a6SFelix Kuehling PACKET3_INVALIDATE_TLBS_PASID(pasid) | 634e14ba95bSshaoyunl PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); 635d5a114a6SFelix Kuehling amdgpu_fence_emit_polling(ring, &seq); 636d5a114a6SFelix Kuehling amdgpu_ring_commit(ring); 637d5a114a6SFelix Kuehling spin_unlock(&adev->gfx.kiq.ring_lock); 638d5a114a6SFelix Kuehling 639d5a114a6SFelix Kuehling r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 640d5a114a6SFelix Kuehling if (r < 1) { 641d5a114a6SFelix Kuehling DRM_ERROR("wait for kiq fence error: %ld.\n", r); 642d5a114a6SFelix Kuehling return -ETIME; 643d5a114a6SFelix Kuehling } 644d5a114a6SFelix Kuehling 645d5a114a6SFelix Kuehling return 0; 646d5a114a6SFelix Kuehling } 647d5a114a6SFelix Kuehling 6483e205a08SOak Zeng int kgd_gfx_v9_invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 649d5a114a6SFelix Kuehling { 650d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 6513ff98548SOak Zeng int vmid, i; 65256fc40abSYong Zhao uint16_t queried_pasid; 65356fc40abSYong Zhao bool ret; 654d5a114a6SFelix Kuehling struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 655e14ba95bSshaoyunl uint32_t flush_type = 0; 656d5a114a6SFelix Kuehling 657bff418a2SShaoyun Liu if (adev->in_gpu_reset) 658bff418a2SShaoyun Liu return -EIO; 659e14ba95bSshaoyunl if (adev->gmc.xgmi.num_physical_nodes && 660e14ba95bSshaoyunl adev->asic_type == CHIP_VEGA20) 661e14ba95bSshaoyunl flush_type = 2; 662bff418a2SShaoyun Liu 663c66ed765SAndrey Grodzovsky if (ring->sched.ready) 664e14ba95bSshaoyunl return invalidate_tlbs_with_kiq(adev, pasid, flush_type); 665d5a114a6SFelix Kuehling 666d5a114a6SFelix Kuehling for (vmid = 0; vmid < 16; vmid++) { 667d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 668d5a114a6SFelix Kuehling continue; 66956fc40abSYong Zhao 67056fc40abSYong Zhao ret = kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(kgd, vmid, 67156fc40abSYong Zhao &queried_pasid); 67256fc40abSYong Zhao if (ret && queried_pasid == pasid) { 6733ff98548SOak Zeng for (i = 0; i < adev->num_vmhubs; i++) 674e14ba95bSshaoyunl amdgpu_gmc_flush_gpu_tlb(adev, vmid, 6753ff98548SOak Zeng i, flush_type); 676d5a114a6SFelix Kuehling break; 677d5a114a6SFelix Kuehling } 678d5a114a6SFelix Kuehling } 679d5a114a6SFelix Kuehling 680d5a114a6SFelix Kuehling return 0; 681d5a114a6SFelix Kuehling } 682d5a114a6SFelix Kuehling 6833e205a08SOak Zeng int kgd_gfx_v9_invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 684d5a114a6SFelix Kuehling { 685d5a114a6SFelix Kuehling struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 6863ff98548SOak Zeng int i; 687d5a114a6SFelix Kuehling 688d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 689d5a114a6SFelix Kuehling pr_err("non kfd vmid %d\n", vmid); 690d5a114a6SFelix Kuehling return 0; 691d5a114a6SFelix Kuehling } 692d5a114a6SFelix Kuehling 693e14ba95bSshaoyunl /* Use legacy mode tlb invalidation. 694e14ba95bSshaoyunl * 695e14ba95bSshaoyunl * Currently on Raven the code below is broken for anything but 696e14ba95bSshaoyunl * legacy mode due to a MMHUB power gating problem. A workaround 697e14ba95bSshaoyunl * is for MMHUB to wait until the condition PER_VMID_INVALIDATE_REQ 698e14ba95bSshaoyunl * == PER_VMID_INVALIDATE_ACK instead of simply waiting for the ack 699e14ba95bSshaoyunl * bit. 700e14ba95bSshaoyunl * 701e14ba95bSshaoyunl * TODO 1: agree on the right set of invalidation registers for 702e14ba95bSshaoyunl * KFD use. Use the last one for now. Invalidate both GC and 703e14ba95bSshaoyunl * MMHUB. 704e14ba95bSshaoyunl * 705e14ba95bSshaoyunl * TODO 2: support range-based invalidation, requires kfg2kgd 706e14ba95bSshaoyunl * interface change 707e14ba95bSshaoyunl */ 7083ff98548SOak Zeng for (i = 0; i < adev->num_vmhubs; i++) 7093ff98548SOak Zeng amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 7103ff98548SOak Zeng 711d5a114a6SFelix Kuehling return 0; 712d5a114a6SFelix Kuehling } 713d5a114a6SFelix Kuehling 7143e205a08SOak Zeng int kgd_gfx_v9_address_watch_disable(struct kgd_dev *kgd) 715d5a114a6SFelix Kuehling { 716d5a114a6SFelix Kuehling return 0; 717d5a114a6SFelix Kuehling } 718d5a114a6SFelix Kuehling 7193e205a08SOak Zeng int kgd_gfx_v9_address_watch_execute(struct kgd_dev *kgd, 720d5a114a6SFelix Kuehling unsigned int watch_point_id, 721d5a114a6SFelix Kuehling uint32_t cntl_val, 722d5a114a6SFelix Kuehling uint32_t addr_hi, 723d5a114a6SFelix Kuehling uint32_t addr_lo) 724d5a114a6SFelix Kuehling { 725d5a114a6SFelix Kuehling return 0; 726d5a114a6SFelix Kuehling } 727d5a114a6SFelix Kuehling 7283e205a08SOak Zeng int kgd_gfx_v9_wave_control_execute(struct kgd_dev *kgd, 729d5a114a6SFelix Kuehling uint32_t gfx_index_val, 730d5a114a6SFelix Kuehling uint32_t sq_cmd) 731d5a114a6SFelix Kuehling { 732d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 733d5a114a6SFelix Kuehling uint32_t data = 0; 734d5a114a6SFelix Kuehling 735d5a114a6SFelix Kuehling mutex_lock(&adev->grbm_idx_mutex); 736d5a114a6SFelix Kuehling 7371bff7f6cSTrigger Huang WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); 738d5a114a6SFelix Kuehling WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 739d5a114a6SFelix Kuehling 740d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 741d5a114a6SFelix Kuehling INSTANCE_BROADCAST_WRITES, 1); 742d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 743d5a114a6SFelix Kuehling SH_BROADCAST_WRITES, 1); 744d5a114a6SFelix Kuehling data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 745d5a114a6SFelix Kuehling SE_BROADCAST_WRITES, 1); 746d5a114a6SFelix Kuehling 7471bff7f6cSTrigger Huang WREG32_SOC15_RLC_SHADOW(GC, 0, mmGRBM_GFX_INDEX, data); 748d5a114a6SFelix Kuehling mutex_unlock(&adev->grbm_idx_mutex); 749d5a114a6SFelix Kuehling 750d5a114a6SFelix Kuehling return 0; 751d5a114a6SFelix Kuehling } 752d5a114a6SFelix Kuehling 7533e205a08SOak Zeng uint32_t kgd_gfx_v9_address_watch_get_offset(struct kgd_dev *kgd, 754d5a114a6SFelix Kuehling unsigned int watch_point_id, 755d5a114a6SFelix Kuehling unsigned int reg_offset) 756d5a114a6SFelix Kuehling { 757d5a114a6SFelix Kuehling return 0; 758d5a114a6SFelix Kuehling } 759d5a114a6SFelix Kuehling 760ad5901dfSYong Zhao static void kgd_gfx_v9_set_vm_context_page_table_base(struct kgd_dev *kgd, 761ad5901dfSYong Zhao uint32_t vmid, uint64_t page_table_base) 762d5a114a6SFelix Kuehling { 763d5a114a6SFelix Kuehling struct amdgpu_device *adev = get_amdgpu_device(kgd); 764d5a114a6SFelix Kuehling 765d5a114a6SFelix Kuehling if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 766d5a114a6SFelix Kuehling pr_err("trying to set page table base for wrong VMID %u\n", 767d5a114a6SFelix Kuehling vmid); 768d5a114a6SFelix Kuehling return; 769d5a114a6SFelix Kuehling } 770d5a114a6SFelix Kuehling 771435e2f97SYong Zhao mmhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 772d5a114a6SFelix Kuehling 773435e2f97SYong Zhao gfxhub_v1_0_setup_vm_pt_regs(adev, vmid, page_table_base); 774d5a114a6SFelix Kuehling } 7753e205a08SOak Zeng 776e392c887SYong Zhao const struct kfd2kgd_calls gfx_v9_kfd2kgd = { 7773e205a08SOak Zeng .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 7783e205a08SOak Zeng .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 7793e205a08SOak Zeng .init_interrupts = kgd_gfx_v9_init_interrupts, 7803e205a08SOak Zeng .hqd_load = kgd_gfx_v9_hqd_load, 7813e205a08SOak Zeng .hqd_sdma_load = kgd_hqd_sdma_load, 7823e205a08SOak Zeng .hqd_dump = kgd_gfx_v9_hqd_dump, 7833e205a08SOak Zeng .hqd_sdma_dump = kgd_hqd_sdma_dump, 7843e205a08SOak Zeng .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 7853e205a08SOak Zeng .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 7863e205a08SOak Zeng .hqd_destroy = kgd_gfx_v9_hqd_destroy, 7873e205a08SOak Zeng .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 7883e205a08SOak Zeng .address_watch_disable = kgd_gfx_v9_address_watch_disable, 7893e205a08SOak Zeng .address_watch_execute = kgd_gfx_v9_address_watch_execute, 7903e205a08SOak Zeng .wave_control_execute = kgd_gfx_v9_wave_control_execute, 7913e205a08SOak Zeng .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, 79256fc40abSYong Zhao .get_atc_vmid_pasid_mapping_info = 79356fc40abSYong Zhao kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, 7943e205a08SOak Zeng .get_tile_config = kgd_gfx_v9_get_tile_config, 7953e205a08SOak Zeng .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 7963e205a08SOak Zeng .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, 7973e205a08SOak Zeng .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, 7983e205a08SOak Zeng .get_hive_id = amdgpu_amdkfd_get_hive_id, 7993e205a08SOak Zeng }; 800