1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/fdtable.h> 25 #include <linux/uaccess.h> 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_amdkfd.h" 30 #include "amdgpu_ucode.h" 31 #include "gfx_v8_0.h" 32 #include "gca/gfx_8_0_sh_mask.h" 33 #include "gca/gfx_8_0_d.h" 34 #include "gca/gfx_8_0_enum.h" 35 #include "oss/oss_3_0_sh_mask.h" 36 #include "oss/oss_3_0_d.h" 37 #include "gmc/gmc_8_1_sh_mask.h" 38 #include "gmc/gmc_8_1_d.h" 39 #include "vi_structs.h" 40 #include "vid.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES 46 }; 47 48 struct vi_sdma_mqd; 49 50 /* 51 * Register access functions 52 */ 53 54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 55 uint32_t sh_mem_config, 56 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 57 uint32_t sh_mem_bases); 58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 59 unsigned int vmid); 60 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 61 uint32_t hpd_size, uint64_t hpd_gpu_addr); 62 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 63 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 64 uint32_t queue_id, uint32_t __user *wptr, 65 uint32_t wptr_shift, uint32_t wptr_mask, 66 struct mm_struct *mm); 67 static int kgd_hqd_dump(struct kgd_dev *kgd, 68 uint32_t pipe_id, uint32_t queue_id, 69 uint32_t (**dump)[2], uint32_t *n_regs); 70 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 71 uint32_t __user *wptr, struct mm_struct *mm); 72 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 73 uint32_t engine_id, uint32_t queue_id, 74 uint32_t (**dump)[2], uint32_t *n_regs); 75 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 76 uint32_t pipe_id, uint32_t queue_id); 77 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 78 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 79 enum kfd_preempt_type reset_type, 80 unsigned int utimeout, uint32_t pipe_id, 81 uint32_t queue_id); 82 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 83 unsigned int utimeout); 84 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); 85 static int kgd_address_watch_disable(struct kgd_dev *kgd); 86 static int kgd_address_watch_execute(struct kgd_dev *kgd, 87 unsigned int watch_point_id, 88 uint32_t cntl_val, 89 uint32_t addr_hi, 90 uint32_t addr_lo); 91 static int kgd_wave_control_execute(struct kgd_dev *kgd, 92 uint32_t gfx_index_val, 93 uint32_t sq_cmd); 94 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 95 unsigned int watch_point_id, 96 unsigned int reg_offset); 97 98 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 99 uint8_t vmid); 100 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 101 uint8_t vmid); 102 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid); 103 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 104 static void set_scratch_backing_va(struct kgd_dev *kgd, 105 uint64_t va, uint32_t vmid); 106 107 /* Because of REG_GET_FIELD() being used, we put this function in the 108 * asic specific file. 109 */ 110 static int get_tile_config(struct kgd_dev *kgd, 111 struct tile_config *config) 112 { 113 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 114 115 config->gb_addr_config = adev->gfx.config.gb_addr_config; 116 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 117 MC_ARB_RAMCFG, NOOFBANK); 118 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 119 MC_ARB_RAMCFG, NOOFRANKS); 120 121 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 122 config->num_tile_configs = 123 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 124 config->macro_tile_config_ptr = 125 adev->gfx.config.macrotile_mode_array; 126 config->num_macro_tile_configs = 127 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 128 129 return 0; 130 } 131 132 static const struct kfd2kgd_calls kfd2kgd = { 133 .init_gtt_mem_allocation = alloc_gtt_mem, 134 .free_gtt_mem = free_gtt_mem, 135 .get_local_mem_info = get_local_mem_info, 136 .get_gpu_clock_counter = get_gpu_clock_counter, 137 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 138 .alloc_pasid = amdgpu_pasid_alloc, 139 .free_pasid = amdgpu_pasid_free, 140 .program_sh_mem_settings = kgd_program_sh_mem_settings, 141 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 142 .init_pipeline = kgd_init_pipeline, 143 .init_interrupts = kgd_init_interrupts, 144 .hqd_load = kgd_hqd_load, 145 .hqd_sdma_load = kgd_hqd_sdma_load, 146 .hqd_dump = kgd_hqd_dump, 147 .hqd_sdma_dump = kgd_hqd_sdma_dump, 148 .hqd_is_occupied = kgd_hqd_is_occupied, 149 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 150 .hqd_destroy = kgd_hqd_destroy, 151 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 152 .address_watch_disable = kgd_address_watch_disable, 153 .address_watch_execute = kgd_address_watch_execute, 154 .wave_control_execute = kgd_wave_control_execute, 155 .address_watch_get_offset = kgd_address_watch_get_offset, 156 .get_atc_vmid_pasid_mapping_pasid = 157 get_atc_vmid_pasid_mapping_pasid, 158 .get_atc_vmid_pasid_mapping_valid = 159 get_atc_vmid_pasid_mapping_valid, 160 .write_vmid_invalidate_request = write_vmid_invalidate_request, 161 .get_fw_version = get_fw_version, 162 .set_scratch_backing_va = set_scratch_backing_va, 163 .get_tile_config = get_tile_config, 164 .get_cu_info = get_cu_info, 165 .get_vram_usage = amdgpu_amdkfd_get_vram_usage 166 }; 167 168 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) 169 { 170 return (struct kfd2kgd_calls *)&kfd2kgd; 171 } 172 173 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 174 { 175 return (struct amdgpu_device *)kgd; 176 } 177 178 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 179 uint32_t queue, uint32_t vmid) 180 { 181 struct amdgpu_device *adev = get_amdgpu_device(kgd); 182 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 183 184 mutex_lock(&adev->srbm_mutex); 185 WREG32(mmSRBM_GFX_CNTL, value); 186 } 187 188 static void unlock_srbm(struct kgd_dev *kgd) 189 { 190 struct amdgpu_device *adev = get_amdgpu_device(kgd); 191 192 WREG32(mmSRBM_GFX_CNTL, 0); 193 mutex_unlock(&adev->srbm_mutex); 194 } 195 196 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 197 uint32_t queue_id) 198 { 199 struct amdgpu_device *adev = get_amdgpu_device(kgd); 200 201 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 202 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 203 204 lock_srbm(kgd, mec, pipe, queue_id, 0); 205 } 206 207 static void release_queue(struct kgd_dev *kgd) 208 { 209 unlock_srbm(kgd); 210 } 211 212 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 213 uint32_t sh_mem_config, 214 uint32_t sh_mem_ape1_base, 215 uint32_t sh_mem_ape1_limit, 216 uint32_t sh_mem_bases) 217 { 218 struct amdgpu_device *adev = get_amdgpu_device(kgd); 219 220 lock_srbm(kgd, 0, 0, 0, vmid); 221 222 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 223 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 224 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 225 WREG32(mmSH_MEM_BASES, sh_mem_bases); 226 227 unlock_srbm(kgd); 228 } 229 230 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 231 unsigned int vmid) 232 { 233 struct amdgpu_device *adev = get_amdgpu_device(kgd); 234 235 /* 236 * We have to assume that there is no outstanding mapping. 237 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 238 * a mapping is in progress or because a mapping finished 239 * and the SW cleared it. 240 * So the protocol is to always wait & clear. 241 */ 242 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 243 ATC_VMID0_PASID_MAPPING__VALID_MASK; 244 245 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 246 247 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 248 cpu_relax(); 249 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 250 251 /* Mapping vmid to pasid also for IH block */ 252 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 253 254 return 0; 255 } 256 257 static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id, 258 uint32_t hpd_size, uint64_t hpd_gpu_addr) 259 { 260 /* amdgpu owns the per-pipe state */ 261 return 0; 262 } 263 264 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 265 { 266 struct amdgpu_device *adev = get_amdgpu_device(kgd); 267 uint32_t mec; 268 uint32_t pipe; 269 270 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 271 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 272 273 lock_srbm(kgd, mec, pipe, 0, 0); 274 275 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); 276 277 unlock_srbm(kgd); 278 279 return 0; 280 } 281 282 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m) 283 { 284 uint32_t retval; 285 286 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 287 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 288 pr_debug("kfd: sdma base address: 0x%x\n", retval); 289 290 return retval; 291 } 292 293 static inline struct vi_mqd *get_mqd(void *mqd) 294 { 295 return (struct vi_mqd *)mqd; 296 } 297 298 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 299 { 300 return (struct vi_sdma_mqd *)mqd; 301 } 302 303 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 304 uint32_t queue_id, uint32_t __user *wptr, 305 uint32_t wptr_shift, uint32_t wptr_mask, 306 struct mm_struct *mm) 307 { 308 struct amdgpu_device *adev = get_amdgpu_device(kgd); 309 struct vi_mqd *m; 310 uint32_t *mqd_hqd; 311 uint32_t reg, wptr_val, data; 312 bool valid_wptr = false; 313 314 m = get_mqd(mqd); 315 316 acquire_queue(kgd, pipe_id, queue_id); 317 318 /* HIQ is set during driver init period with vmid set to 0*/ 319 if (m->cp_hqd_vmid == 0) { 320 uint32_t value, mec, pipe; 321 322 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 323 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 324 325 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 326 mec, pipe, queue_id); 327 value = RREG32(mmRLC_CP_SCHEDULERS); 328 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 329 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 330 WREG32(mmRLC_CP_SCHEDULERS, value); 331 } 332 333 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 334 mqd_hqd = &m->cp_mqd_base_addr_lo; 335 336 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) 337 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 338 339 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 340 * This is safe since EOP RPTR==WPTR for any inactive HQD 341 * on ASICs that do not support context-save. 342 * EOP writes/reads can start anywhere in the ring. 343 */ 344 if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { 345 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); 346 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); 347 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); 348 } 349 350 for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) 351 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 352 353 /* Copy userspace write pointer value to register. 354 * Activate doorbell logic to monitor subsequent changes. 355 */ 356 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 357 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 358 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 359 360 /* read_user_ptr may take the mm->mmap_sem. 361 * release srbm_mutex to avoid circular dependency between 362 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 363 */ 364 release_queue(kgd); 365 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 366 acquire_queue(kgd, pipe_id, queue_id); 367 if (valid_wptr) 368 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 369 370 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 371 WREG32(mmCP_HQD_ACTIVE, data); 372 373 release_queue(kgd); 374 375 return 0; 376 } 377 378 static int kgd_hqd_dump(struct kgd_dev *kgd, 379 uint32_t pipe_id, uint32_t queue_id, 380 uint32_t (**dump)[2], uint32_t *n_regs) 381 { 382 struct amdgpu_device *adev = get_amdgpu_device(kgd); 383 uint32_t i = 0, reg; 384 #define HQD_N_REGS (54+4) 385 #define DUMP_REG(addr) do { \ 386 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 387 break; \ 388 (*dump)[i][0] = (addr) << 2; \ 389 (*dump)[i++][1] = RREG32(addr); \ 390 } while (0) 391 392 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 393 if (*dump == NULL) 394 return -ENOMEM; 395 396 acquire_queue(kgd, pipe_id, queue_id); 397 398 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 399 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 400 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 401 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 402 403 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) 404 DUMP_REG(reg); 405 406 release_queue(kgd); 407 408 WARN_ON_ONCE(i != HQD_N_REGS); 409 *n_regs = i; 410 411 return 0; 412 } 413 414 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 415 uint32_t __user *wptr, struct mm_struct *mm) 416 { 417 struct amdgpu_device *adev = get_amdgpu_device(kgd); 418 struct vi_sdma_mqd *m; 419 unsigned long end_jiffies; 420 uint32_t sdma_base_addr; 421 uint32_t data; 422 423 m = get_sdma_mqd(mqd); 424 sdma_base_addr = get_sdma_base_addr(m); 425 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 426 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 427 428 end_jiffies = msecs_to_jiffies(2000) + jiffies; 429 while (true) { 430 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 431 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 432 break; 433 if (time_after(jiffies, end_jiffies)) 434 return -ETIME; 435 usleep_range(500, 1000); 436 } 437 if (m->sdma_engine_id) { 438 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); 439 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, 440 RESUME_CTX, 0); 441 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); 442 } else { 443 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); 444 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 445 RESUME_CTX, 0); 446 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); 447 } 448 449 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 450 ENABLE, 1); 451 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 452 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 453 454 if (read_user_wptr(mm, wptr, data)) 455 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); 456 else 457 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 458 m->sdmax_rlcx_rb_rptr); 459 460 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, 461 m->sdmax_rlcx_virtual_addr); 462 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 463 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 464 m->sdmax_rlcx_rb_base_hi); 465 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 466 m->sdmax_rlcx_rb_rptr_addr_lo); 467 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 468 m->sdmax_rlcx_rb_rptr_addr_hi); 469 470 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 471 RB_ENABLE, 1); 472 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 473 474 return 0; 475 } 476 477 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 478 uint32_t engine_id, uint32_t queue_id, 479 uint32_t (**dump)[2], uint32_t *n_regs) 480 { 481 struct amdgpu_device *adev = get_amdgpu_device(kgd); 482 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 483 queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 484 uint32_t i = 0, reg; 485 #undef HQD_N_REGS 486 #define HQD_N_REGS (19+4+2+3+7) 487 488 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 489 if (*dump == NULL) 490 return -ENOMEM; 491 492 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 493 DUMP_REG(sdma_offset + reg); 494 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 495 reg++) 496 DUMP_REG(sdma_offset + reg); 497 for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; 498 reg++) 499 DUMP_REG(sdma_offset + reg); 500 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; 501 reg++) 502 DUMP_REG(sdma_offset + reg); 503 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; 504 reg++) 505 DUMP_REG(sdma_offset + reg); 506 507 WARN_ON_ONCE(i != HQD_N_REGS); 508 *n_regs = i; 509 510 return 0; 511 } 512 513 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 514 uint32_t pipe_id, uint32_t queue_id) 515 { 516 struct amdgpu_device *adev = get_amdgpu_device(kgd); 517 uint32_t act; 518 bool retval = false; 519 uint32_t low, high; 520 521 acquire_queue(kgd, pipe_id, queue_id); 522 act = RREG32(mmCP_HQD_ACTIVE); 523 if (act) { 524 low = lower_32_bits(queue_address >> 8); 525 high = upper_32_bits(queue_address >> 8); 526 527 if (low == RREG32(mmCP_HQD_PQ_BASE) && 528 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 529 retval = true; 530 } 531 release_queue(kgd); 532 return retval; 533 } 534 535 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 536 { 537 struct amdgpu_device *adev = get_amdgpu_device(kgd); 538 struct vi_sdma_mqd *m; 539 uint32_t sdma_base_addr; 540 uint32_t sdma_rlc_rb_cntl; 541 542 m = get_sdma_mqd(mqd); 543 sdma_base_addr = get_sdma_base_addr(m); 544 545 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 546 547 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 548 return true; 549 550 return false; 551 } 552 553 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 554 enum kfd_preempt_type reset_type, 555 unsigned int utimeout, uint32_t pipe_id, 556 uint32_t queue_id) 557 { 558 struct amdgpu_device *adev = get_amdgpu_device(kgd); 559 uint32_t temp; 560 enum hqd_dequeue_request_type type; 561 unsigned long flags, end_jiffies; 562 int retry; 563 struct vi_mqd *m = get_mqd(mqd); 564 565 acquire_queue(kgd, pipe_id, queue_id); 566 567 if (m->cp_hqd_vmid == 0) 568 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); 569 570 switch (reset_type) { 571 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 572 type = DRAIN_PIPE; 573 break; 574 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 575 type = RESET_WAVES; 576 break; 577 default: 578 type = DRAIN_PIPE; 579 break; 580 } 581 582 /* Workaround: If IQ timer is active and the wait time is close to or 583 * equal to 0, dequeueing is not safe. Wait until either the wait time 584 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 585 * cleared before continuing. Also, ensure wait times are set to at 586 * least 0x3. 587 */ 588 local_irq_save(flags); 589 preempt_disable(); 590 retry = 5000; /* wait for 500 usecs at maximum */ 591 while (true) { 592 temp = RREG32(mmCP_HQD_IQ_TIMER); 593 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 594 pr_debug("HW is processing IQ\n"); 595 goto loop; 596 } 597 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 598 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 599 == 3) /* SEM-rearm is safe */ 600 break; 601 /* Wait time 3 is safe for CP, but our MMIO read/write 602 * time is close to 1 microsecond, so check for 10 to 603 * leave more buffer room 604 */ 605 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 606 >= 10) 607 break; 608 pr_debug("IQ timer is active\n"); 609 } else 610 break; 611 loop: 612 if (!retry) { 613 pr_err("CP HQD IQ timer status time out\n"); 614 break; 615 } 616 ndelay(100); 617 --retry; 618 } 619 retry = 1000; 620 while (true) { 621 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 622 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 623 break; 624 pr_debug("Dequeue request is pending\n"); 625 626 if (!retry) { 627 pr_err("CP HQD dequeue request time out\n"); 628 break; 629 } 630 ndelay(100); 631 --retry; 632 } 633 local_irq_restore(flags); 634 preempt_enable(); 635 636 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 637 638 end_jiffies = (utimeout * HZ / 1000) + jiffies; 639 while (true) { 640 temp = RREG32(mmCP_HQD_ACTIVE); 641 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 642 break; 643 if (time_after(jiffies, end_jiffies)) { 644 pr_err("cp queue preemption time out.\n"); 645 release_queue(kgd); 646 return -ETIME; 647 } 648 usleep_range(500, 1000); 649 } 650 651 release_queue(kgd); 652 return 0; 653 } 654 655 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 656 unsigned int utimeout) 657 { 658 struct amdgpu_device *adev = get_amdgpu_device(kgd); 659 struct vi_sdma_mqd *m; 660 uint32_t sdma_base_addr; 661 uint32_t temp; 662 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 663 664 m = get_sdma_mqd(mqd); 665 sdma_base_addr = get_sdma_base_addr(m); 666 667 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 668 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 669 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 670 671 while (true) { 672 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 673 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 674 break; 675 if (time_after(jiffies, end_jiffies)) 676 return -ETIME; 677 usleep_range(500, 1000); 678 } 679 680 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 681 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 682 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 683 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 684 685 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 686 687 return 0; 688 } 689 690 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 691 uint8_t vmid) 692 { 693 uint32_t reg; 694 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 695 696 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 697 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 698 } 699 700 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 701 uint8_t vmid) 702 { 703 uint32_t reg; 704 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 705 706 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 707 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 708 } 709 710 static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid) 711 { 712 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 713 714 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 715 } 716 717 static int kgd_address_watch_disable(struct kgd_dev *kgd) 718 { 719 return 0; 720 } 721 722 static int kgd_address_watch_execute(struct kgd_dev *kgd, 723 unsigned int watch_point_id, 724 uint32_t cntl_val, 725 uint32_t addr_hi, 726 uint32_t addr_lo) 727 { 728 return 0; 729 } 730 731 static int kgd_wave_control_execute(struct kgd_dev *kgd, 732 uint32_t gfx_index_val, 733 uint32_t sq_cmd) 734 { 735 struct amdgpu_device *adev = get_amdgpu_device(kgd); 736 uint32_t data = 0; 737 738 mutex_lock(&adev->grbm_idx_mutex); 739 740 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 741 WREG32(mmSQ_CMD, sq_cmd); 742 743 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 744 INSTANCE_BROADCAST_WRITES, 1); 745 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 746 SH_BROADCAST_WRITES, 1); 747 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 748 SE_BROADCAST_WRITES, 1); 749 750 WREG32(mmGRBM_GFX_INDEX, data); 751 mutex_unlock(&adev->grbm_idx_mutex); 752 753 return 0; 754 } 755 756 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 757 unsigned int watch_point_id, 758 unsigned int reg_offset) 759 { 760 return 0; 761 } 762 763 static void set_scratch_backing_va(struct kgd_dev *kgd, 764 uint64_t va, uint32_t vmid) 765 { 766 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 767 768 lock_srbm(kgd, 0, 0, 0, vmid); 769 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 770 unlock_srbm(kgd); 771 } 772 773 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 774 { 775 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 776 const union amdgpu_firmware_header *hdr; 777 778 BUG_ON(kgd == NULL); 779 780 switch (type) { 781 case KGD_ENGINE_PFP: 782 hdr = (const union amdgpu_firmware_header *) 783 adev->gfx.pfp_fw->data; 784 break; 785 786 case KGD_ENGINE_ME: 787 hdr = (const union amdgpu_firmware_header *) 788 adev->gfx.me_fw->data; 789 break; 790 791 case KGD_ENGINE_CE: 792 hdr = (const union amdgpu_firmware_header *) 793 adev->gfx.ce_fw->data; 794 break; 795 796 case KGD_ENGINE_MEC1: 797 hdr = (const union amdgpu_firmware_header *) 798 adev->gfx.mec_fw->data; 799 break; 800 801 case KGD_ENGINE_MEC2: 802 hdr = (const union amdgpu_firmware_header *) 803 adev->gfx.mec2_fw->data; 804 break; 805 806 case KGD_ENGINE_RLC: 807 hdr = (const union amdgpu_firmware_header *) 808 adev->gfx.rlc_fw->data; 809 break; 810 811 case KGD_ENGINE_SDMA1: 812 hdr = (const union amdgpu_firmware_header *) 813 adev->sdma.instance[0].fw->data; 814 break; 815 816 case KGD_ENGINE_SDMA2: 817 hdr = (const union amdgpu_firmware_header *) 818 adev->sdma.instance[1].fw->data; 819 break; 820 821 default: 822 return 0; 823 } 824 825 if (hdr == NULL) 826 return 0; 827 828 /* Only 12 bit in use*/ 829 return hdr->common.ucode_version; 830 } 831