1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/fdtable.h> 25 #include <linux/uaccess.h> 26 #include <linux/firmware.h> 27 #include <drm/drmP.h> 28 #include "amdgpu.h" 29 #include "amdgpu_amdkfd.h" 30 #include "amdgpu_ucode.h" 31 #include "gfx_v8_0.h" 32 #include "gca/gfx_8_0_sh_mask.h" 33 #include "gca/gfx_8_0_d.h" 34 #include "gca/gfx_8_0_enum.h" 35 #include "oss/oss_3_0_sh_mask.h" 36 #include "oss/oss_3_0_d.h" 37 #include "gmc/gmc_8_1_sh_mask.h" 38 #include "gmc/gmc_8_1_d.h" 39 #include "vi_structs.h" 40 #include "vid.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES 46 }; 47 48 struct vi_sdma_mqd; 49 50 /* 51 * Register access functions 52 */ 53 54 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 55 uint32_t sh_mem_config, 56 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 57 uint32_t sh_mem_bases); 58 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 59 unsigned int vmid); 60 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 61 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 62 uint32_t queue_id, uint32_t __user *wptr, 63 uint32_t wptr_shift, uint32_t wptr_mask, 64 struct mm_struct *mm); 65 static int kgd_hqd_dump(struct kgd_dev *kgd, 66 uint32_t pipe_id, uint32_t queue_id, 67 uint32_t (**dump)[2], uint32_t *n_regs); 68 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 69 uint32_t __user *wptr, struct mm_struct *mm); 70 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 71 uint32_t engine_id, uint32_t queue_id, 72 uint32_t (**dump)[2], uint32_t *n_regs); 73 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 74 uint32_t pipe_id, uint32_t queue_id); 75 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 76 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 77 enum kfd_preempt_type reset_type, 78 unsigned int utimeout, uint32_t pipe_id, 79 uint32_t queue_id); 80 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 81 unsigned int utimeout); 82 static int kgd_address_watch_disable(struct kgd_dev *kgd); 83 static int kgd_address_watch_execute(struct kgd_dev *kgd, 84 unsigned int watch_point_id, 85 uint32_t cntl_val, 86 uint32_t addr_hi, 87 uint32_t addr_lo); 88 static int kgd_wave_control_execute(struct kgd_dev *kgd, 89 uint32_t gfx_index_val, 90 uint32_t sq_cmd); 91 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 92 unsigned int watch_point_id, 93 unsigned int reg_offset); 94 95 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 96 uint8_t vmid); 97 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 98 uint8_t vmid); 99 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 100 static void set_scratch_backing_va(struct kgd_dev *kgd, 101 uint64_t va, uint32_t vmid); 102 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 103 uint32_t page_table_base); 104 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 105 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 106 107 /* Because of REG_GET_FIELD() being used, we put this function in the 108 * asic specific file. 109 */ 110 static int get_tile_config(struct kgd_dev *kgd, 111 struct tile_config *config) 112 { 113 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 114 115 config->gb_addr_config = adev->gfx.config.gb_addr_config; 116 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 117 MC_ARB_RAMCFG, NOOFBANK); 118 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 119 MC_ARB_RAMCFG, NOOFRANKS); 120 121 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 122 config->num_tile_configs = 123 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 124 config->macro_tile_config_ptr = 125 adev->gfx.config.macrotile_mode_array; 126 config->num_macro_tile_configs = 127 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 128 129 return 0; 130 } 131 132 static const struct kfd2kgd_calls kfd2kgd = { 133 .init_gtt_mem_allocation = alloc_gtt_mem, 134 .free_gtt_mem = free_gtt_mem, 135 .get_local_mem_info = get_local_mem_info, 136 .get_gpu_clock_counter = get_gpu_clock_counter, 137 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz, 138 .alloc_pasid = amdgpu_pasid_alloc, 139 .free_pasid = amdgpu_pasid_free, 140 .program_sh_mem_settings = kgd_program_sh_mem_settings, 141 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 142 .init_interrupts = kgd_init_interrupts, 143 .hqd_load = kgd_hqd_load, 144 .hqd_sdma_load = kgd_hqd_sdma_load, 145 .hqd_dump = kgd_hqd_dump, 146 .hqd_sdma_dump = kgd_hqd_sdma_dump, 147 .hqd_is_occupied = kgd_hqd_is_occupied, 148 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 149 .hqd_destroy = kgd_hqd_destroy, 150 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 151 .address_watch_disable = kgd_address_watch_disable, 152 .address_watch_execute = kgd_address_watch_execute, 153 .wave_control_execute = kgd_wave_control_execute, 154 .address_watch_get_offset = kgd_address_watch_get_offset, 155 .get_atc_vmid_pasid_mapping_pasid = 156 get_atc_vmid_pasid_mapping_pasid, 157 .get_atc_vmid_pasid_mapping_valid = 158 get_atc_vmid_pasid_mapping_valid, 159 .get_fw_version = get_fw_version, 160 .set_scratch_backing_va = set_scratch_backing_va, 161 .get_tile_config = get_tile_config, 162 .get_cu_info = get_cu_info, 163 .get_vram_usage = amdgpu_amdkfd_get_vram_usage, 164 .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm, 165 .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm, 166 .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm, 167 .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir, 168 .set_vm_context_page_table_base = set_vm_context_page_table_base, 169 .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu, 170 .free_memory_of_gpu = amdgpu_amdkfd_gpuvm_free_memory_of_gpu, 171 .map_memory_to_gpu = amdgpu_amdkfd_gpuvm_map_memory_to_gpu, 172 .unmap_memory_to_gpu = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu, 173 .sync_memory = amdgpu_amdkfd_gpuvm_sync_memory, 174 .map_gtt_bo_to_kernel = amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel, 175 .restore_process_bos = amdgpu_amdkfd_gpuvm_restore_process_bos, 176 .invalidate_tlbs = invalidate_tlbs, 177 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 178 .submit_ib = amdgpu_amdkfd_submit_ib, 179 }; 180 181 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) 182 { 183 return (struct kfd2kgd_calls *)&kfd2kgd; 184 } 185 186 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 187 { 188 return (struct amdgpu_device *)kgd; 189 } 190 191 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 192 uint32_t queue, uint32_t vmid) 193 { 194 struct amdgpu_device *adev = get_amdgpu_device(kgd); 195 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 196 197 mutex_lock(&adev->srbm_mutex); 198 WREG32(mmSRBM_GFX_CNTL, value); 199 } 200 201 static void unlock_srbm(struct kgd_dev *kgd) 202 { 203 struct amdgpu_device *adev = get_amdgpu_device(kgd); 204 205 WREG32(mmSRBM_GFX_CNTL, 0); 206 mutex_unlock(&adev->srbm_mutex); 207 } 208 209 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 210 uint32_t queue_id) 211 { 212 struct amdgpu_device *adev = get_amdgpu_device(kgd); 213 214 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 215 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 216 217 lock_srbm(kgd, mec, pipe, queue_id, 0); 218 } 219 220 static void release_queue(struct kgd_dev *kgd) 221 { 222 unlock_srbm(kgd); 223 } 224 225 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 226 uint32_t sh_mem_config, 227 uint32_t sh_mem_ape1_base, 228 uint32_t sh_mem_ape1_limit, 229 uint32_t sh_mem_bases) 230 { 231 struct amdgpu_device *adev = get_amdgpu_device(kgd); 232 233 lock_srbm(kgd, 0, 0, 0, vmid); 234 235 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 236 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 237 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 238 WREG32(mmSH_MEM_BASES, sh_mem_bases); 239 240 unlock_srbm(kgd); 241 } 242 243 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 244 unsigned int vmid) 245 { 246 struct amdgpu_device *adev = get_amdgpu_device(kgd); 247 248 /* 249 * We have to assume that there is no outstanding mapping. 250 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 251 * a mapping is in progress or because a mapping finished 252 * and the SW cleared it. 253 * So the protocol is to always wait & clear. 254 */ 255 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 256 ATC_VMID0_PASID_MAPPING__VALID_MASK; 257 258 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 259 260 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 261 cpu_relax(); 262 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 263 264 /* Mapping vmid to pasid also for IH block */ 265 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 266 267 return 0; 268 } 269 270 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 271 { 272 struct amdgpu_device *adev = get_amdgpu_device(kgd); 273 uint32_t mec; 274 uint32_t pipe; 275 276 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 277 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 278 279 lock_srbm(kgd, mec, pipe, 0, 0); 280 281 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK); 282 283 unlock_srbm(kgd); 284 285 return 0; 286 } 287 288 static inline uint32_t get_sdma_base_addr(struct vi_sdma_mqd *m) 289 { 290 uint32_t retval; 291 292 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 293 m->sdma_queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 294 pr_debug("kfd: sdma base address: 0x%x\n", retval); 295 296 return retval; 297 } 298 299 static inline struct vi_mqd *get_mqd(void *mqd) 300 { 301 return (struct vi_mqd *)mqd; 302 } 303 304 static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) 305 { 306 return (struct vi_sdma_mqd *)mqd; 307 } 308 309 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 310 uint32_t queue_id, uint32_t __user *wptr, 311 uint32_t wptr_shift, uint32_t wptr_mask, 312 struct mm_struct *mm) 313 { 314 struct amdgpu_device *adev = get_amdgpu_device(kgd); 315 struct vi_mqd *m; 316 uint32_t *mqd_hqd; 317 uint32_t reg, wptr_val, data; 318 bool valid_wptr = false; 319 320 m = get_mqd(mqd); 321 322 acquire_queue(kgd, pipe_id, queue_id); 323 324 /* HIQ is set during driver init period with vmid set to 0*/ 325 if (m->cp_hqd_vmid == 0) { 326 uint32_t value, mec, pipe; 327 328 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 329 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 330 331 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 332 mec, pipe, queue_id); 333 value = RREG32(mmRLC_CP_SCHEDULERS); 334 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 335 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 336 WREG32(mmRLC_CP_SCHEDULERS, value); 337 } 338 339 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 340 mqd_hqd = &m->cp_mqd_base_addr_lo; 341 342 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_CONTROL; reg++) 343 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 344 345 /* Tonga errata: EOP RPTR/WPTR should be left unmodified. 346 * This is safe since EOP RPTR==WPTR for any inactive HQD 347 * on ASICs that do not support context-save. 348 * EOP writes/reads can start anywhere in the ring. 349 */ 350 if (get_amdgpu_device(kgd)->asic_type != CHIP_TONGA) { 351 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr); 352 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr); 353 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem); 354 } 355 356 for (reg = mmCP_HQD_EOP_EVENTS; reg <= mmCP_HQD_ERROR; reg++) 357 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 358 359 /* Copy userspace write pointer value to register. 360 * Activate doorbell logic to monitor subsequent changes. 361 */ 362 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 363 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 364 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 365 366 /* read_user_ptr may take the mm->mmap_sem. 367 * release srbm_mutex to avoid circular dependency between 368 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 369 */ 370 release_queue(kgd); 371 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 372 acquire_queue(kgd, pipe_id, queue_id); 373 if (valid_wptr) 374 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 375 376 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 377 WREG32(mmCP_HQD_ACTIVE, data); 378 379 release_queue(kgd); 380 381 return 0; 382 } 383 384 static int kgd_hqd_dump(struct kgd_dev *kgd, 385 uint32_t pipe_id, uint32_t queue_id, 386 uint32_t (**dump)[2], uint32_t *n_regs) 387 { 388 struct amdgpu_device *adev = get_amdgpu_device(kgd); 389 uint32_t i = 0, reg; 390 #define HQD_N_REGS (54+4) 391 #define DUMP_REG(addr) do { \ 392 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 393 break; \ 394 (*dump)[i][0] = (addr) << 2; \ 395 (*dump)[i++][1] = RREG32(addr); \ 396 } while (0) 397 398 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 399 if (*dump == NULL) 400 return -ENOMEM; 401 402 acquire_queue(kgd, pipe_id, queue_id); 403 404 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 405 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 406 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 407 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 408 409 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_HQD_EOP_DONES; reg++) 410 DUMP_REG(reg); 411 412 release_queue(kgd); 413 414 WARN_ON_ONCE(i != HQD_N_REGS); 415 *n_regs = i; 416 417 return 0; 418 } 419 420 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 421 uint32_t __user *wptr, struct mm_struct *mm) 422 { 423 struct amdgpu_device *adev = get_amdgpu_device(kgd); 424 struct vi_sdma_mqd *m; 425 unsigned long end_jiffies; 426 uint32_t sdma_base_addr; 427 uint32_t data; 428 429 m = get_sdma_mqd(mqd); 430 sdma_base_addr = get_sdma_base_addr(m); 431 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 432 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 433 434 end_jiffies = msecs_to_jiffies(2000) + jiffies; 435 while (true) { 436 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 437 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 438 break; 439 if (time_after(jiffies, end_jiffies)) 440 return -ETIME; 441 usleep_range(500, 1000); 442 } 443 if (m->sdma_engine_id) { 444 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); 445 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, 446 RESUME_CTX, 0); 447 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); 448 } else { 449 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); 450 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 451 RESUME_CTX, 0); 452 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); 453 } 454 455 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 456 ENABLE, 1); 457 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 458 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 459 460 if (read_user_wptr(mm, wptr, data)) 461 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); 462 else 463 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 464 m->sdmax_rlcx_rb_rptr); 465 466 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, 467 m->sdmax_rlcx_virtual_addr); 468 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 469 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 470 m->sdmax_rlcx_rb_base_hi); 471 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 472 m->sdmax_rlcx_rb_rptr_addr_lo); 473 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 474 m->sdmax_rlcx_rb_rptr_addr_hi); 475 476 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 477 RB_ENABLE, 1); 478 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 479 480 return 0; 481 } 482 483 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 484 uint32_t engine_id, uint32_t queue_id, 485 uint32_t (**dump)[2], uint32_t *n_regs) 486 { 487 struct amdgpu_device *adev = get_amdgpu_device(kgd); 488 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 489 queue_id * KFD_VI_SDMA_QUEUE_OFFSET; 490 uint32_t i = 0, reg; 491 #undef HQD_N_REGS 492 #define HQD_N_REGS (19+4+2+3+7) 493 494 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 495 if (*dump == NULL) 496 return -ENOMEM; 497 498 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 499 DUMP_REG(sdma_offset + reg); 500 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 501 reg++) 502 DUMP_REG(sdma_offset + reg); 503 for (reg = mmSDMA0_RLC0_CSA_ADDR_LO; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; 504 reg++) 505 DUMP_REG(sdma_offset + reg); 506 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; reg <= mmSDMA0_RLC0_DUMMY_REG; 507 reg++) 508 DUMP_REG(sdma_offset + reg); 509 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; reg <= mmSDMA0_RLC0_MIDCMD_CNTL; 510 reg++) 511 DUMP_REG(sdma_offset + reg); 512 513 WARN_ON_ONCE(i != HQD_N_REGS); 514 *n_regs = i; 515 516 return 0; 517 } 518 519 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 520 uint32_t pipe_id, uint32_t queue_id) 521 { 522 struct amdgpu_device *adev = get_amdgpu_device(kgd); 523 uint32_t act; 524 bool retval = false; 525 uint32_t low, high; 526 527 acquire_queue(kgd, pipe_id, queue_id); 528 act = RREG32(mmCP_HQD_ACTIVE); 529 if (act) { 530 low = lower_32_bits(queue_address >> 8); 531 high = upper_32_bits(queue_address >> 8); 532 533 if (low == RREG32(mmCP_HQD_PQ_BASE) && 534 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 535 retval = true; 536 } 537 release_queue(kgd); 538 return retval; 539 } 540 541 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 542 { 543 struct amdgpu_device *adev = get_amdgpu_device(kgd); 544 struct vi_sdma_mqd *m; 545 uint32_t sdma_base_addr; 546 uint32_t sdma_rlc_rb_cntl; 547 548 m = get_sdma_mqd(mqd); 549 sdma_base_addr = get_sdma_base_addr(m); 550 551 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 552 553 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 554 return true; 555 556 return false; 557 } 558 559 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 560 enum kfd_preempt_type reset_type, 561 unsigned int utimeout, uint32_t pipe_id, 562 uint32_t queue_id) 563 { 564 struct amdgpu_device *adev = get_amdgpu_device(kgd); 565 uint32_t temp; 566 enum hqd_dequeue_request_type type; 567 unsigned long flags, end_jiffies; 568 int retry; 569 struct vi_mqd *m = get_mqd(mqd); 570 571 acquire_queue(kgd, pipe_id, queue_id); 572 573 if (m->cp_hqd_vmid == 0) 574 WREG32_FIELD(RLC_CP_SCHEDULERS, scheduler1, 0); 575 576 switch (reset_type) { 577 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 578 type = DRAIN_PIPE; 579 break; 580 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 581 type = RESET_WAVES; 582 break; 583 default: 584 type = DRAIN_PIPE; 585 break; 586 } 587 588 /* Workaround: If IQ timer is active and the wait time is close to or 589 * equal to 0, dequeueing is not safe. Wait until either the wait time 590 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 591 * cleared before continuing. Also, ensure wait times are set to at 592 * least 0x3. 593 */ 594 local_irq_save(flags); 595 preempt_disable(); 596 retry = 5000; /* wait for 500 usecs at maximum */ 597 while (true) { 598 temp = RREG32(mmCP_HQD_IQ_TIMER); 599 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 600 pr_debug("HW is processing IQ\n"); 601 goto loop; 602 } 603 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 604 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 605 == 3) /* SEM-rearm is safe */ 606 break; 607 /* Wait time 3 is safe for CP, but our MMIO read/write 608 * time is close to 1 microsecond, so check for 10 to 609 * leave more buffer room 610 */ 611 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 612 >= 10) 613 break; 614 pr_debug("IQ timer is active\n"); 615 } else 616 break; 617 loop: 618 if (!retry) { 619 pr_err("CP HQD IQ timer status time out\n"); 620 break; 621 } 622 ndelay(100); 623 --retry; 624 } 625 retry = 1000; 626 while (true) { 627 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 628 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 629 break; 630 pr_debug("Dequeue request is pending\n"); 631 632 if (!retry) { 633 pr_err("CP HQD dequeue request time out\n"); 634 break; 635 } 636 ndelay(100); 637 --retry; 638 } 639 local_irq_restore(flags); 640 preempt_enable(); 641 642 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 643 644 end_jiffies = (utimeout * HZ / 1000) + jiffies; 645 while (true) { 646 temp = RREG32(mmCP_HQD_ACTIVE); 647 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 648 break; 649 if (time_after(jiffies, end_jiffies)) { 650 pr_err("cp queue preemption time out.\n"); 651 release_queue(kgd); 652 return -ETIME; 653 } 654 usleep_range(500, 1000); 655 } 656 657 release_queue(kgd); 658 return 0; 659 } 660 661 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 662 unsigned int utimeout) 663 { 664 struct amdgpu_device *adev = get_amdgpu_device(kgd); 665 struct vi_sdma_mqd *m; 666 uint32_t sdma_base_addr; 667 uint32_t temp; 668 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 669 670 m = get_sdma_mqd(mqd); 671 sdma_base_addr = get_sdma_base_addr(m); 672 673 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 674 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 675 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 676 677 while (true) { 678 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 679 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 680 break; 681 if (time_after(jiffies, end_jiffies)) 682 return -ETIME; 683 usleep_range(500, 1000); 684 } 685 686 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 687 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 688 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 689 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 690 691 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 692 693 return 0; 694 } 695 696 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 697 uint8_t vmid) 698 { 699 uint32_t reg; 700 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 701 702 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 703 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 704 } 705 706 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 707 uint8_t vmid) 708 { 709 uint32_t reg; 710 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 711 712 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 713 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 714 } 715 716 static int kgd_address_watch_disable(struct kgd_dev *kgd) 717 { 718 return 0; 719 } 720 721 static int kgd_address_watch_execute(struct kgd_dev *kgd, 722 unsigned int watch_point_id, 723 uint32_t cntl_val, 724 uint32_t addr_hi, 725 uint32_t addr_lo) 726 { 727 return 0; 728 } 729 730 static int kgd_wave_control_execute(struct kgd_dev *kgd, 731 uint32_t gfx_index_val, 732 uint32_t sq_cmd) 733 { 734 struct amdgpu_device *adev = get_amdgpu_device(kgd); 735 uint32_t data = 0; 736 737 mutex_lock(&adev->grbm_idx_mutex); 738 739 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 740 WREG32(mmSQ_CMD, sq_cmd); 741 742 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 743 INSTANCE_BROADCAST_WRITES, 1); 744 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 745 SH_BROADCAST_WRITES, 1); 746 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 747 SE_BROADCAST_WRITES, 1); 748 749 WREG32(mmGRBM_GFX_INDEX, data); 750 mutex_unlock(&adev->grbm_idx_mutex); 751 752 return 0; 753 } 754 755 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 756 unsigned int watch_point_id, 757 unsigned int reg_offset) 758 { 759 return 0; 760 } 761 762 static void set_scratch_backing_va(struct kgd_dev *kgd, 763 uint64_t va, uint32_t vmid) 764 { 765 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 766 767 lock_srbm(kgd, 0, 0, 0, vmid); 768 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 769 unlock_srbm(kgd); 770 } 771 772 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 773 { 774 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 775 const union amdgpu_firmware_header *hdr; 776 777 switch (type) { 778 case KGD_ENGINE_PFP: 779 hdr = (const union amdgpu_firmware_header *) 780 adev->gfx.pfp_fw->data; 781 break; 782 783 case KGD_ENGINE_ME: 784 hdr = (const union amdgpu_firmware_header *) 785 adev->gfx.me_fw->data; 786 break; 787 788 case KGD_ENGINE_CE: 789 hdr = (const union amdgpu_firmware_header *) 790 adev->gfx.ce_fw->data; 791 break; 792 793 case KGD_ENGINE_MEC1: 794 hdr = (const union amdgpu_firmware_header *) 795 adev->gfx.mec_fw->data; 796 break; 797 798 case KGD_ENGINE_MEC2: 799 hdr = (const union amdgpu_firmware_header *) 800 adev->gfx.mec2_fw->data; 801 break; 802 803 case KGD_ENGINE_RLC: 804 hdr = (const union amdgpu_firmware_header *) 805 adev->gfx.rlc_fw->data; 806 break; 807 808 case KGD_ENGINE_SDMA1: 809 hdr = (const union amdgpu_firmware_header *) 810 adev->sdma.instance[0].fw->data; 811 break; 812 813 case KGD_ENGINE_SDMA2: 814 hdr = (const union amdgpu_firmware_header *) 815 adev->sdma.instance[1].fw->data; 816 break; 817 818 default: 819 return 0; 820 } 821 822 if (hdr == NULL) 823 return 0; 824 825 /* Only 12 bit in use*/ 826 return hdr->common.ucode_version; 827 } 828 829 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 830 uint32_t page_table_base) 831 { 832 struct amdgpu_device *adev = get_amdgpu_device(kgd); 833 834 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 835 pr_err("trying to set page table base for wrong VMID\n"); 836 return; 837 } 838 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, page_table_base); 839 } 840 841 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 842 { 843 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 844 int vmid; 845 unsigned int tmp; 846 847 for (vmid = 0; vmid < 16; vmid++) { 848 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 849 continue; 850 851 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 852 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 853 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 854 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 855 RREG32(mmVM_INVALIDATE_RESPONSE); 856 break; 857 } 858 } 859 860 return 0; 861 } 862 863 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 864 { 865 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 866 867 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 868 pr_err("non kfd vmid %d\n", vmid); 869 return -EINVAL; 870 } 871 872 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 873 RREG32(mmVM_INVALIDATE_RESPONSE); 874 return 0; 875 } 876