1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/fdtable.h> 24 #include <linux/uaccess.h> 25 #include <linux/firmware.h> 26 #include <drm/drmP.h> 27 #include "amdgpu.h" 28 #include "amdgpu_amdkfd.h" 29 #include "cikd.h" 30 #include "cik_sdma.h" 31 #include "amdgpu_ucode.h" 32 #include "gfx_v7_0.h" 33 #include "gca/gfx_7_2_d.h" 34 #include "gca/gfx_7_2_enum.h" 35 #include "gca/gfx_7_2_sh_mask.h" 36 #include "oss/oss_2_0_d.h" 37 #include "oss/oss_2_0_sh_mask.h" 38 #include "gmc/gmc_7_1_d.h" 39 #include "gmc/gmc_7_1_sh_mask.h" 40 #include "cik_structs.h" 41 42 enum hqd_dequeue_request_type { 43 NO_ACTION = 0, 44 DRAIN_PIPE, 45 RESET_WAVES 46 }; 47 48 enum { 49 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 50 MAX_WATCH_ADDRESSES = 4 51 }; 52 53 enum { 54 ADDRESS_WATCH_REG_ADDR_HI = 0, 55 ADDRESS_WATCH_REG_ADDR_LO, 56 ADDRESS_WATCH_REG_CNTL, 57 ADDRESS_WATCH_REG_MAX 58 }; 59 60 /* not defined in the CI/KV reg file */ 61 enum { 62 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 63 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 64 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 65 /* extend the mask to 26 bits to match the low address field */ 66 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 67 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 68 }; 69 70 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { 71 mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL, 72 mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL, 73 mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL, 74 mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL 75 }; 76 77 union TCP_WATCH_CNTL_BITS { 78 struct { 79 uint32_t mask:24; 80 uint32_t vmid:4; 81 uint32_t atc:1; 82 uint32_t mode:2; 83 uint32_t valid:1; 84 } bitfields, bits; 85 uint32_t u32All; 86 signed int i32All; 87 float f32All; 88 }; 89 90 /* 91 * Register access functions 92 */ 93 94 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 95 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base, 96 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases); 97 98 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 99 unsigned int vmid); 100 101 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 102 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 103 uint32_t queue_id, uint32_t __user *wptr, 104 uint32_t wptr_shift, uint32_t wptr_mask, 105 struct mm_struct *mm); 106 static int kgd_hqd_dump(struct kgd_dev *kgd, 107 uint32_t pipe_id, uint32_t queue_id, 108 uint32_t (**dump)[2], uint32_t *n_regs); 109 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 110 uint32_t __user *wptr, struct mm_struct *mm); 111 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 112 uint32_t engine_id, uint32_t queue_id, 113 uint32_t (**dump)[2], uint32_t *n_regs); 114 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 115 uint32_t pipe_id, uint32_t queue_id); 116 117 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 118 enum kfd_preempt_type reset_type, 119 unsigned int utimeout, uint32_t pipe_id, 120 uint32_t queue_id); 121 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 122 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 123 unsigned int utimeout); 124 static int kgd_address_watch_disable(struct kgd_dev *kgd); 125 static int kgd_address_watch_execute(struct kgd_dev *kgd, 126 unsigned int watch_point_id, 127 uint32_t cntl_val, 128 uint32_t addr_hi, 129 uint32_t addr_lo); 130 static int kgd_wave_control_execute(struct kgd_dev *kgd, 131 uint32_t gfx_index_val, 132 uint32_t sq_cmd); 133 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 134 unsigned int watch_point_id, 135 unsigned int reg_offset); 136 137 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, uint8_t vmid); 138 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 139 uint8_t vmid); 140 141 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type); 142 static void set_scratch_backing_va(struct kgd_dev *kgd, 143 uint64_t va, uint32_t vmid); 144 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 145 uint64_t page_table_base); 146 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 147 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 148 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd); 149 150 /* Because of REG_GET_FIELD() being used, we put this function in the 151 * asic specific file. 152 */ 153 static int get_tile_config(struct kgd_dev *kgd, 154 struct tile_config *config) 155 { 156 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 157 158 config->gb_addr_config = adev->gfx.config.gb_addr_config; 159 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 160 MC_ARB_RAMCFG, NOOFBANK); 161 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 162 MC_ARB_RAMCFG, NOOFRANKS); 163 164 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 165 config->num_tile_configs = 166 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 167 config->macro_tile_config_ptr = 168 adev->gfx.config.macrotile_mode_array; 169 config->num_macro_tile_configs = 170 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 171 172 return 0; 173 } 174 175 static const struct kfd2kgd_calls kfd2kgd = { 176 .program_sh_mem_settings = kgd_program_sh_mem_settings, 177 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 178 .init_interrupts = kgd_init_interrupts, 179 .hqd_load = kgd_hqd_load, 180 .hqd_sdma_load = kgd_hqd_sdma_load, 181 .hqd_dump = kgd_hqd_dump, 182 .hqd_sdma_dump = kgd_hqd_sdma_dump, 183 .hqd_is_occupied = kgd_hqd_is_occupied, 184 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 185 .hqd_destroy = kgd_hqd_destroy, 186 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 187 .address_watch_disable = kgd_address_watch_disable, 188 .address_watch_execute = kgd_address_watch_execute, 189 .wave_control_execute = kgd_wave_control_execute, 190 .address_watch_get_offset = kgd_address_watch_get_offset, 191 .get_atc_vmid_pasid_mapping_pasid = get_atc_vmid_pasid_mapping_pasid, 192 .get_atc_vmid_pasid_mapping_valid = get_atc_vmid_pasid_mapping_valid, 193 .get_fw_version = get_fw_version, 194 .set_scratch_backing_va = set_scratch_backing_va, 195 .get_tile_config = get_tile_config, 196 .set_vm_context_page_table_base = set_vm_context_page_table_base, 197 .invalidate_tlbs = invalidate_tlbs, 198 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 199 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg, 200 }; 201 202 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) 203 { 204 return (struct kfd2kgd_calls *)&kfd2kgd; 205 } 206 207 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 208 { 209 return (struct amdgpu_device *)kgd; 210 } 211 212 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 213 uint32_t queue, uint32_t vmid) 214 { 215 struct amdgpu_device *adev = get_amdgpu_device(kgd); 216 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 217 218 mutex_lock(&adev->srbm_mutex); 219 WREG32(mmSRBM_GFX_CNTL, value); 220 } 221 222 static void unlock_srbm(struct kgd_dev *kgd) 223 { 224 struct amdgpu_device *adev = get_amdgpu_device(kgd); 225 226 WREG32(mmSRBM_GFX_CNTL, 0); 227 mutex_unlock(&adev->srbm_mutex); 228 } 229 230 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 231 uint32_t queue_id) 232 { 233 struct amdgpu_device *adev = get_amdgpu_device(kgd); 234 235 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 236 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 237 238 lock_srbm(kgd, mec, pipe, queue_id, 0); 239 } 240 241 static void release_queue(struct kgd_dev *kgd) 242 { 243 unlock_srbm(kgd); 244 } 245 246 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 247 uint32_t sh_mem_config, 248 uint32_t sh_mem_ape1_base, 249 uint32_t sh_mem_ape1_limit, 250 uint32_t sh_mem_bases) 251 { 252 struct amdgpu_device *adev = get_amdgpu_device(kgd); 253 254 lock_srbm(kgd, 0, 0, 0, vmid); 255 256 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 257 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 258 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 259 WREG32(mmSH_MEM_BASES, sh_mem_bases); 260 261 unlock_srbm(kgd); 262 } 263 264 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 265 unsigned int vmid) 266 { 267 struct amdgpu_device *adev = get_amdgpu_device(kgd); 268 269 /* 270 * We have to assume that there is no outstanding mapping. 271 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 272 * a mapping is in progress or because a mapping finished and the 273 * SW cleared it. So the protocol is to always wait & clear. 274 */ 275 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 276 ATC_VMID0_PASID_MAPPING__VALID_MASK; 277 278 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 279 280 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 281 cpu_relax(); 282 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 283 284 /* Mapping vmid to pasid also for IH block */ 285 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 286 287 return 0; 288 } 289 290 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 291 { 292 struct amdgpu_device *adev = get_amdgpu_device(kgd); 293 uint32_t mec; 294 uint32_t pipe; 295 296 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 297 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 298 299 lock_srbm(kgd, mec, pipe, 0, 0); 300 301 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 302 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 303 304 unlock_srbm(kgd); 305 306 return 0; 307 } 308 309 static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m) 310 { 311 uint32_t retval; 312 313 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 314 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; 315 316 pr_debug("kfd: sdma base address: 0x%x\n", retval); 317 318 return retval; 319 } 320 321 static inline struct cik_mqd *get_mqd(void *mqd) 322 { 323 return (struct cik_mqd *)mqd; 324 } 325 326 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 327 { 328 return (struct cik_sdma_rlc_registers *)mqd; 329 } 330 331 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 332 uint32_t queue_id, uint32_t __user *wptr, 333 uint32_t wptr_shift, uint32_t wptr_mask, 334 struct mm_struct *mm) 335 { 336 struct amdgpu_device *adev = get_amdgpu_device(kgd); 337 struct cik_mqd *m; 338 uint32_t *mqd_hqd; 339 uint32_t reg, wptr_val, data; 340 bool valid_wptr = false; 341 342 m = get_mqd(mqd); 343 344 acquire_queue(kgd, pipe_id, queue_id); 345 346 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */ 347 mqd_hqd = &m->cp_mqd_base_addr_lo; 348 349 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) 350 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 351 352 /* Copy userspace write pointer value to register. 353 * Activate doorbell logic to monitor subsequent changes. 354 */ 355 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 356 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 357 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 358 359 /* read_user_ptr may take the mm->mmap_sem. 360 * release srbm_mutex to avoid circular dependency between 361 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 362 */ 363 release_queue(kgd); 364 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 365 acquire_queue(kgd, pipe_id, queue_id); 366 if (valid_wptr) 367 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 368 369 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 370 WREG32(mmCP_HQD_ACTIVE, data); 371 372 release_queue(kgd); 373 374 return 0; 375 } 376 377 static int kgd_hqd_dump(struct kgd_dev *kgd, 378 uint32_t pipe_id, uint32_t queue_id, 379 uint32_t (**dump)[2], uint32_t *n_regs) 380 { 381 struct amdgpu_device *adev = get_amdgpu_device(kgd); 382 uint32_t i = 0, reg; 383 #define HQD_N_REGS (35+4) 384 #define DUMP_REG(addr) do { \ 385 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 386 break; \ 387 (*dump)[i][0] = (addr) << 2; \ 388 (*dump)[i++][1] = RREG32(addr); \ 389 } while (0) 390 391 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 392 if (*dump == NULL) 393 return -ENOMEM; 394 395 acquire_queue(kgd, pipe_id, queue_id); 396 397 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 398 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 399 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 400 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 401 402 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) 403 DUMP_REG(reg); 404 405 release_queue(kgd); 406 407 WARN_ON_ONCE(i != HQD_N_REGS); 408 *n_regs = i; 409 410 return 0; 411 } 412 413 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 414 uint32_t __user *wptr, struct mm_struct *mm) 415 { 416 struct amdgpu_device *adev = get_amdgpu_device(kgd); 417 struct cik_sdma_rlc_registers *m; 418 unsigned long end_jiffies; 419 uint32_t sdma_base_addr; 420 uint32_t data; 421 422 m = get_sdma_mqd(mqd); 423 sdma_base_addr = get_sdma_base_addr(m); 424 425 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 426 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 427 428 end_jiffies = msecs_to_jiffies(2000) + jiffies; 429 while (true) { 430 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 431 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 432 break; 433 if (time_after(jiffies, end_jiffies)) 434 return -ETIME; 435 usleep_range(500, 1000); 436 } 437 if (m->sdma_engine_id) { 438 data = RREG32(mmSDMA1_GFX_CONTEXT_CNTL); 439 data = REG_SET_FIELD(data, SDMA1_GFX_CONTEXT_CNTL, 440 RESUME_CTX, 0); 441 WREG32(mmSDMA1_GFX_CONTEXT_CNTL, data); 442 } else { 443 data = RREG32(mmSDMA0_GFX_CONTEXT_CNTL); 444 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 445 RESUME_CTX, 0); 446 WREG32(mmSDMA0_GFX_CONTEXT_CNTL, data); 447 } 448 449 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL, 450 ENABLE, 1); 451 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 452 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdma_rlc_rb_rptr); 453 454 if (read_user_wptr(mm, wptr, data)) 455 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, data); 456 else 457 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 458 m->sdma_rlc_rb_rptr); 459 460 WREG32(sdma_base_addr + mmSDMA0_RLC0_VIRTUAL_ADDR, 461 m->sdma_rlc_virtual_addr); 462 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); 463 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 464 m->sdma_rlc_rb_base_hi); 465 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 466 m->sdma_rlc_rb_rptr_addr_lo); 467 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 468 m->sdma_rlc_rb_rptr_addr_hi); 469 470 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL, 471 RB_ENABLE, 1); 472 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 473 474 return 0; 475 } 476 477 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 478 uint32_t engine_id, uint32_t queue_id, 479 uint32_t (**dump)[2], uint32_t *n_regs) 480 { 481 struct amdgpu_device *adev = get_amdgpu_device(kgd); 482 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 483 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; 484 uint32_t i = 0, reg; 485 #undef HQD_N_REGS 486 #define HQD_N_REGS (19+4) 487 488 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 489 if (*dump == NULL) 490 return -ENOMEM; 491 492 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 493 DUMP_REG(sdma_offset + reg); 494 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 495 reg++) 496 DUMP_REG(sdma_offset + reg); 497 498 WARN_ON_ONCE(i != HQD_N_REGS); 499 *n_regs = i; 500 501 return 0; 502 } 503 504 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 505 uint32_t pipe_id, uint32_t queue_id) 506 { 507 struct amdgpu_device *adev = get_amdgpu_device(kgd); 508 uint32_t act; 509 bool retval = false; 510 uint32_t low, high; 511 512 acquire_queue(kgd, pipe_id, queue_id); 513 act = RREG32(mmCP_HQD_ACTIVE); 514 if (act) { 515 low = lower_32_bits(queue_address >> 8); 516 high = upper_32_bits(queue_address >> 8); 517 518 if (low == RREG32(mmCP_HQD_PQ_BASE) && 519 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 520 retval = true; 521 } 522 release_queue(kgd); 523 return retval; 524 } 525 526 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 527 { 528 struct amdgpu_device *adev = get_amdgpu_device(kgd); 529 struct cik_sdma_rlc_registers *m; 530 uint32_t sdma_base_addr; 531 uint32_t sdma_rlc_rb_cntl; 532 533 m = get_sdma_mqd(mqd); 534 sdma_base_addr = get_sdma_base_addr(m); 535 536 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 537 538 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 539 return true; 540 541 return false; 542 } 543 544 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 545 enum kfd_preempt_type reset_type, 546 unsigned int utimeout, uint32_t pipe_id, 547 uint32_t queue_id) 548 { 549 struct amdgpu_device *adev = get_amdgpu_device(kgd); 550 uint32_t temp; 551 enum hqd_dequeue_request_type type; 552 unsigned long flags, end_jiffies; 553 int retry; 554 555 if (adev->in_gpu_reset) 556 return -EIO; 557 558 acquire_queue(kgd, pipe_id, queue_id); 559 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 560 561 switch (reset_type) { 562 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 563 type = DRAIN_PIPE; 564 break; 565 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 566 type = RESET_WAVES; 567 break; 568 default: 569 type = DRAIN_PIPE; 570 break; 571 } 572 573 /* Workaround: If IQ timer is active and the wait time is close to or 574 * equal to 0, dequeueing is not safe. Wait until either the wait time 575 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 576 * cleared before continuing. Also, ensure wait times are set to at 577 * least 0x3. 578 */ 579 local_irq_save(flags); 580 preempt_disable(); 581 retry = 5000; /* wait for 500 usecs at maximum */ 582 while (true) { 583 temp = RREG32(mmCP_HQD_IQ_TIMER); 584 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 585 pr_debug("HW is processing IQ\n"); 586 goto loop; 587 } 588 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 589 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 590 == 3) /* SEM-rearm is safe */ 591 break; 592 /* Wait time 3 is safe for CP, but our MMIO read/write 593 * time is close to 1 microsecond, so check for 10 to 594 * leave more buffer room 595 */ 596 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 597 >= 10) 598 break; 599 pr_debug("IQ timer is active\n"); 600 } else 601 break; 602 loop: 603 if (!retry) { 604 pr_err("CP HQD IQ timer status time out\n"); 605 break; 606 } 607 ndelay(100); 608 --retry; 609 } 610 retry = 1000; 611 while (true) { 612 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 613 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 614 break; 615 pr_debug("Dequeue request is pending\n"); 616 617 if (!retry) { 618 pr_err("CP HQD dequeue request time out\n"); 619 break; 620 } 621 ndelay(100); 622 --retry; 623 } 624 local_irq_restore(flags); 625 preempt_enable(); 626 627 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 628 629 end_jiffies = (utimeout * HZ / 1000) + jiffies; 630 while (true) { 631 temp = RREG32(mmCP_HQD_ACTIVE); 632 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 633 break; 634 if (time_after(jiffies, end_jiffies)) { 635 pr_err("cp queue preemption time out\n"); 636 release_queue(kgd); 637 return -ETIME; 638 } 639 usleep_range(500, 1000); 640 } 641 642 release_queue(kgd); 643 return 0; 644 } 645 646 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 647 unsigned int utimeout) 648 { 649 struct amdgpu_device *adev = get_amdgpu_device(kgd); 650 struct cik_sdma_rlc_registers *m; 651 uint32_t sdma_base_addr; 652 uint32_t temp; 653 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 654 655 m = get_sdma_mqd(mqd); 656 sdma_base_addr = get_sdma_base_addr(m); 657 658 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 659 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 660 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 661 662 while (true) { 663 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 664 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 665 break; 666 if (time_after(jiffies, end_jiffies)) 667 return -ETIME; 668 usleep_range(500, 1000); 669 } 670 671 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 672 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 673 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 674 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 675 676 m->sdma_rlc_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 677 678 return 0; 679 } 680 681 static int kgd_address_watch_disable(struct kgd_dev *kgd) 682 { 683 struct amdgpu_device *adev = get_amdgpu_device(kgd); 684 union TCP_WATCH_CNTL_BITS cntl; 685 unsigned int i; 686 687 cntl.u32All = 0; 688 689 cntl.bitfields.valid = 0; 690 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; 691 cntl.bitfields.atc = 1; 692 693 /* Turning off this address until we set all the registers */ 694 for (i = 0; i < MAX_WATCH_ADDRESSES; i++) 695 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX + 696 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 697 698 return 0; 699 } 700 701 static int kgd_address_watch_execute(struct kgd_dev *kgd, 702 unsigned int watch_point_id, 703 uint32_t cntl_val, 704 uint32_t addr_hi, 705 uint32_t addr_lo) 706 { 707 struct amdgpu_device *adev = get_amdgpu_device(kgd); 708 union TCP_WATCH_CNTL_BITS cntl; 709 710 cntl.u32All = cntl_val; 711 712 /* Turning off this watch point until we set all the registers */ 713 cntl.bitfields.valid = 0; 714 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 715 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 716 717 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 718 ADDRESS_WATCH_REG_ADDR_HI], addr_hi); 719 720 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 721 ADDRESS_WATCH_REG_ADDR_LO], addr_lo); 722 723 /* Enable the watch point */ 724 cntl.bitfields.valid = 1; 725 726 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 727 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 728 729 return 0; 730 } 731 732 static int kgd_wave_control_execute(struct kgd_dev *kgd, 733 uint32_t gfx_index_val, 734 uint32_t sq_cmd) 735 { 736 struct amdgpu_device *adev = get_amdgpu_device(kgd); 737 uint32_t data; 738 739 mutex_lock(&adev->grbm_idx_mutex); 740 741 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 742 WREG32(mmSQ_CMD, sq_cmd); 743 744 /* Restore the GRBM_GFX_INDEX register */ 745 746 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | 747 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 748 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 749 750 WREG32(mmGRBM_GFX_INDEX, data); 751 752 mutex_unlock(&adev->grbm_idx_mutex); 753 754 return 0; 755 } 756 757 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 758 unsigned int watch_point_id, 759 unsigned int reg_offset) 760 { 761 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; 762 } 763 764 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 765 uint8_t vmid) 766 { 767 uint32_t reg; 768 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 769 770 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 771 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 772 } 773 774 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 775 uint8_t vmid) 776 { 777 uint32_t reg; 778 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 779 780 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 781 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 782 } 783 784 static void set_scratch_backing_va(struct kgd_dev *kgd, 785 uint64_t va, uint32_t vmid) 786 { 787 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 788 789 lock_srbm(kgd, 0, 0, 0, vmid); 790 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 791 unlock_srbm(kgd); 792 } 793 794 static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type) 795 { 796 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 797 const union amdgpu_firmware_header *hdr; 798 799 switch (type) { 800 case KGD_ENGINE_PFP: 801 hdr = (const union amdgpu_firmware_header *) 802 adev->gfx.pfp_fw->data; 803 break; 804 805 case KGD_ENGINE_ME: 806 hdr = (const union amdgpu_firmware_header *) 807 adev->gfx.me_fw->data; 808 break; 809 810 case KGD_ENGINE_CE: 811 hdr = (const union amdgpu_firmware_header *) 812 adev->gfx.ce_fw->data; 813 break; 814 815 case KGD_ENGINE_MEC1: 816 hdr = (const union amdgpu_firmware_header *) 817 adev->gfx.mec_fw->data; 818 break; 819 820 case KGD_ENGINE_MEC2: 821 hdr = (const union amdgpu_firmware_header *) 822 adev->gfx.mec2_fw->data; 823 break; 824 825 case KGD_ENGINE_RLC: 826 hdr = (const union amdgpu_firmware_header *) 827 adev->gfx.rlc_fw->data; 828 break; 829 830 case KGD_ENGINE_SDMA1: 831 hdr = (const union amdgpu_firmware_header *) 832 adev->sdma.instance[0].fw->data; 833 break; 834 835 case KGD_ENGINE_SDMA2: 836 hdr = (const union amdgpu_firmware_header *) 837 adev->sdma.instance[1].fw->data; 838 break; 839 840 default: 841 return 0; 842 } 843 844 if (hdr == NULL) 845 return 0; 846 847 /* Only 12 bit in use*/ 848 return hdr->common.ucode_version; 849 } 850 851 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 852 uint64_t page_table_base) 853 { 854 struct amdgpu_device *adev = get_amdgpu_device(kgd); 855 856 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 857 pr_err("trying to set page table base for wrong VMID\n"); 858 return; 859 } 860 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, 861 lower_32_bits(page_table_base)); 862 } 863 864 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 865 { 866 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 867 int vmid; 868 unsigned int tmp; 869 870 if (adev->in_gpu_reset) 871 return -EIO; 872 873 for (vmid = 0; vmid < 16; vmid++) { 874 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 875 continue; 876 877 tmp = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 878 if ((tmp & ATC_VMID0_PASID_MAPPING__VALID_MASK) && 879 (tmp & ATC_VMID0_PASID_MAPPING__PASID_MASK) == pasid) { 880 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 881 RREG32(mmVM_INVALIDATE_RESPONSE); 882 break; 883 } 884 } 885 886 return 0; 887 } 888 889 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 890 { 891 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 892 893 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 894 pr_err("non kfd vmid\n"); 895 return 0; 896 } 897 898 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid); 899 RREG32(mmVM_INVALIDATE_RESPONSE); 900 return 0; 901 } 902 903 /** 904 * read_vmid_from_vmfault_reg - read vmid from register 905 * 906 * adev: amdgpu_device pointer 907 * @vmid: vmid pointer 908 * read vmid from register (CIK). 909 */ 910 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd) 911 { 912 struct amdgpu_device *adev = get_amdgpu_device(kgd); 913 914 uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 915 916 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 917 } 918