1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include <linux/mmu_context.h> 24 25 #include "amdgpu.h" 26 #include "amdgpu_amdkfd.h" 27 #include "cikd.h" 28 #include "cik_sdma.h" 29 #include "gfx_v7_0.h" 30 #include "gca/gfx_7_2_d.h" 31 #include "gca/gfx_7_2_enum.h" 32 #include "gca/gfx_7_2_sh_mask.h" 33 #include "oss/oss_2_0_d.h" 34 #include "oss/oss_2_0_sh_mask.h" 35 #include "gmc/gmc_7_1_d.h" 36 #include "gmc/gmc_7_1_sh_mask.h" 37 #include "cik_structs.h" 38 39 enum hqd_dequeue_request_type { 40 NO_ACTION = 0, 41 DRAIN_PIPE, 42 RESET_WAVES 43 }; 44 45 enum { 46 MAX_TRAPID = 8, /* 3 bits in the bitfield. */ 47 MAX_WATCH_ADDRESSES = 4 48 }; 49 50 enum { 51 ADDRESS_WATCH_REG_ADDR_HI = 0, 52 ADDRESS_WATCH_REG_ADDR_LO, 53 ADDRESS_WATCH_REG_CNTL, 54 ADDRESS_WATCH_REG_MAX 55 }; 56 57 /* not defined in the CI/KV reg file */ 58 enum { 59 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL, 60 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF, 61 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000, 62 /* extend the mask to 26 bits to match the low address field */ 63 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6, 64 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF 65 }; 66 67 static const uint32_t watchRegs[MAX_WATCH_ADDRESSES * ADDRESS_WATCH_REG_MAX] = { 68 mmTCP_WATCH0_ADDR_H, mmTCP_WATCH0_ADDR_L, mmTCP_WATCH0_CNTL, 69 mmTCP_WATCH1_ADDR_H, mmTCP_WATCH1_ADDR_L, mmTCP_WATCH1_CNTL, 70 mmTCP_WATCH2_ADDR_H, mmTCP_WATCH2_ADDR_L, mmTCP_WATCH2_CNTL, 71 mmTCP_WATCH3_ADDR_H, mmTCP_WATCH3_ADDR_L, mmTCP_WATCH3_CNTL 72 }; 73 74 union TCP_WATCH_CNTL_BITS { 75 struct { 76 uint32_t mask:24; 77 uint32_t vmid:4; 78 uint32_t atc:1; 79 uint32_t mode:2; 80 uint32_t valid:1; 81 } bitfields, bits; 82 uint32_t u32All; 83 signed int i32All; 84 float f32All; 85 }; 86 87 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 88 { 89 return (struct amdgpu_device *)kgd; 90 } 91 92 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 93 uint32_t queue, uint32_t vmid) 94 { 95 struct amdgpu_device *adev = get_amdgpu_device(kgd); 96 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue); 97 98 mutex_lock(&adev->srbm_mutex); 99 WREG32(mmSRBM_GFX_CNTL, value); 100 } 101 102 static void unlock_srbm(struct kgd_dev *kgd) 103 { 104 struct amdgpu_device *adev = get_amdgpu_device(kgd); 105 106 WREG32(mmSRBM_GFX_CNTL, 0); 107 mutex_unlock(&adev->srbm_mutex); 108 } 109 110 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 111 uint32_t queue_id) 112 { 113 struct amdgpu_device *adev = get_amdgpu_device(kgd); 114 115 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 116 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 117 118 lock_srbm(kgd, mec, pipe, queue_id, 0); 119 } 120 121 static void release_queue(struct kgd_dev *kgd) 122 { 123 unlock_srbm(kgd); 124 } 125 126 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 127 uint32_t sh_mem_config, 128 uint32_t sh_mem_ape1_base, 129 uint32_t sh_mem_ape1_limit, 130 uint32_t sh_mem_bases) 131 { 132 struct amdgpu_device *adev = get_amdgpu_device(kgd); 133 134 lock_srbm(kgd, 0, 0, 0, vmid); 135 136 WREG32(mmSH_MEM_CONFIG, sh_mem_config); 137 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base); 138 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit); 139 WREG32(mmSH_MEM_BASES, sh_mem_bases); 140 141 unlock_srbm(kgd); 142 } 143 144 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 145 unsigned int vmid) 146 { 147 struct amdgpu_device *adev = get_amdgpu_device(kgd); 148 149 /* 150 * We have to assume that there is no outstanding mapping. 151 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 152 * a mapping is in progress or because a mapping finished and the 153 * SW cleared it. So the protocol is to always wait & clear. 154 */ 155 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 156 ATC_VMID0_PASID_MAPPING__VALID_MASK; 157 158 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping); 159 160 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid))) 161 cpu_relax(); 162 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid); 163 164 /* Mapping vmid to pasid also for IH block */ 165 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping); 166 167 return 0; 168 } 169 170 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 171 { 172 struct amdgpu_device *adev = get_amdgpu_device(kgd); 173 uint32_t mec; 174 uint32_t pipe; 175 176 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 177 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 178 179 lock_srbm(kgd, mec, pipe, 0, 0); 180 181 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 182 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 183 184 unlock_srbm(kgd); 185 186 return 0; 187 } 188 189 static inline uint32_t get_sdma_rlc_reg_offset(struct cik_sdma_rlc_registers *m) 190 { 191 uint32_t retval; 192 193 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + 194 m->sdma_queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; 195 196 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", 197 m->sdma_engine_id, m->sdma_queue_id, retval); 198 199 return retval; 200 } 201 202 static inline struct cik_mqd *get_mqd(void *mqd) 203 { 204 return (struct cik_mqd *)mqd; 205 } 206 207 static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) 208 { 209 return (struct cik_sdma_rlc_registers *)mqd; 210 } 211 212 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 213 uint32_t queue_id, uint32_t __user *wptr, 214 uint32_t wptr_shift, uint32_t wptr_mask, 215 struct mm_struct *mm) 216 { 217 struct amdgpu_device *adev = get_amdgpu_device(kgd); 218 struct cik_mqd *m; 219 uint32_t *mqd_hqd; 220 uint32_t reg, wptr_val, data; 221 bool valid_wptr = false; 222 223 m = get_mqd(mqd); 224 225 acquire_queue(kgd, pipe_id, queue_id); 226 227 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_MQD_CONTROL. */ 228 mqd_hqd = &m->cp_mqd_base_addr_lo; 229 230 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) 231 WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]); 232 233 /* Copy userspace write pointer value to register. 234 * Activate doorbell logic to monitor subsequent changes. 235 */ 236 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 237 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 238 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data); 239 240 /* read_user_ptr may take the mm->mmap_sem. 241 * release srbm_mutex to avoid circular dependency between 242 * srbm_mutex->mm_sem->reservation_ww_class_mutex->srbm_mutex. 243 */ 244 release_queue(kgd); 245 valid_wptr = read_user_wptr(mm, wptr, wptr_val); 246 acquire_queue(kgd, pipe_id, queue_id); 247 if (valid_wptr) 248 WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask); 249 250 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 251 WREG32(mmCP_HQD_ACTIVE, data); 252 253 release_queue(kgd); 254 255 return 0; 256 } 257 258 static int kgd_hqd_dump(struct kgd_dev *kgd, 259 uint32_t pipe_id, uint32_t queue_id, 260 uint32_t (**dump)[2], uint32_t *n_regs) 261 { 262 struct amdgpu_device *adev = get_amdgpu_device(kgd); 263 uint32_t i = 0, reg; 264 #define HQD_N_REGS (35+4) 265 #define DUMP_REG(addr) do { \ 266 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 267 break; \ 268 (*dump)[i][0] = (addr) << 2; \ 269 (*dump)[i++][1] = RREG32(addr); \ 270 } while (0) 271 272 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 273 if (*dump == NULL) 274 return -ENOMEM; 275 276 acquire_queue(kgd, pipe_id, queue_id); 277 278 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE0); 279 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE1); 280 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE2); 281 DUMP_REG(mmCOMPUTE_STATIC_THREAD_MGMT_SE3); 282 283 for (reg = mmCP_MQD_BASE_ADDR; reg <= mmCP_MQD_CONTROL; reg++) 284 DUMP_REG(reg); 285 286 release_queue(kgd); 287 288 WARN_ON_ONCE(i != HQD_N_REGS); 289 *n_regs = i; 290 291 return 0; 292 } 293 294 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 295 uint32_t __user *wptr, struct mm_struct *mm) 296 { 297 struct amdgpu_device *adev = get_amdgpu_device(kgd); 298 struct cik_sdma_rlc_registers *m; 299 unsigned long end_jiffies; 300 uint32_t sdma_rlc_reg_offset; 301 uint32_t data; 302 303 m = get_sdma_mqd(mqd); 304 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 305 306 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 307 m->sdma_rlc_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 308 309 end_jiffies = msecs_to_jiffies(2000) + jiffies; 310 while (true) { 311 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 312 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 313 break; 314 if (time_after(jiffies, end_jiffies)) { 315 pr_err("SDMA RLC not idle in %s\n", __func__); 316 return -ETIME; 317 } 318 usleep_range(500, 1000); 319 } 320 321 data = REG_SET_FIELD(m->sdma_rlc_doorbell, SDMA0_RLC0_DOORBELL, 322 ENABLE, 1); 323 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 324 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 325 m->sdma_rlc_rb_rptr); 326 327 if (read_user_wptr(mm, wptr, data)) 328 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data); 329 else 330 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 331 m->sdma_rlc_rb_rptr); 332 333 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR, 334 m->sdma_rlc_virtual_addr); 335 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base); 336 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 337 m->sdma_rlc_rb_base_hi); 338 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 339 m->sdma_rlc_rb_rptr_addr_lo); 340 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 341 m->sdma_rlc_rb_rptr_addr_hi); 342 343 data = REG_SET_FIELD(m->sdma_rlc_rb_cntl, SDMA0_RLC0_RB_CNTL, 344 RB_ENABLE, 1); 345 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 346 347 return 0; 348 } 349 350 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 351 uint32_t engine_id, uint32_t queue_id, 352 uint32_t (**dump)[2], uint32_t *n_regs) 353 { 354 struct amdgpu_device *adev = get_amdgpu_device(kgd); 355 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + 356 queue_id * KFD_CIK_SDMA_QUEUE_OFFSET; 357 uint32_t i = 0, reg; 358 #undef HQD_N_REGS 359 #define HQD_N_REGS (19+4) 360 361 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 362 if (*dump == NULL) 363 return -ENOMEM; 364 365 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 366 DUMP_REG(sdma_offset + reg); 367 for (reg = mmSDMA0_RLC0_VIRTUAL_ADDR; reg <= mmSDMA0_RLC0_WATERMARK; 368 reg++) 369 DUMP_REG(sdma_offset + reg); 370 371 WARN_ON_ONCE(i != HQD_N_REGS); 372 *n_regs = i; 373 374 return 0; 375 } 376 377 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 378 uint32_t pipe_id, uint32_t queue_id) 379 { 380 struct amdgpu_device *adev = get_amdgpu_device(kgd); 381 uint32_t act; 382 bool retval = false; 383 uint32_t low, high; 384 385 acquire_queue(kgd, pipe_id, queue_id); 386 act = RREG32(mmCP_HQD_ACTIVE); 387 if (act) { 388 low = lower_32_bits(queue_address >> 8); 389 high = upper_32_bits(queue_address >> 8); 390 391 if (low == RREG32(mmCP_HQD_PQ_BASE) && 392 high == RREG32(mmCP_HQD_PQ_BASE_HI)) 393 retval = true; 394 } 395 release_queue(kgd); 396 return retval; 397 } 398 399 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 400 { 401 struct amdgpu_device *adev = get_amdgpu_device(kgd); 402 struct cik_sdma_rlc_registers *m; 403 uint32_t sdma_rlc_reg_offset; 404 uint32_t sdma_rlc_rb_cntl; 405 406 m = get_sdma_mqd(mqd); 407 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 408 409 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 410 411 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 412 return true; 413 414 return false; 415 } 416 417 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 418 enum kfd_preempt_type reset_type, 419 unsigned int utimeout, uint32_t pipe_id, 420 uint32_t queue_id) 421 { 422 struct amdgpu_device *adev = get_amdgpu_device(kgd); 423 uint32_t temp; 424 enum hqd_dequeue_request_type type; 425 unsigned long flags, end_jiffies; 426 int retry; 427 428 if (adev->in_gpu_reset) 429 return -EIO; 430 431 acquire_queue(kgd, pipe_id, queue_id); 432 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, 0); 433 434 switch (reset_type) { 435 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 436 type = DRAIN_PIPE; 437 break; 438 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 439 type = RESET_WAVES; 440 break; 441 default: 442 type = DRAIN_PIPE; 443 break; 444 } 445 446 /* Workaround: If IQ timer is active and the wait time is close to or 447 * equal to 0, dequeueing is not safe. Wait until either the wait time 448 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 449 * cleared before continuing. Also, ensure wait times are set to at 450 * least 0x3. 451 */ 452 local_irq_save(flags); 453 preempt_disable(); 454 retry = 5000; /* wait for 500 usecs at maximum */ 455 while (true) { 456 temp = RREG32(mmCP_HQD_IQ_TIMER); 457 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 458 pr_debug("HW is processing IQ\n"); 459 goto loop; 460 } 461 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 462 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 463 == 3) /* SEM-rearm is safe */ 464 break; 465 /* Wait time 3 is safe for CP, but our MMIO read/write 466 * time is close to 1 microsecond, so check for 10 to 467 * leave more buffer room 468 */ 469 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 470 >= 10) 471 break; 472 pr_debug("IQ timer is active\n"); 473 } else 474 break; 475 loop: 476 if (!retry) { 477 pr_err("CP HQD IQ timer status time out\n"); 478 break; 479 } 480 ndelay(100); 481 --retry; 482 } 483 retry = 1000; 484 while (true) { 485 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 486 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 487 break; 488 pr_debug("Dequeue request is pending\n"); 489 490 if (!retry) { 491 pr_err("CP HQD dequeue request time out\n"); 492 break; 493 } 494 ndelay(100); 495 --retry; 496 } 497 local_irq_restore(flags); 498 preempt_enable(); 499 500 WREG32(mmCP_HQD_DEQUEUE_REQUEST, type); 501 502 end_jiffies = (utimeout * HZ / 1000) + jiffies; 503 while (true) { 504 temp = RREG32(mmCP_HQD_ACTIVE); 505 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 506 break; 507 if (time_after(jiffies, end_jiffies)) { 508 pr_err("cp queue preemption time out\n"); 509 release_queue(kgd); 510 return -ETIME; 511 } 512 usleep_range(500, 1000); 513 } 514 515 release_queue(kgd); 516 return 0; 517 } 518 519 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 520 unsigned int utimeout) 521 { 522 struct amdgpu_device *adev = get_amdgpu_device(kgd); 523 struct cik_sdma_rlc_registers *m; 524 uint32_t sdma_rlc_reg_offset; 525 uint32_t temp; 526 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 527 528 m = get_sdma_mqd(mqd); 529 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(m); 530 531 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 532 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 533 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 534 535 while (true) { 536 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 537 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 538 break; 539 if (time_after(jiffies, end_jiffies)) { 540 pr_err("SDMA RLC not idle in %s\n", __func__); 541 return -ETIME; 542 } 543 usleep_range(500, 1000); 544 } 545 546 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 547 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 548 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 549 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 550 551 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 552 553 return 0; 554 } 555 556 static int kgd_address_watch_disable(struct kgd_dev *kgd) 557 { 558 struct amdgpu_device *adev = get_amdgpu_device(kgd); 559 union TCP_WATCH_CNTL_BITS cntl; 560 unsigned int i; 561 562 cntl.u32All = 0; 563 564 cntl.bitfields.valid = 0; 565 cntl.bitfields.mask = ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK; 566 cntl.bitfields.atc = 1; 567 568 /* Turning off this address until we set all the registers */ 569 for (i = 0; i < MAX_WATCH_ADDRESSES; i++) 570 WREG32(watchRegs[i * ADDRESS_WATCH_REG_MAX + 571 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 572 573 return 0; 574 } 575 576 static int kgd_address_watch_execute(struct kgd_dev *kgd, 577 unsigned int watch_point_id, 578 uint32_t cntl_val, 579 uint32_t addr_hi, 580 uint32_t addr_lo) 581 { 582 struct amdgpu_device *adev = get_amdgpu_device(kgd); 583 union TCP_WATCH_CNTL_BITS cntl; 584 585 cntl.u32All = cntl_val; 586 587 /* Turning off this watch point until we set all the registers */ 588 cntl.bitfields.valid = 0; 589 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 590 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 591 592 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 593 ADDRESS_WATCH_REG_ADDR_HI], addr_hi); 594 595 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 596 ADDRESS_WATCH_REG_ADDR_LO], addr_lo); 597 598 /* Enable the watch point */ 599 cntl.bitfields.valid = 1; 600 601 WREG32(watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + 602 ADDRESS_WATCH_REG_CNTL], cntl.u32All); 603 604 return 0; 605 } 606 607 static int kgd_wave_control_execute(struct kgd_dev *kgd, 608 uint32_t gfx_index_val, 609 uint32_t sq_cmd) 610 { 611 struct amdgpu_device *adev = get_amdgpu_device(kgd); 612 uint32_t data; 613 614 mutex_lock(&adev->grbm_idx_mutex); 615 616 WREG32(mmGRBM_GFX_INDEX, gfx_index_val); 617 WREG32(mmSQ_CMD, sq_cmd); 618 619 /* Restore the GRBM_GFX_INDEX register */ 620 621 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | 622 GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | 623 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK; 624 625 WREG32(mmGRBM_GFX_INDEX, data); 626 627 mutex_unlock(&adev->grbm_idx_mutex); 628 629 return 0; 630 } 631 632 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 633 unsigned int watch_point_id, 634 unsigned int reg_offset) 635 { 636 return watchRegs[watch_point_id * ADDRESS_WATCH_REG_MAX + reg_offset]; 637 } 638 639 static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 640 uint8_t vmid, uint16_t *p_pasid) 641 { 642 uint32_t value; 643 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 644 645 value = RREG32(mmATC_VMID0_PASID_MAPPING + vmid); 646 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 647 648 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 649 } 650 651 static void set_scratch_backing_va(struct kgd_dev *kgd, 652 uint64_t va, uint32_t vmid) 653 { 654 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 655 656 lock_srbm(kgd, 0, 0, 0, vmid); 657 WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va); 658 unlock_srbm(kgd); 659 } 660 661 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 662 uint64_t page_table_base) 663 { 664 struct amdgpu_device *adev = get_amdgpu_device(kgd); 665 666 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 667 pr_err("trying to set page table base for wrong VMID\n"); 668 return; 669 } 670 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8, 671 lower_32_bits(page_table_base)); 672 } 673 674 /** 675 * read_vmid_from_vmfault_reg - read vmid from register 676 * 677 * adev: amdgpu_device pointer 678 * @vmid: vmid pointer 679 * read vmid from register (CIK). 680 */ 681 static uint32_t read_vmid_from_vmfault_reg(struct kgd_dev *kgd) 682 { 683 struct amdgpu_device *adev = get_amdgpu_device(kgd); 684 685 uint32_t status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS); 686 687 return REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID); 688 } 689 690 const struct kfd2kgd_calls gfx_v7_kfd2kgd = { 691 .program_sh_mem_settings = kgd_program_sh_mem_settings, 692 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 693 .init_interrupts = kgd_init_interrupts, 694 .hqd_load = kgd_hqd_load, 695 .hqd_sdma_load = kgd_hqd_sdma_load, 696 .hqd_dump = kgd_hqd_dump, 697 .hqd_sdma_dump = kgd_hqd_sdma_dump, 698 .hqd_is_occupied = kgd_hqd_is_occupied, 699 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 700 .hqd_destroy = kgd_hqd_destroy, 701 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 702 .address_watch_disable = kgd_address_watch_disable, 703 .address_watch_execute = kgd_address_watch_execute, 704 .wave_control_execute = kgd_wave_control_execute, 705 .address_watch_get_offset = kgd_address_watch_get_offset, 706 .get_atc_vmid_pasid_mapping_info = get_atc_vmid_pasid_mapping_info, 707 .set_scratch_backing_va = set_scratch_backing_va, 708 .set_vm_context_page_table_base = set_vm_context_page_table_base, 709 .read_vmid_from_vmfault_reg = read_vmid_from_vmfault_reg, 710 }; 711