1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include <linux/mmu_context.h> 23 #include "amdgpu.h" 24 #include "amdgpu_amdkfd.h" 25 #include "gc/gc_10_1_0_offset.h" 26 #include "gc/gc_10_1_0_sh_mask.h" 27 #include "navi10_enum.h" 28 #include "athub/athub_2_0_0_offset.h" 29 #include "athub/athub_2_0_0_sh_mask.h" 30 #include "oss/osssys_5_0_0_offset.h" 31 #include "oss/osssys_5_0_0_sh_mask.h" 32 #include "soc15_common.h" 33 #include "v10_structs.h" 34 #include "nv.h" 35 #include "nvd.h" 36 #include "gfxhub_v2_0.h" 37 38 enum hqd_dequeue_request_type { 39 NO_ACTION = 0, 40 DRAIN_PIPE, 41 RESET_WAVES, 42 SAVE_WAVES 43 }; 44 45 /* Because of REG_GET_FIELD() being used, we put this function in the 46 * asic specific file. 47 */ 48 static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 49 struct tile_config *config) 50 { 51 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 52 53 config->gb_addr_config = adev->gfx.config.gb_addr_config; 54 #if 0 55 /* TODO - confirm REG_GET_FIELD x2, should be OK as is... but 56 * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu 57 * changes commented out related code, doing the same here for now but 58 * need to sync with Ken et al 59 */ 60 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 61 MC_ARB_RAMCFG, NOOFBANK); 62 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 63 MC_ARB_RAMCFG, NOOFRANKS); 64 #endif 65 66 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 67 config->num_tile_configs = 68 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 69 config->macro_tile_config_ptr = 70 adev->gfx.config.macrotile_mode_array; 71 config->num_macro_tile_configs = 72 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 73 74 return 0; 75 } 76 77 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 78 { 79 return (struct amdgpu_device *)kgd; 80 } 81 82 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 83 uint32_t queue, uint32_t vmid) 84 { 85 struct amdgpu_device *adev = get_amdgpu_device(kgd); 86 87 mutex_lock(&adev->srbm_mutex); 88 nv_grbm_select(adev, mec, pipe, queue, vmid); 89 } 90 91 static void unlock_srbm(struct kgd_dev *kgd) 92 { 93 struct amdgpu_device *adev = get_amdgpu_device(kgd); 94 95 nv_grbm_select(adev, 0, 0, 0, 0); 96 mutex_unlock(&adev->srbm_mutex); 97 } 98 99 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 100 uint32_t queue_id) 101 { 102 struct amdgpu_device *adev = get_amdgpu_device(kgd); 103 104 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 105 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 106 107 lock_srbm(kgd, mec, pipe, queue_id, 0); 108 } 109 110 static uint32_t get_queue_mask(struct amdgpu_device *adev, 111 uint32_t pipe_id, uint32_t queue_id) 112 { 113 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 114 queue_id) & 31; 115 116 return ((uint32_t)1) << bit; 117 } 118 119 static void release_queue(struct kgd_dev *kgd) 120 { 121 unlock_srbm(kgd); 122 } 123 124 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 125 uint32_t sh_mem_config, 126 uint32_t sh_mem_ape1_base, 127 uint32_t sh_mem_ape1_limit, 128 uint32_t sh_mem_bases) 129 { 130 struct amdgpu_device *adev = get_amdgpu_device(kgd); 131 132 lock_srbm(kgd, 0, 0, 0, vmid); 133 134 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 135 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 136 /* APE1 no longer exists on GFX9 */ 137 138 unlock_srbm(kgd); 139 } 140 141 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 142 unsigned int vmid) 143 { 144 struct amdgpu_device *adev = get_amdgpu_device(kgd); 145 146 /* 147 * We have to assume that there is no outstanding mapping. 148 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 149 * a mapping is in progress or because a mapping finished 150 * and the SW cleared it. 151 * So the protocol is to always wait & clear. 152 */ 153 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 154 ATC_VMID0_PASID_MAPPING__VALID_MASK; 155 156 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping); 157 158 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); 159 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 160 pasid_mapping); 161 162 #if 0 163 /* TODO: uncomment this code when the hardware support is ready. */ 164 while (!(RREG32(SOC15_REG_OFFSET( 165 ATHUB, 0, 166 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 167 (1U << vmid))) 168 cpu_relax(); 169 170 pr_debug("ATHUB mapping update finished\n"); 171 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 172 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 173 1U << vmid); 174 #endif 175 176 /* Mapping vmid to pasid also for IH block */ 177 pr_debug("update mapping for IH block and mmhub"); 178 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 179 pasid_mapping); 180 181 return 0; 182 } 183 184 /* TODO - RING0 form of field is obsolete, seems to date back to SI 185 * but still works 186 */ 187 188 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 189 { 190 struct amdgpu_device *adev = get_amdgpu_device(kgd); 191 uint32_t mec; 192 uint32_t pipe; 193 194 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 195 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 196 197 lock_srbm(kgd, mec, pipe, 0, 0); 198 199 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 200 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 201 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 202 203 unlock_srbm(kgd); 204 205 return 0; 206 } 207 208 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 209 unsigned int engine_id, 210 unsigned int queue_id) 211 { 212 uint32_t sdma_engine_reg_base[2] = { 213 SOC15_REG_OFFSET(SDMA0, 0, 214 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 215 /* On gfx10, mmSDMA1_xxx registers are defined NOT based 216 * on SDMA1 base address (dw 0x1860) but based on SDMA0 217 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL 218 * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc 219 * below 220 */ 221 SOC15_REG_OFFSET(SDMA1, 0, 222 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL 223 }; 224 225 uint32_t retval = sdma_engine_reg_base[engine_id] 226 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 227 228 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 229 queue_id, retval); 230 231 return retval; 232 } 233 234 #if 0 235 static uint32_t get_watch_base_addr(struct amdgpu_device *adev) 236 { 237 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 238 mmTCP_WATCH0_ADDR_H; 239 240 pr_debug("kfd: reg watch base address: 0x%x\n", retval); 241 242 return retval; 243 } 244 #endif 245 246 static inline struct v10_compute_mqd *get_mqd(void *mqd) 247 { 248 return (struct v10_compute_mqd *)mqd; 249 } 250 251 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 252 { 253 return (struct v10_sdma_mqd *)mqd; 254 } 255 256 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 257 uint32_t queue_id, uint32_t __user *wptr, 258 uint32_t wptr_shift, uint32_t wptr_mask, 259 struct mm_struct *mm) 260 { 261 struct amdgpu_device *adev = get_amdgpu_device(kgd); 262 struct v10_compute_mqd *m; 263 uint32_t *mqd_hqd; 264 uint32_t reg, hqd_base, data; 265 266 m = get_mqd(mqd); 267 268 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id); 269 acquire_queue(kgd, pipe_id, queue_id); 270 271 /* HIQ is set during driver init period with vmid set to 0*/ 272 if (m->cp_hqd_vmid == 0) { 273 uint32_t value, mec, pipe; 274 275 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 276 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 277 278 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 279 mec, pipe, queue_id); 280 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 281 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 282 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 283 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 284 } 285 286 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 287 mqd_hqd = &m->cp_mqd_base_addr_lo; 288 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 289 290 for (reg = hqd_base; 291 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 292 WREG32(reg, mqd_hqd[reg - hqd_base]); 293 294 295 /* Activate doorbell logic before triggering WPTR poll. */ 296 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 297 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 298 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 299 300 if (wptr) { 301 /* Don't read wptr with get_user because the user 302 * context may not be accessible (if this function 303 * runs in a work queue). Instead trigger a one-shot 304 * polling read from memory in the CP. This assumes 305 * that wptr is GPU-accessible in the queue's VMID via 306 * ATC or SVM. WPTR==RPTR before starting the poll so 307 * the CP starts fetching new commands from the right 308 * place. 309 * 310 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 311 * tricky. Assume that the queue didn't overflow. The 312 * number of valid bits in the 32-bit RPTR depends on 313 * the queue size. The remaining bits are taken from 314 * the saved 64-bit WPTR. If the WPTR wrapped, add the 315 * queue size. 316 */ 317 uint32_t queue_size = 318 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 319 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 320 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 321 322 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 323 guessed_wptr += queue_size; 324 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 325 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 326 327 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 328 lower_32_bits(guessed_wptr)); 329 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 330 upper_32_bits(guessed_wptr)); 331 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 332 lower_32_bits((uint64_t)wptr)); 333 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 334 upper_32_bits((uint64_t)wptr)); 335 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, get_queue_mask(adev, pipe_id, queue_id)); 336 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 337 get_queue_mask(adev, pipe_id, queue_id)); 338 } 339 340 /* Start the EOP fetcher */ 341 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 342 REG_SET_FIELD(m->cp_hqd_eop_rptr, 343 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 344 345 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 346 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 347 348 release_queue(kgd); 349 350 return 0; 351 } 352 353 static int kgd_hqd_dump(struct kgd_dev *kgd, 354 uint32_t pipe_id, uint32_t queue_id, 355 uint32_t (**dump)[2], uint32_t *n_regs) 356 { 357 struct amdgpu_device *adev = get_amdgpu_device(kgd); 358 uint32_t i = 0, reg; 359 #define HQD_N_REGS 56 360 #define DUMP_REG(addr) do { \ 361 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 362 break; \ 363 (*dump)[i][0] = (addr) << 2; \ 364 (*dump)[i++][1] = RREG32(addr); \ 365 } while (0) 366 367 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 368 if (*dump == NULL) 369 return -ENOMEM; 370 371 acquire_queue(kgd, pipe_id, queue_id); 372 373 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 374 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 375 DUMP_REG(reg); 376 377 release_queue(kgd); 378 379 WARN_ON_ONCE(i != HQD_N_REGS); 380 *n_regs = i; 381 382 return 0; 383 } 384 385 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 386 uint32_t __user *wptr, struct mm_struct *mm) 387 { 388 struct amdgpu_device *adev = get_amdgpu_device(kgd); 389 struct v10_sdma_mqd *m; 390 uint32_t sdma_rlc_reg_offset; 391 unsigned long end_jiffies; 392 uint32_t data; 393 uint64_t data64; 394 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 395 396 m = get_sdma_mqd(mqd); 397 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 398 m->sdma_queue_id); 399 400 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 401 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 402 403 end_jiffies = msecs_to_jiffies(2000) + jiffies; 404 while (true) { 405 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 406 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 407 break; 408 if (time_after(jiffies, end_jiffies)) { 409 pr_err("SDMA RLC not idle in %s\n", __func__); 410 return -ETIME; 411 } 412 usleep_range(500, 1000); 413 } 414 415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 416 m->sdmax_rlcx_doorbell_offset); 417 418 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 419 ENABLE, 1); 420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 421 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 422 m->sdmax_rlcx_rb_rptr); 423 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 424 m->sdmax_rlcx_rb_rptr_hi); 425 426 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 427 if (read_user_wptr(mm, wptr64, data64)) { 428 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 429 lower_32_bits(data64)); 430 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 431 upper_32_bits(data64)); 432 } else { 433 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 434 m->sdmax_rlcx_rb_rptr); 435 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 436 m->sdmax_rlcx_rb_rptr_hi); 437 } 438 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 439 440 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 441 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 442 m->sdmax_rlcx_rb_base_hi); 443 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 444 m->sdmax_rlcx_rb_rptr_addr_lo); 445 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 446 m->sdmax_rlcx_rb_rptr_addr_hi); 447 448 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 449 RB_ENABLE, 1); 450 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 451 452 return 0; 453 } 454 455 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 456 uint32_t engine_id, uint32_t queue_id, 457 uint32_t (**dump)[2], uint32_t *n_regs) 458 { 459 struct amdgpu_device *adev = get_amdgpu_device(kgd); 460 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 461 engine_id, queue_id); 462 uint32_t i = 0, reg; 463 #undef HQD_N_REGS 464 #define HQD_N_REGS (19+6+7+10) 465 466 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 467 if (*dump == NULL) 468 return -ENOMEM; 469 470 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 471 DUMP_REG(sdma_rlc_reg_offset + reg); 472 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 473 DUMP_REG(sdma_rlc_reg_offset + reg); 474 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 475 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 476 DUMP_REG(sdma_rlc_reg_offset + reg); 477 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 478 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 479 DUMP_REG(sdma_rlc_reg_offset + reg); 480 481 WARN_ON_ONCE(i != HQD_N_REGS); 482 *n_regs = i; 483 484 return 0; 485 } 486 487 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 488 uint32_t pipe_id, uint32_t queue_id) 489 { 490 struct amdgpu_device *adev = get_amdgpu_device(kgd); 491 uint32_t act; 492 bool retval = false; 493 uint32_t low, high; 494 495 acquire_queue(kgd, pipe_id, queue_id); 496 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 497 if (act) { 498 low = lower_32_bits(queue_address >> 8); 499 high = upper_32_bits(queue_address >> 8); 500 501 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 502 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 503 retval = true; 504 } 505 release_queue(kgd); 506 return retval; 507 } 508 509 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 510 { 511 struct amdgpu_device *adev = get_amdgpu_device(kgd); 512 struct v10_sdma_mqd *m; 513 uint32_t sdma_rlc_reg_offset; 514 uint32_t sdma_rlc_rb_cntl; 515 516 m = get_sdma_mqd(mqd); 517 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 518 m->sdma_queue_id); 519 520 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 521 522 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 523 return true; 524 525 return false; 526 } 527 528 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 529 enum kfd_preempt_type reset_type, 530 unsigned int utimeout, uint32_t pipe_id, 531 uint32_t queue_id) 532 { 533 struct amdgpu_device *adev = get_amdgpu_device(kgd); 534 enum hqd_dequeue_request_type type; 535 unsigned long end_jiffies; 536 uint32_t temp; 537 struct v10_compute_mqd *m = get_mqd(mqd); 538 539 #if 0 540 unsigned long flags; 541 int retry; 542 #endif 543 544 acquire_queue(kgd, pipe_id, queue_id); 545 546 if (m->cp_hqd_vmid == 0) 547 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 548 549 switch (reset_type) { 550 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 551 type = DRAIN_PIPE; 552 break; 553 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 554 type = RESET_WAVES; 555 break; 556 default: 557 type = DRAIN_PIPE; 558 break; 559 } 560 561 #if 0 /* Is this still needed? */ 562 /* Workaround: If IQ timer is active and the wait time is close to or 563 * equal to 0, dequeueing is not safe. Wait until either the wait time 564 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 565 * cleared before continuing. Also, ensure wait times are set to at 566 * least 0x3. 567 */ 568 local_irq_save(flags); 569 preempt_disable(); 570 retry = 5000; /* wait for 500 usecs at maximum */ 571 while (true) { 572 temp = RREG32(mmCP_HQD_IQ_TIMER); 573 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 574 pr_debug("HW is processing IQ\n"); 575 goto loop; 576 } 577 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 578 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 579 == 3) /* SEM-rearm is safe */ 580 break; 581 /* Wait time 3 is safe for CP, but our MMIO read/write 582 * time is close to 1 microsecond, so check for 10 to 583 * leave more buffer room 584 */ 585 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 586 >= 10) 587 break; 588 pr_debug("IQ timer is active\n"); 589 } else 590 break; 591 loop: 592 if (!retry) { 593 pr_err("CP HQD IQ timer status time out\n"); 594 break; 595 } 596 ndelay(100); 597 --retry; 598 } 599 retry = 1000; 600 while (true) { 601 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 602 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 603 break; 604 pr_debug("Dequeue request is pending\n"); 605 606 if (!retry) { 607 pr_err("CP HQD dequeue request time out\n"); 608 break; 609 } 610 ndelay(100); 611 --retry; 612 } 613 local_irq_restore(flags); 614 preempt_enable(); 615 #endif 616 617 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 618 619 end_jiffies = (utimeout * HZ / 1000) + jiffies; 620 while (true) { 621 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 622 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 623 break; 624 if (time_after(jiffies, end_jiffies)) { 625 pr_err("cp queue preemption time out.\n"); 626 release_queue(kgd); 627 return -ETIME; 628 } 629 usleep_range(500, 1000); 630 } 631 632 release_queue(kgd); 633 return 0; 634 } 635 636 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 637 unsigned int utimeout) 638 { 639 struct amdgpu_device *adev = get_amdgpu_device(kgd); 640 struct v10_sdma_mqd *m; 641 uint32_t sdma_rlc_reg_offset; 642 uint32_t temp; 643 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 644 645 m = get_sdma_mqd(mqd); 646 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 647 m->sdma_queue_id); 648 649 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 650 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 651 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 652 653 while (true) { 654 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 655 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 656 break; 657 if (time_after(jiffies, end_jiffies)) { 658 pr_err("SDMA RLC not idle in %s\n", __func__); 659 return -ETIME; 660 } 661 usleep_range(500, 1000); 662 } 663 664 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 665 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 666 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 667 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 668 669 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 670 m->sdmax_rlcx_rb_rptr_hi = 671 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 672 673 return 0; 674 } 675 676 static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 677 uint8_t vmid, uint16_t *p_pasid) 678 { 679 uint32_t value; 680 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 681 682 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 683 + vmid); 684 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 685 686 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 687 } 688 689 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 690 { 691 signed long r; 692 uint32_t seq; 693 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 694 695 spin_lock(&adev->gfx.kiq.ring_lock); 696 amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 697 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 698 amdgpu_ring_write(ring, 699 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 700 PACKET3_INVALIDATE_TLBS_PASID(pasid)); 701 amdgpu_fence_emit_polling(ring, &seq); 702 amdgpu_ring_commit(ring); 703 spin_unlock(&adev->gfx.kiq.ring_lock); 704 705 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 706 if (r < 1) { 707 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 708 return -ETIME; 709 } 710 711 return 0; 712 } 713 714 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 715 { 716 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 717 int vmid; 718 uint16_t queried_pasid; 719 bool ret; 720 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 721 722 if (amdgpu_emu_mode == 0 && ring->sched.ready) 723 return invalidate_tlbs_with_kiq(adev, pasid); 724 725 for (vmid = 0; vmid < 16; vmid++) { 726 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 727 continue; 728 729 ret = get_atc_vmid_pasid_mapping_info(kgd, vmid, 730 &queried_pasid); 731 if (ret && queried_pasid == pasid) { 732 amdgpu_gmc_flush_gpu_tlb(adev, vmid, 733 AMDGPU_GFXHUB_0, 0); 734 break; 735 } 736 } 737 738 return 0; 739 } 740 741 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 742 { 743 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 744 745 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 746 pr_err("non kfd vmid %d\n", vmid); 747 return 0; 748 } 749 750 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 751 return 0; 752 } 753 754 static int kgd_address_watch_disable(struct kgd_dev *kgd) 755 { 756 return 0; 757 } 758 759 static int kgd_address_watch_execute(struct kgd_dev *kgd, 760 unsigned int watch_point_id, 761 uint32_t cntl_val, 762 uint32_t addr_hi, 763 uint32_t addr_lo) 764 { 765 return 0; 766 } 767 768 static int kgd_wave_control_execute(struct kgd_dev *kgd, 769 uint32_t gfx_index_val, 770 uint32_t sq_cmd) 771 { 772 struct amdgpu_device *adev = get_amdgpu_device(kgd); 773 uint32_t data = 0; 774 775 mutex_lock(&adev->grbm_idx_mutex); 776 777 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 778 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 779 780 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 781 INSTANCE_BROADCAST_WRITES, 1); 782 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 783 SA_BROADCAST_WRITES, 1); 784 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 785 SE_BROADCAST_WRITES, 1); 786 787 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 788 mutex_unlock(&adev->grbm_idx_mutex); 789 790 return 0; 791 } 792 793 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 794 unsigned int watch_point_id, 795 unsigned int reg_offset) 796 { 797 return 0; 798 } 799 800 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 801 uint64_t page_table_base) 802 { 803 struct amdgpu_device *adev = get_amdgpu_device(kgd); 804 805 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 806 pr_err("trying to set page table base for wrong VMID %u\n", 807 vmid); 808 return; 809 } 810 811 /* SDMA is on gfxhub as well for Navi1* series */ 812 gfxhub_v2_0_setup_vm_pt_regs(adev, vmid, page_table_base); 813 } 814 815 const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 816 .program_sh_mem_settings = kgd_program_sh_mem_settings, 817 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 818 .init_interrupts = kgd_init_interrupts, 819 .hqd_load = kgd_hqd_load, 820 .hqd_sdma_load = kgd_hqd_sdma_load, 821 .hqd_dump = kgd_hqd_dump, 822 .hqd_sdma_dump = kgd_hqd_sdma_dump, 823 .hqd_is_occupied = kgd_hqd_is_occupied, 824 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 825 .hqd_destroy = kgd_hqd_destroy, 826 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 827 .address_watch_disable = kgd_address_watch_disable, 828 .address_watch_execute = kgd_address_watch_execute, 829 .wave_control_execute = kgd_wave_control_execute, 830 .address_watch_get_offset = kgd_address_watch_get_offset, 831 .get_atc_vmid_pasid_mapping_info = 832 get_atc_vmid_pasid_mapping_info, 833 .get_tile_config = amdgpu_amdkfd_get_tile_config, 834 .set_vm_context_page_table_base = set_vm_context_page_table_base, 835 .invalidate_tlbs = invalidate_tlbs, 836 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 837 .get_hive_id = amdgpu_amdkfd_get_hive_id, 838 }; 839