1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "amdgpu.h" 23 #include "amdgpu_amdkfd.h" 24 #include "gc/gc_10_1_0_offset.h" 25 #include "gc/gc_10_1_0_sh_mask.h" 26 #include "navi10_enum.h" 27 #include "athub/athub_2_0_0_offset.h" 28 #include "athub/athub_2_0_0_sh_mask.h" 29 #include "oss/osssys_5_0_0_offset.h" 30 #include "oss/osssys_5_0_0_sh_mask.h" 31 #include "soc15_common.h" 32 #include "v10_structs.h" 33 #include "nv.h" 34 #include "nvd.h" 35 36 enum hqd_dequeue_request_type { 37 NO_ACTION = 0, 38 DRAIN_PIPE, 39 RESET_WAVES, 40 SAVE_WAVES 41 }; 42 43 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 44 { 45 return (struct amdgpu_device *)kgd; 46 } 47 48 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 49 uint32_t queue, uint32_t vmid) 50 { 51 struct amdgpu_device *adev = get_amdgpu_device(kgd); 52 53 mutex_lock(&adev->srbm_mutex); 54 nv_grbm_select(adev, mec, pipe, queue, vmid); 55 } 56 57 static void unlock_srbm(struct kgd_dev *kgd) 58 { 59 struct amdgpu_device *adev = get_amdgpu_device(kgd); 60 61 nv_grbm_select(adev, 0, 0, 0, 0); 62 mutex_unlock(&adev->srbm_mutex); 63 } 64 65 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 66 uint32_t queue_id) 67 { 68 struct amdgpu_device *adev = get_amdgpu_device(kgd); 69 70 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 71 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 72 73 lock_srbm(kgd, mec, pipe, queue_id, 0); 74 } 75 76 static uint64_t get_queue_mask(struct amdgpu_device *adev, 77 uint32_t pipe_id, uint32_t queue_id) 78 { 79 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + 80 queue_id; 81 82 return 1ull << bit; 83 } 84 85 static void release_queue(struct kgd_dev *kgd) 86 { 87 unlock_srbm(kgd); 88 } 89 90 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 91 uint32_t sh_mem_config, 92 uint32_t sh_mem_ape1_base, 93 uint32_t sh_mem_ape1_limit, 94 uint32_t sh_mem_bases) 95 { 96 struct amdgpu_device *adev = get_amdgpu_device(kgd); 97 98 lock_srbm(kgd, 0, 0, 0, vmid); 99 100 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 101 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 102 /* APE1 no longer exists on GFX9 */ 103 104 unlock_srbm(kgd); 105 } 106 107 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, u32 pasid, 108 unsigned int vmid) 109 { 110 struct amdgpu_device *adev = get_amdgpu_device(kgd); 111 112 /* 113 * We have to assume that there is no outstanding mapping. 114 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 115 * a mapping is in progress or because a mapping finished 116 * and the SW cleared it. 117 * So the protocol is to always wait & clear. 118 */ 119 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 120 ATC_VMID0_PASID_MAPPING__VALID_MASK; 121 122 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping); 123 124 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); 125 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 126 pasid_mapping); 127 128 #if 0 129 /* TODO: uncomment this code when the hardware support is ready. */ 130 while (!(RREG32(SOC15_REG_OFFSET( 131 ATHUB, 0, 132 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 133 (1U << vmid))) 134 cpu_relax(); 135 136 pr_debug("ATHUB mapping update finished\n"); 137 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 138 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 139 1U << vmid); 140 #endif 141 142 /* Mapping vmid to pasid also for IH block */ 143 pr_debug("update mapping for IH block and mmhub"); 144 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 145 pasid_mapping); 146 147 return 0; 148 } 149 150 /* TODO - RING0 form of field is obsolete, seems to date back to SI 151 * but still works 152 */ 153 154 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 155 { 156 struct amdgpu_device *adev = get_amdgpu_device(kgd); 157 uint32_t mec; 158 uint32_t pipe; 159 160 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 161 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 162 163 lock_srbm(kgd, mec, pipe, 0, 0); 164 165 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 166 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 167 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 168 169 unlock_srbm(kgd); 170 171 return 0; 172 } 173 174 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 175 unsigned int engine_id, 176 unsigned int queue_id) 177 { 178 uint32_t sdma_engine_reg_base[2] = { 179 SOC15_REG_OFFSET(SDMA0, 0, 180 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 181 /* On gfx10, mmSDMA1_xxx registers are defined NOT based 182 * on SDMA1 base address (dw 0x1860) but based on SDMA0 183 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL 184 * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc 185 * below 186 */ 187 SOC15_REG_OFFSET(SDMA1, 0, 188 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL 189 }; 190 191 uint32_t retval = sdma_engine_reg_base[engine_id] 192 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 193 194 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 195 queue_id, retval); 196 197 return retval; 198 } 199 200 #if 0 201 static uint32_t get_watch_base_addr(struct amdgpu_device *adev) 202 { 203 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 204 mmTCP_WATCH0_ADDR_H; 205 206 pr_debug("kfd: reg watch base address: 0x%x\n", retval); 207 208 return retval; 209 } 210 #endif 211 212 static inline struct v10_compute_mqd *get_mqd(void *mqd) 213 { 214 return (struct v10_compute_mqd *)mqd; 215 } 216 217 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 218 { 219 return (struct v10_sdma_mqd *)mqd; 220 } 221 222 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 223 uint32_t queue_id, uint32_t __user *wptr, 224 uint32_t wptr_shift, uint32_t wptr_mask, 225 struct mm_struct *mm) 226 { 227 struct amdgpu_device *adev = get_amdgpu_device(kgd); 228 struct v10_compute_mqd *m; 229 uint32_t *mqd_hqd; 230 uint32_t reg, hqd_base, data; 231 232 m = get_mqd(mqd); 233 234 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id); 235 acquire_queue(kgd, pipe_id, queue_id); 236 237 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 238 mqd_hqd = &m->cp_mqd_base_addr_lo; 239 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 240 241 for (reg = hqd_base; 242 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 243 WREG32(reg, mqd_hqd[reg - hqd_base]); 244 245 246 /* Activate doorbell logic before triggering WPTR poll. */ 247 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 248 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 249 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 250 251 if (wptr) { 252 /* Don't read wptr with get_user because the user 253 * context may not be accessible (if this function 254 * runs in a work queue). Instead trigger a one-shot 255 * polling read from memory in the CP. This assumes 256 * that wptr is GPU-accessible in the queue's VMID via 257 * ATC or SVM. WPTR==RPTR before starting the poll so 258 * the CP starts fetching new commands from the right 259 * place. 260 * 261 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 262 * tricky. Assume that the queue didn't overflow. The 263 * number of valid bits in the 32-bit RPTR depends on 264 * the queue size. The remaining bits are taken from 265 * the saved 64-bit WPTR. If the WPTR wrapped, add the 266 * queue size. 267 */ 268 uint32_t queue_size = 269 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 270 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 271 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 272 273 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 274 guessed_wptr += queue_size; 275 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 276 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 277 278 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 279 lower_32_bits(guessed_wptr)); 280 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 281 upper_32_bits(guessed_wptr)); 282 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 283 lower_32_bits((uint64_t)wptr)); 284 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 285 upper_32_bits((uint64_t)wptr)); 286 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, 287 (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); 288 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 289 (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); 290 } 291 292 /* Start the EOP fetcher */ 293 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 294 REG_SET_FIELD(m->cp_hqd_eop_rptr, 295 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 296 297 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 298 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 299 300 release_queue(kgd); 301 302 return 0; 303 } 304 305 static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd, 306 uint32_t pipe_id, uint32_t queue_id, 307 uint32_t doorbell_off) 308 { 309 struct amdgpu_device *adev = get_amdgpu_device(kgd); 310 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; 311 struct v10_compute_mqd *m; 312 uint32_t mec, pipe; 313 int r; 314 315 m = get_mqd(mqd); 316 317 acquire_queue(kgd, pipe_id, queue_id); 318 319 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 320 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 321 322 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 323 mec, pipe, queue_id); 324 325 spin_lock(&adev->gfx.kiq.ring_lock); 326 r = amdgpu_ring_alloc(kiq_ring, 7); 327 if (r) { 328 pr_err("Failed to alloc KIQ (%d).\n", r); 329 goto out_unlock; 330 } 331 332 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 333 amdgpu_ring_write(kiq_ring, 334 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 335 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */ 336 PACKET3_MAP_QUEUES_QUEUE(queue_id) | 337 PACKET3_MAP_QUEUES_PIPE(pipe) | 338 PACKET3_MAP_QUEUES_ME((mec - 1)) | 339 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 340 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 341 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */ 342 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 343 amdgpu_ring_write(kiq_ring, 344 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off)); 345 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); 346 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); 347 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); 348 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); 349 amdgpu_ring_commit(kiq_ring); 350 351 out_unlock: 352 spin_unlock(&adev->gfx.kiq.ring_lock); 353 release_queue(kgd); 354 355 return r; 356 } 357 358 static int kgd_hqd_dump(struct kgd_dev *kgd, 359 uint32_t pipe_id, uint32_t queue_id, 360 uint32_t (**dump)[2], uint32_t *n_regs) 361 { 362 struct amdgpu_device *adev = get_amdgpu_device(kgd); 363 uint32_t i = 0, reg; 364 #define HQD_N_REGS 56 365 #define DUMP_REG(addr) do { \ 366 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 367 break; \ 368 (*dump)[i][0] = (addr) << 2; \ 369 (*dump)[i++][1] = RREG32(addr); \ 370 } while (0) 371 372 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 373 if (*dump == NULL) 374 return -ENOMEM; 375 376 acquire_queue(kgd, pipe_id, queue_id); 377 378 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 379 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 380 DUMP_REG(reg); 381 382 release_queue(kgd); 383 384 WARN_ON_ONCE(i != HQD_N_REGS); 385 *n_regs = i; 386 387 return 0; 388 } 389 390 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 391 uint32_t __user *wptr, struct mm_struct *mm) 392 { 393 struct amdgpu_device *adev = get_amdgpu_device(kgd); 394 struct v10_sdma_mqd *m; 395 uint32_t sdma_rlc_reg_offset; 396 unsigned long end_jiffies; 397 uint32_t data; 398 uint64_t data64; 399 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 400 401 m = get_sdma_mqd(mqd); 402 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 403 m->sdma_queue_id); 404 405 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 406 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 407 408 end_jiffies = msecs_to_jiffies(2000) + jiffies; 409 while (true) { 410 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 411 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 412 break; 413 if (time_after(jiffies, end_jiffies)) { 414 pr_err("SDMA RLC not idle in %s\n", __func__); 415 return -ETIME; 416 } 417 usleep_range(500, 1000); 418 } 419 420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 421 m->sdmax_rlcx_doorbell_offset); 422 423 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 424 ENABLE, 1); 425 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 426 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 427 m->sdmax_rlcx_rb_rptr); 428 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 429 m->sdmax_rlcx_rb_rptr_hi); 430 431 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 432 if (read_user_wptr(mm, wptr64, data64)) { 433 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 434 lower_32_bits(data64)); 435 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 436 upper_32_bits(data64)); 437 } else { 438 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 439 m->sdmax_rlcx_rb_rptr); 440 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 441 m->sdmax_rlcx_rb_rptr_hi); 442 } 443 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 444 445 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 446 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 447 m->sdmax_rlcx_rb_base_hi); 448 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 449 m->sdmax_rlcx_rb_rptr_addr_lo); 450 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 451 m->sdmax_rlcx_rb_rptr_addr_hi); 452 453 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 454 RB_ENABLE, 1); 455 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 456 457 return 0; 458 } 459 460 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 461 uint32_t engine_id, uint32_t queue_id, 462 uint32_t (**dump)[2], uint32_t *n_regs) 463 { 464 struct amdgpu_device *adev = get_amdgpu_device(kgd); 465 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 466 engine_id, queue_id); 467 uint32_t i = 0, reg; 468 #undef HQD_N_REGS 469 #define HQD_N_REGS (19+6+7+10) 470 471 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 472 if (*dump == NULL) 473 return -ENOMEM; 474 475 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 476 DUMP_REG(sdma_rlc_reg_offset + reg); 477 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 478 DUMP_REG(sdma_rlc_reg_offset + reg); 479 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 480 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 481 DUMP_REG(sdma_rlc_reg_offset + reg); 482 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 483 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 484 DUMP_REG(sdma_rlc_reg_offset + reg); 485 486 WARN_ON_ONCE(i != HQD_N_REGS); 487 *n_regs = i; 488 489 return 0; 490 } 491 492 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 493 uint32_t pipe_id, uint32_t queue_id) 494 { 495 struct amdgpu_device *adev = get_amdgpu_device(kgd); 496 uint32_t act; 497 bool retval = false; 498 uint32_t low, high; 499 500 acquire_queue(kgd, pipe_id, queue_id); 501 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 502 if (act) { 503 low = lower_32_bits(queue_address >> 8); 504 high = upper_32_bits(queue_address >> 8); 505 506 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 507 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 508 retval = true; 509 } 510 release_queue(kgd); 511 return retval; 512 } 513 514 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 515 { 516 struct amdgpu_device *adev = get_amdgpu_device(kgd); 517 struct v10_sdma_mqd *m; 518 uint32_t sdma_rlc_reg_offset; 519 uint32_t sdma_rlc_rb_cntl; 520 521 m = get_sdma_mqd(mqd); 522 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 523 m->sdma_queue_id); 524 525 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 526 527 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 528 return true; 529 530 return false; 531 } 532 533 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 534 enum kfd_preempt_type reset_type, 535 unsigned int utimeout, uint32_t pipe_id, 536 uint32_t queue_id) 537 { 538 struct amdgpu_device *adev = get_amdgpu_device(kgd); 539 enum hqd_dequeue_request_type type; 540 unsigned long end_jiffies; 541 uint32_t temp; 542 struct v10_compute_mqd *m = get_mqd(mqd); 543 544 if (amdgpu_in_reset(adev)) 545 return -EIO; 546 547 #if 0 548 unsigned long flags; 549 int retry; 550 #endif 551 552 acquire_queue(kgd, pipe_id, queue_id); 553 554 if (m->cp_hqd_vmid == 0) 555 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 556 557 switch (reset_type) { 558 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 559 type = DRAIN_PIPE; 560 break; 561 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 562 type = RESET_WAVES; 563 break; 564 default: 565 type = DRAIN_PIPE; 566 break; 567 } 568 569 #if 0 /* Is this still needed? */ 570 /* Workaround: If IQ timer is active and the wait time is close to or 571 * equal to 0, dequeueing is not safe. Wait until either the wait time 572 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 573 * cleared before continuing. Also, ensure wait times are set to at 574 * least 0x3. 575 */ 576 local_irq_save(flags); 577 preempt_disable(); 578 retry = 5000; /* wait for 500 usecs at maximum */ 579 while (true) { 580 temp = RREG32(mmCP_HQD_IQ_TIMER); 581 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 582 pr_debug("HW is processing IQ\n"); 583 goto loop; 584 } 585 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 586 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 587 == 3) /* SEM-rearm is safe */ 588 break; 589 /* Wait time 3 is safe for CP, but our MMIO read/write 590 * time is close to 1 microsecond, so check for 10 to 591 * leave more buffer room 592 */ 593 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 594 >= 10) 595 break; 596 pr_debug("IQ timer is active\n"); 597 } else 598 break; 599 loop: 600 if (!retry) { 601 pr_err("CP HQD IQ timer status time out\n"); 602 break; 603 } 604 ndelay(100); 605 --retry; 606 } 607 retry = 1000; 608 while (true) { 609 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 610 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 611 break; 612 pr_debug("Dequeue request is pending\n"); 613 614 if (!retry) { 615 pr_err("CP HQD dequeue request time out\n"); 616 break; 617 } 618 ndelay(100); 619 --retry; 620 } 621 local_irq_restore(flags); 622 preempt_enable(); 623 #endif 624 625 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 626 627 end_jiffies = (utimeout * HZ / 1000) + jiffies; 628 while (true) { 629 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 630 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 631 break; 632 if (time_after(jiffies, end_jiffies)) { 633 pr_err("cp queue preemption time out.\n"); 634 release_queue(kgd); 635 return -ETIME; 636 } 637 usleep_range(500, 1000); 638 } 639 640 release_queue(kgd); 641 return 0; 642 } 643 644 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 645 unsigned int utimeout) 646 { 647 struct amdgpu_device *adev = get_amdgpu_device(kgd); 648 struct v10_sdma_mqd *m; 649 uint32_t sdma_rlc_reg_offset; 650 uint32_t temp; 651 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 652 653 m = get_sdma_mqd(mqd); 654 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 655 m->sdma_queue_id); 656 657 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 658 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 659 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 660 661 while (true) { 662 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 663 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 664 break; 665 if (time_after(jiffies, end_jiffies)) { 666 pr_err("SDMA RLC not idle in %s\n", __func__); 667 return -ETIME; 668 } 669 usleep_range(500, 1000); 670 } 671 672 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 673 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 674 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 675 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 676 677 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 678 m->sdmax_rlcx_rb_rptr_hi = 679 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 680 681 return 0; 682 } 683 684 static bool get_atc_vmid_pasid_mapping_info(struct kgd_dev *kgd, 685 uint8_t vmid, uint16_t *p_pasid) 686 { 687 uint32_t value; 688 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 689 690 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 691 + vmid); 692 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 693 694 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 695 } 696 697 static int kgd_address_watch_disable(struct kgd_dev *kgd) 698 { 699 return 0; 700 } 701 702 static int kgd_address_watch_execute(struct kgd_dev *kgd, 703 unsigned int watch_point_id, 704 uint32_t cntl_val, 705 uint32_t addr_hi, 706 uint32_t addr_lo) 707 { 708 return 0; 709 } 710 711 static int kgd_wave_control_execute(struct kgd_dev *kgd, 712 uint32_t gfx_index_val, 713 uint32_t sq_cmd) 714 { 715 struct amdgpu_device *adev = get_amdgpu_device(kgd); 716 uint32_t data = 0; 717 718 mutex_lock(&adev->grbm_idx_mutex); 719 720 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 721 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 722 723 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 724 INSTANCE_BROADCAST_WRITES, 1); 725 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 726 SA_BROADCAST_WRITES, 1); 727 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 728 SE_BROADCAST_WRITES, 1); 729 730 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 731 mutex_unlock(&adev->grbm_idx_mutex); 732 733 return 0; 734 } 735 736 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 737 unsigned int watch_point_id, 738 unsigned int reg_offset) 739 { 740 return 0; 741 } 742 743 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 744 uint64_t page_table_base) 745 { 746 struct amdgpu_device *adev = get_amdgpu_device(kgd); 747 748 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 749 pr_err("trying to set page table base for wrong VMID %u\n", 750 vmid); 751 return; 752 } 753 754 /* SDMA is on gfxhub as well for Navi1* series */ 755 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); 756 } 757 758 const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 759 .program_sh_mem_settings = kgd_program_sh_mem_settings, 760 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 761 .init_interrupts = kgd_init_interrupts, 762 .hqd_load = kgd_hqd_load, 763 .hiq_mqd_load = kgd_hiq_mqd_load, 764 .hqd_sdma_load = kgd_hqd_sdma_load, 765 .hqd_dump = kgd_hqd_dump, 766 .hqd_sdma_dump = kgd_hqd_sdma_dump, 767 .hqd_is_occupied = kgd_hqd_is_occupied, 768 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 769 .hqd_destroy = kgd_hqd_destroy, 770 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 771 .address_watch_disable = kgd_address_watch_disable, 772 .address_watch_execute = kgd_address_watch_execute, 773 .wave_control_execute = kgd_wave_control_execute, 774 .address_watch_get_offset = kgd_address_watch_get_offset, 775 .get_atc_vmid_pasid_mapping_info = 776 get_atc_vmid_pasid_mapping_info, 777 .set_vm_context_page_table_base = set_vm_context_page_table_base, 778 }; 779