1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #undef pr_fmt 23 #define pr_fmt(fmt) "kfd2kgd: " fmt 24 25 #include <linux/module.h> 26 #include <linux/fdtable.h> 27 #include <linux/uaccess.h> 28 #include <linux/firmware.h> 29 #include <linux/mmu_context.h> 30 #include "amdgpu.h" 31 #include "amdgpu_amdkfd.h" 32 #include "amdgpu_ucode.h" 33 #include "soc15_hw_ip.h" 34 #include "gc/gc_10_1_0_offset.h" 35 #include "gc/gc_10_1_0_sh_mask.h" 36 #include "navi10_enum.h" 37 #include "athub/athub_2_0_0_offset.h" 38 #include "athub/athub_2_0_0_sh_mask.h" 39 #include "oss/osssys_5_0_0_offset.h" 40 #include "oss/osssys_5_0_0_sh_mask.h" 41 #include "soc15_common.h" 42 #include "v10_structs.h" 43 #include "nv.h" 44 #include "nvd.h" 45 46 enum hqd_dequeue_request_type { 47 NO_ACTION = 0, 48 DRAIN_PIPE, 49 RESET_WAVES, 50 SAVE_WAVES 51 }; 52 53 /* 54 * Register access functions 55 */ 56 57 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 58 uint32_t sh_mem_config, 59 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit, 60 uint32_t sh_mem_bases); 61 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 62 unsigned int vmid); 63 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id); 64 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 65 uint32_t queue_id, uint32_t __user *wptr, 66 uint32_t wptr_shift, uint32_t wptr_mask, 67 struct mm_struct *mm); 68 static int kgd_hqd_dump(struct kgd_dev *kgd, 69 uint32_t pipe_id, uint32_t queue_id, 70 uint32_t (**dump)[2], uint32_t *n_regs); 71 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 72 uint32_t __user *wptr, struct mm_struct *mm); 73 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 74 uint32_t engine_id, uint32_t queue_id, 75 uint32_t (**dump)[2], uint32_t *n_regs); 76 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 77 uint32_t pipe_id, uint32_t queue_id); 78 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd); 79 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 80 enum kfd_preempt_type reset_type, 81 unsigned int utimeout, uint32_t pipe_id, 82 uint32_t queue_id); 83 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 84 unsigned int utimeout); 85 #if 0 86 static uint32_t get_watch_base_addr(struct amdgpu_device *adev); 87 #endif 88 static int kgd_address_watch_disable(struct kgd_dev *kgd); 89 static int kgd_address_watch_execute(struct kgd_dev *kgd, 90 unsigned int watch_point_id, 91 uint32_t cntl_val, 92 uint32_t addr_hi, 93 uint32_t addr_lo); 94 static int kgd_wave_control_execute(struct kgd_dev *kgd, 95 uint32_t gfx_index_val, 96 uint32_t sq_cmd); 97 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 98 unsigned int watch_point_id, 99 unsigned int reg_offset); 100 101 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 102 uint8_t vmid); 103 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 104 uint8_t vmid); 105 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 106 uint64_t page_table_base); 107 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid); 108 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid); 109 110 /* Because of REG_GET_FIELD() being used, we put this function in the 111 * asic specific file. 112 */ 113 static int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 114 struct tile_config *config) 115 { 116 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 117 118 config->gb_addr_config = adev->gfx.config.gb_addr_config; 119 #if 0 120 /* TODO - confirm REG_GET_FIELD x2, should be OK as is... but 121 * MC_ARB_RAMCFG register doesn't exist on Vega10 - initial amdgpu 122 * changes commented out related code, doing the same here for now but 123 * need to sync with Ken et al 124 */ 125 config->num_banks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 126 MC_ARB_RAMCFG, NOOFBANK); 127 config->num_ranks = REG_GET_FIELD(adev->gfx.config.mc_arb_ramcfg, 128 MC_ARB_RAMCFG, NOOFRANKS); 129 #endif 130 131 config->tile_config_ptr = adev->gfx.config.tile_mode_array; 132 config->num_tile_configs = 133 ARRAY_SIZE(adev->gfx.config.tile_mode_array); 134 config->macro_tile_config_ptr = 135 adev->gfx.config.macrotile_mode_array; 136 config->num_macro_tile_configs = 137 ARRAY_SIZE(adev->gfx.config.macrotile_mode_array); 138 139 return 0; 140 } 141 142 static const struct kfd2kgd_calls kfd2kgd = { 143 .program_sh_mem_settings = kgd_program_sh_mem_settings, 144 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 145 .init_interrupts = kgd_init_interrupts, 146 .hqd_load = kgd_hqd_load, 147 .hqd_sdma_load = kgd_hqd_sdma_load, 148 .hqd_dump = kgd_hqd_dump, 149 .hqd_sdma_dump = kgd_hqd_sdma_dump, 150 .hqd_is_occupied = kgd_hqd_is_occupied, 151 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 152 .hqd_destroy = kgd_hqd_destroy, 153 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 154 .address_watch_disable = kgd_address_watch_disable, 155 .address_watch_execute = kgd_address_watch_execute, 156 .wave_control_execute = kgd_wave_control_execute, 157 .address_watch_get_offset = kgd_address_watch_get_offset, 158 .get_atc_vmid_pasid_mapping_pasid = 159 get_atc_vmid_pasid_mapping_pasid, 160 .get_atc_vmid_pasid_mapping_valid = 161 get_atc_vmid_pasid_mapping_valid, 162 .invalidate_tlbs = invalidate_tlbs, 163 .invalidate_tlbs_vmid = invalidate_tlbs_vmid, 164 .set_vm_context_page_table_base = set_vm_context_page_table_base, 165 .get_tile_config = amdgpu_amdkfd_get_tile_config, 166 }; 167 168 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions() 169 { 170 return (struct kfd2kgd_calls *)&kfd2kgd; 171 } 172 173 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 174 { 175 return (struct amdgpu_device *)kgd; 176 } 177 178 static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe, 179 uint32_t queue, uint32_t vmid) 180 { 181 struct amdgpu_device *adev = get_amdgpu_device(kgd); 182 183 mutex_lock(&adev->srbm_mutex); 184 nv_grbm_select(adev, mec, pipe, queue, vmid); 185 } 186 187 static void unlock_srbm(struct kgd_dev *kgd) 188 { 189 struct amdgpu_device *adev = get_amdgpu_device(kgd); 190 191 nv_grbm_select(adev, 0, 0, 0, 0); 192 mutex_unlock(&adev->srbm_mutex); 193 } 194 195 static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id, 196 uint32_t queue_id) 197 { 198 struct amdgpu_device *adev = get_amdgpu_device(kgd); 199 200 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 201 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 202 203 lock_srbm(kgd, mec, pipe, queue_id, 0); 204 } 205 206 static uint32_t get_queue_mask(struct amdgpu_device *adev, 207 uint32_t pipe_id, uint32_t queue_id) 208 { 209 unsigned int bit = (pipe_id * adev->gfx.mec.num_queue_per_pipe + 210 queue_id) & 31; 211 212 return ((uint32_t)1) << bit; 213 } 214 215 static void release_queue(struct kgd_dev *kgd) 216 { 217 unlock_srbm(kgd); 218 } 219 220 static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid, 221 uint32_t sh_mem_config, 222 uint32_t sh_mem_ape1_base, 223 uint32_t sh_mem_ape1_limit, 224 uint32_t sh_mem_bases) 225 { 226 struct amdgpu_device *adev = get_amdgpu_device(kgd); 227 228 lock_srbm(kgd, 0, 0, 0, vmid); 229 230 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config); 231 WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases); 232 /* APE1 no longer exists on GFX9 */ 233 234 unlock_srbm(kgd); 235 } 236 237 static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid, 238 unsigned int vmid) 239 { 240 struct amdgpu_device *adev = get_amdgpu_device(kgd); 241 242 /* 243 * We have to assume that there is no outstanding mapping. 244 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 245 * a mapping is in progress or because a mapping finished 246 * and the SW cleared it. 247 * So the protocol is to always wait & clear. 248 */ 249 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 250 ATC_VMID0_PASID_MAPPING__VALID_MASK; 251 252 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping); 253 /* 254 * need to do this twice, once for gfx and once for mmhub 255 * for ATC add 16 to VMID for mmhub, for IH different registers. 256 * ATC_VMID0..15 registers are separate from ATC_VMID16..31. 257 */ 258 259 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); 260 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 261 pasid_mapping); 262 263 #if 0 264 /* TODO: uncomment this code when the hardware support is ready. */ 265 while (!(RREG32(SOC15_REG_OFFSET( 266 ATHUB, 0, 267 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 268 (1U << vmid))) 269 cpu_relax(); 270 271 pr_debug("ATHUB mapping update finished\n"); 272 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 273 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 274 1U << vmid); 275 #endif 276 277 /* Mapping vmid to pasid also for IH block */ 278 pr_debug("update mapping for IH block and mmhub"); 279 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 280 pasid_mapping); 281 282 return 0; 283 } 284 285 /* TODO - RING0 form of field is obsolete, seems to date back to SI 286 * but still works 287 */ 288 289 static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id) 290 { 291 struct amdgpu_device *adev = get_amdgpu_device(kgd); 292 uint32_t mec; 293 uint32_t pipe; 294 295 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 296 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 297 298 lock_srbm(kgd, mec, pipe, 0, 0); 299 300 WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL), 301 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 302 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 303 304 unlock_srbm(kgd); 305 306 return 0; 307 } 308 309 static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 310 unsigned int engine_id, 311 unsigned int queue_id) 312 { 313 uint32_t base[2] = { 314 SOC15_REG_OFFSET(SDMA0, 0, 315 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 316 /* On gfx10, mmSDMA1_xxx registers are defined NOT based 317 * on SDMA1 base address (dw 0x1860) but based on SDMA0 318 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL 319 * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc 320 * below 321 */ 322 SOC15_REG_OFFSET(SDMA1, 0, 323 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL 324 }; 325 uint32_t retval; 326 327 retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 328 mmSDMA0_RLC0_RB_CNTL); 329 330 pr_debug("sdma base address: 0x%x\n", retval); 331 332 return retval; 333 } 334 335 #if 0 336 static uint32_t get_watch_base_addr(struct amdgpu_device *adev) 337 { 338 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 339 mmTCP_WATCH0_ADDR_H; 340 341 pr_debug("kfd: reg watch base address: 0x%x\n", retval); 342 343 return retval; 344 } 345 #endif 346 347 static inline struct v10_compute_mqd *get_mqd(void *mqd) 348 { 349 return (struct v10_compute_mqd *)mqd; 350 } 351 352 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 353 { 354 return (struct v10_sdma_mqd *)mqd; 355 } 356 357 static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id, 358 uint32_t queue_id, uint32_t __user *wptr, 359 uint32_t wptr_shift, uint32_t wptr_mask, 360 struct mm_struct *mm) 361 { 362 struct amdgpu_device *adev = get_amdgpu_device(kgd); 363 struct v10_compute_mqd *m; 364 uint32_t *mqd_hqd; 365 uint32_t reg, hqd_base, data; 366 367 m = get_mqd(mqd); 368 369 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id); 370 acquire_queue(kgd, pipe_id, queue_id); 371 372 /* HIQ is set during driver init period with vmid set to 0*/ 373 if (m->cp_hqd_vmid == 0) { 374 uint32_t value, mec, pipe; 375 376 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 377 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 378 379 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 380 mec, pipe, queue_id); 381 value = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS)); 382 value = REG_SET_FIELD(value, RLC_CP_SCHEDULERS, scheduler1, 383 ((mec << 5) | (pipe << 3) | queue_id | 0x80)); 384 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CP_SCHEDULERS), value); 385 } 386 387 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 388 mqd_hqd = &m->cp_mqd_base_addr_lo; 389 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 390 391 for (reg = hqd_base; 392 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 393 WREG32(reg, mqd_hqd[reg - hqd_base]); 394 395 396 /* Activate doorbell logic before triggering WPTR poll. */ 397 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 398 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 399 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data); 400 401 if (wptr) { 402 /* Don't read wptr with get_user because the user 403 * context may not be accessible (if this function 404 * runs in a work queue). Instead trigger a one-shot 405 * polling read from memory in the CP. This assumes 406 * that wptr is GPU-accessible in the queue's VMID via 407 * ATC or SVM. WPTR==RPTR before starting the poll so 408 * the CP starts fetching new commands from the right 409 * place. 410 * 411 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 412 * tricky. Assume that the queue didn't overflow. The 413 * number of valid bits in the 32-bit RPTR depends on 414 * the queue size. The remaining bits are taken from 415 * the saved 64-bit WPTR. If the WPTR wrapped, add the 416 * queue size. 417 */ 418 uint32_t queue_size = 419 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 420 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 421 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 422 423 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 424 guessed_wptr += queue_size; 425 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 426 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 427 428 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO), 429 lower_32_bits(guessed_wptr)); 430 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI), 431 upper_32_bits(guessed_wptr)); 432 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR), 433 lower_32_bits((uint64_t)wptr)); 434 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI), 435 upper_32_bits((uint64_t)wptr)); 436 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, get_queue_mask(adev, pipe_id, queue_id)); 437 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1), 438 get_queue_mask(adev, pipe_id, queue_id)); 439 } 440 441 /* Start the EOP fetcher */ 442 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR), 443 REG_SET_FIELD(m->cp_hqd_eop_rptr, 444 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 445 446 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 447 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data); 448 449 release_queue(kgd); 450 451 return 0; 452 } 453 454 static int kgd_hqd_dump(struct kgd_dev *kgd, 455 uint32_t pipe_id, uint32_t queue_id, 456 uint32_t (**dump)[2], uint32_t *n_regs) 457 { 458 struct amdgpu_device *adev = get_amdgpu_device(kgd); 459 uint32_t i = 0, reg; 460 #define HQD_N_REGS 56 461 #define DUMP_REG(addr) do { \ 462 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 463 break; \ 464 (*dump)[i][0] = (addr) << 2; \ 465 (*dump)[i++][1] = RREG32(addr); \ 466 } while (0) 467 468 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 469 if (*dump == NULL) 470 return -ENOMEM; 471 472 acquire_queue(kgd, pipe_id, queue_id); 473 474 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 475 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 476 DUMP_REG(reg); 477 478 release_queue(kgd); 479 480 WARN_ON_ONCE(i != HQD_N_REGS); 481 *n_regs = i; 482 483 return 0; 484 } 485 486 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 487 uint32_t __user *wptr, struct mm_struct *mm) 488 { 489 struct amdgpu_device *adev = get_amdgpu_device(kgd); 490 struct v10_sdma_mqd *m; 491 uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 492 unsigned long end_jiffies; 493 uint32_t data; 494 uint64_t data64; 495 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 496 497 m = get_sdma_mqd(mqd); 498 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 499 m->sdma_queue_id); 500 pr_debug("sdma load base addr %x for engine %d, queue %d\n", sdma_base_addr, m->sdma_engine_id, m->sdma_queue_id); 501 sdmax_gfx_context_cntl = m->sdma_engine_id ? 502 SOC15_REG_OFFSET(SDMA1, 0, mmSDMA1_GFX_CONTEXT_CNTL) : 503 SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GFX_CONTEXT_CNTL); 504 505 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 506 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 507 508 end_jiffies = msecs_to_jiffies(2000) + jiffies; 509 while (true) { 510 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 511 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 512 break; 513 if (time_after(jiffies, end_jiffies)) 514 return -ETIME; 515 usleep_range(500, 1000); 516 } 517 data = RREG32(sdmax_gfx_context_cntl); 518 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 519 RESUME_CTX, 0); 520 WREG32(sdmax_gfx_context_cntl, data); 521 522 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 523 m->sdmax_rlcx_doorbell_offset); 524 525 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 526 ENABLE, 1); 527 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 528 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 529 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 530 m->sdmax_rlcx_rb_rptr_hi); 531 532 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 533 if (read_user_wptr(mm, wptr64, data64)) { 534 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 535 lower_32_bits(data64)); 536 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 537 upper_32_bits(data64)); 538 } else { 539 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 540 m->sdmax_rlcx_rb_rptr); 541 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 542 m->sdmax_rlcx_rb_rptr_hi); 543 } 544 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 545 546 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 547 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 548 m->sdmax_rlcx_rb_base_hi); 549 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 550 m->sdmax_rlcx_rb_rptr_addr_lo); 551 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 552 m->sdmax_rlcx_rb_rptr_addr_hi); 553 554 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 555 RB_ENABLE, 1); 556 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 557 558 return 0; 559 } 560 561 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 562 uint32_t engine_id, uint32_t queue_id, 563 uint32_t (**dump)[2], uint32_t *n_regs) 564 { 565 struct amdgpu_device *adev = get_amdgpu_device(kgd); 566 uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 567 uint32_t i = 0, reg; 568 #undef HQD_N_REGS 569 #define HQD_N_REGS (19+6+7+10) 570 571 pr_debug("sdma dump engine id %d queue_id %d\n", engine_id, queue_id); 572 pr_debug("sdma base addr %x\n", sdma_base_addr); 573 574 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 575 if (*dump == NULL) 576 return -ENOMEM; 577 578 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 579 DUMP_REG(sdma_base_addr + reg); 580 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 581 DUMP_REG(sdma_base_addr + reg); 582 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 583 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 584 DUMP_REG(sdma_base_addr + reg); 585 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 586 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 587 DUMP_REG(sdma_base_addr + reg); 588 589 WARN_ON_ONCE(i != HQD_N_REGS); 590 *n_regs = i; 591 592 return 0; 593 } 594 595 static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address, 596 uint32_t pipe_id, uint32_t queue_id) 597 { 598 struct amdgpu_device *adev = get_amdgpu_device(kgd); 599 uint32_t act; 600 bool retval = false; 601 uint32_t low, high; 602 603 acquire_queue(kgd, pipe_id, queue_id); 604 act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 605 if (act) { 606 low = lower_32_bits(queue_address >> 8); 607 high = upper_32_bits(queue_address >> 8); 608 609 if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) && 610 high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI))) 611 retval = true; 612 } 613 release_queue(kgd); 614 return retval; 615 } 616 617 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 618 { 619 struct amdgpu_device *adev = get_amdgpu_device(kgd); 620 struct v10_sdma_mqd *m; 621 uint32_t sdma_base_addr; 622 uint32_t sdma_rlc_rb_cntl; 623 624 m = get_sdma_mqd(mqd); 625 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 626 m->sdma_queue_id); 627 628 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 629 630 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 631 return true; 632 633 return false; 634 } 635 636 static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd, 637 enum kfd_preempt_type reset_type, 638 unsigned int utimeout, uint32_t pipe_id, 639 uint32_t queue_id) 640 { 641 struct amdgpu_device *adev = get_amdgpu_device(kgd); 642 enum hqd_dequeue_request_type type; 643 unsigned long end_jiffies; 644 uint32_t temp; 645 struct v10_compute_mqd *m = get_mqd(mqd); 646 647 #if 0 648 unsigned long flags; 649 int retry; 650 #endif 651 652 acquire_queue(kgd, pipe_id, queue_id); 653 654 if (m->cp_hqd_vmid == 0) 655 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 656 657 switch (reset_type) { 658 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 659 type = DRAIN_PIPE; 660 break; 661 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 662 type = RESET_WAVES; 663 break; 664 default: 665 type = DRAIN_PIPE; 666 break; 667 } 668 669 #if 0 /* Is this still needed? */ 670 /* Workaround: If IQ timer is active and the wait time is close to or 671 * equal to 0, dequeueing is not safe. Wait until either the wait time 672 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 673 * cleared before continuing. Also, ensure wait times are set to at 674 * least 0x3. 675 */ 676 local_irq_save(flags); 677 preempt_disable(); 678 retry = 5000; /* wait for 500 usecs at maximum */ 679 while (true) { 680 temp = RREG32(mmCP_HQD_IQ_TIMER); 681 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 682 pr_debug("HW is processing IQ\n"); 683 goto loop; 684 } 685 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 686 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 687 == 3) /* SEM-rearm is safe */ 688 break; 689 /* Wait time 3 is safe for CP, but our MMIO read/write 690 * time is close to 1 microsecond, so check for 10 to 691 * leave more buffer room 692 */ 693 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 694 >= 10) 695 break; 696 pr_debug("IQ timer is active\n"); 697 } else 698 break; 699 loop: 700 if (!retry) { 701 pr_err("CP HQD IQ timer status time out\n"); 702 break; 703 } 704 ndelay(100); 705 --retry; 706 } 707 retry = 1000; 708 while (true) { 709 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 710 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 711 break; 712 pr_debug("Dequeue request is pending\n"); 713 714 if (!retry) { 715 pr_err("CP HQD dequeue request time out\n"); 716 break; 717 } 718 ndelay(100); 719 --retry; 720 } 721 local_irq_restore(flags); 722 preempt_enable(); 723 #endif 724 725 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type); 726 727 end_jiffies = (utimeout * HZ / 1000) + jiffies; 728 while (true) { 729 temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE)); 730 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 731 break; 732 if (time_after(jiffies, end_jiffies)) { 733 pr_err("cp queue preemption time out.\n"); 734 release_queue(kgd); 735 return -ETIME; 736 } 737 usleep_range(500, 1000); 738 } 739 740 release_queue(kgd); 741 return 0; 742 } 743 744 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 745 unsigned int utimeout) 746 { 747 struct amdgpu_device *adev = get_amdgpu_device(kgd); 748 struct v10_sdma_mqd *m; 749 uint32_t sdma_base_addr; 750 uint32_t temp; 751 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 752 753 m = get_sdma_mqd(mqd); 754 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 755 m->sdma_queue_id); 756 757 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 758 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 759 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 760 761 while (true) { 762 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 763 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 764 break; 765 if (time_after(jiffies, end_jiffies)) 766 return -ETIME; 767 usleep_range(500, 1000); 768 } 769 770 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 771 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 772 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 773 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 774 775 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 776 m->sdmax_rlcx_rb_rptr_hi = 777 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 778 779 return 0; 780 } 781 782 static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd, 783 uint8_t vmid) 784 { 785 uint32_t reg; 786 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 787 788 reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 789 + vmid); 790 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK; 791 } 792 793 static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd, 794 uint8_t vmid) 795 { 796 uint32_t reg; 797 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 798 799 reg = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 800 + vmid); 801 return reg & ATC_VMID0_PASID_MAPPING__PASID_MASK; 802 } 803 804 static int invalidate_tlbs_with_kiq(struct amdgpu_device *adev, uint16_t pasid) 805 { 806 signed long r; 807 uint32_t seq; 808 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 809 810 spin_lock(&adev->gfx.kiq.ring_lock); 811 amdgpu_ring_alloc(ring, 12); /* fence + invalidate_tlbs package*/ 812 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0)); 813 amdgpu_ring_write(ring, 814 PACKET3_INVALIDATE_TLBS_DST_SEL(1) | 815 PACKET3_INVALIDATE_TLBS_PASID(pasid)); 816 amdgpu_fence_emit_polling(ring, &seq); 817 amdgpu_ring_commit(ring); 818 spin_unlock(&adev->gfx.kiq.ring_lock); 819 820 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout); 821 if (r < 1) { 822 DRM_ERROR("wait for kiq fence error: %ld.\n", r); 823 return -ETIME; 824 } 825 826 return 0; 827 } 828 829 static int invalidate_tlbs(struct kgd_dev *kgd, uint16_t pasid) 830 { 831 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 832 int vmid; 833 struct amdgpu_ring *ring = &adev->gfx.kiq.ring; 834 835 if (amdgpu_emu_mode == 0 && ring->sched.ready) 836 return invalidate_tlbs_with_kiq(adev, pasid); 837 838 for (vmid = 0; vmid < 16; vmid++) { 839 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) 840 continue; 841 if (get_atc_vmid_pasid_mapping_valid(kgd, vmid)) { 842 if (get_atc_vmid_pasid_mapping_pasid(kgd, vmid) 843 == pasid) { 844 amdgpu_gmc_flush_gpu_tlb(adev, vmid, 845 AMDGPU_GFXHUB_0, 0); 846 break; 847 } 848 } 849 } 850 851 return 0; 852 } 853 854 static int invalidate_tlbs_vmid(struct kgd_dev *kgd, uint16_t vmid) 855 { 856 struct amdgpu_device *adev = (struct amdgpu_device *) kgd; 857 858 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 859 pr_err("non kfd vmid %d\n", vmid); 860 return 0; 861 } 862 863 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 864 return 0; 865 } 866 867 static int kgd_address_watch_disable(struct kgd_dev *kgd) 868 { 869 return 0; 870 } 871 872 static int kgd_address_watch_execute(struct kgd_dev *kgd, 873 unsigned int watch_point_id, 874 uint32_t cntl_val, 875 uint32_t addr_hi, 876 uint32_t addr_lo) 877 { 878 return 0; 879 } 880 881 static int kgd_wave_control_execute(struct kgd_dev *kgd, 882 uint32_t gfx_index_val, 883 uint32_t sq_cmd) 884 { 885 struct amdgpu_device *adev = get_amdgpu_device(kgd); 886 uint32_t data = 0; 887 888 mutex_lock(&adev->grbm_idx_mutex); 889 890 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val); 891 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd); 892 893 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 894 INSTANCE_BROADCAST_WRITES, 1); 895 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 896 SA_BROADCAST_WRITES, 1); 897 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 898 SE_BROADCAST_WRITES, 1); 899 900 WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); 901 mutex_unlock(&adev->grbm_idx_mutex); 902 903 return 0; 904 } 905 906 static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd, 907 unsigned int watch_point_id, 908 unsigned int reg_offset) 909 { 910 return 0; 911 } 912 913 static void set_vm_context_page_table_base(struct kgd_dev *kgd, uint32_t vmid, 914 uint64_t page_table_base) 915 { 916 struct amdgpu_device *adev = get_amdgpu_device(kgd); 917 uint64_t base = page_table_base | AMDGPU_PTE_VALID; 918 919 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 920 pr_err("trying to set page table base for wrong VMID %u\n", 921 vmid); 922 return; 923 } 924 925 /* TODO: take advantage of per-process address space size. For 926 * now, all processes share the same address space size, like 927 * on GFX8 and older. 928 */ 929 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32) + (vmid*2), 0); 930 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32) + (vmid*2), 0); 931 932 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32) + (vmid*2), 933 lower_32_bits(adev->vm_manager.max_pfn - 1)); 934 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32) + (vmid*2), 935 upper_32_bits(adev->vm_manager.max_pfn - 1)); 936 937 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) + (vmid*2), lower_32_bits(base)); 938 WREG32(SOC15_REG_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) + (vmid*2), upper_32_bits(base)); 939 } 940