1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "amdgpu.h" 23 #include "amdgpu_amdkfd.h" 24 #include "gc/gc_10_1_0_offset.h" 25 #include "gc/gc_10_1_0_sh_mask.h" 26 #include "athub/athub_2_0_0_offset.h" 27 #include "athub/athub_2_0_0_sh_mask.h" 28 #include "oss/osssys_5_0_0_offset.h" 29 #include "oss/osssys_5_0_0_sh_mask.h" 30 #include "soc15_common.h" 31 #include "v10_structs.h" 32 #include "nv.h" 33 #include "nvd.h" 34 35 enum hqd_dequeue_request_type { 36 NO_ACTION = 0, 37 DRAIN_PIPE, 38 RESET_WAVES, 39 SAVE_WAVES 40 }; 41 42 static void lock_srbm(struct amdgpu_device *adev, uint32_t mec, uint32_t pipe, 43 uint32_t queue, uint32_t vmid) 44 { 45 mutex_lock(&adev->srbm_mutex); 46 nv_grbm_select(adev, mec, pipe, queue, vmid); 47 } 48 49 static void unlock_srbm(struct amdgpu_device *adev) 50 { 51 nv_grbm_select(adev, 0, 0, 0, 0); 52 mutex_unlock(&adev->srbm_mutex); 53 } 54 55 static void acquire_queue(struct amdgpu_device *adev, uint32_t pipe_id, 56 uint32_t queue_id) 57 { 58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 60 61 lock_srbm(adev, mec, pipe, queue_id, 0); 62 } 63 64 static uint64_t get_queue_mask(struct amdgpu_device *adev, 65 uint32_t pipe_id, uint32_t queue_id) 66 { 67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + 68 queue_id; 69 70 return 1ull << bit; 71 } 72 73 static void release_queue(struct amdgpu_device *adev) 74 { 75 unlock_srbm(adev); 76 } 77 78 static void kgd_program_sh_mem_settings(struct amdgpu_device *adev, uint32_t vmid, 79 uint32_t sh_mem_config, 80 uint32_t sh_mem_ape1_base, 81 uint32_t sh_mem_ape1_limit, 82 uint32_t sh_mem_bases, uint32_t inst) 83 { 84 lock_srbm(adev, 0, 0, 0, vmid); 85 86 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config); 87 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases); 88 /* APE1 no longer exists on GFX9 */ 89 90 unlock_srbm(adev); 91 } 92 93 static int kgd_set_pasid_vmid_mapping(struct amdgpu_device *adev, u32 pasid, 94 unsigned int vmid, uint32_t inst) 95 { 96 /* 97 * We have to assume that there is no outstanding mapping. 98 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because 99 * a mapping is in progress or because a mapping finished 100 * and the SW cleared it. 101 * So the protocol is to always wait & clear. 102 */ 103 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid | 104 ATC_VMID0_PASID_MAPPING__VALID_MASK; 105 106 pr_debug("pasid 0x%x vmid %d, reg value %x\n", pasid, vmid, pasid_mapping); 107 108 pr_debug("ATHUB, reg %x\n", SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid); 109 WREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid, 110 pasid_mapping); 111 112 #if 0 113 /* TODO: uncomment this code when the hardware support is ready. */ 114 while (!(RREG32(SOC15_REG_OFFSET( 115 ATHUB, 0, 116 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS)) & 117 (1U << vmid))) 118 cpu_relax(); 119 120 pr_debug("ATHUB mapping update finished\n"); 121 WREG32(SOC15_REG_OFFSET(ATHUB, 0, 122 mmATC_VMID_PASID_MAPPING_UPDATE_STATUS), 123 1U << vmid); 124 #endif 125 126 /* Mapping vmid to pasid also for IH block */ 127 pr_debug("update mapping for IH block and mmhub"); 128 WREG32(SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid, 129 pasid_mapping); 130 131 return 0; 132 } 133 134 /* TODO - RING0 form of field is obsolete, seems to date back to SI 135 * but still works 136 */ 137 138 static int kgd_init_interrupts(struct amdgpu_device *adev, uint32_t pipe_id, 139 uint32_t inst) 140 { 141 uint32_t mec; 142 uint32_t pipe; 143 144 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 145 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 146 147 lock_srbm(adev, mec, pipe, 0, 0); 148 149 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, 150 CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK | 151 CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK); 152 153 unlock_srbm(adev); 154 155 return 0; 156 } 157 158 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 159 unsigned int engine_id, 160 unsigned int queue_id) 161 { 162 uint32_t sdma_engine_reg_base[2] = { 163 SOC15_REG_OFFSET(SDMA0, 0, 164 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 165 /* On gfx10, mmSDMA1_xxx registers are defined NOT based 166 * on SDMA1 base address (dw 0x1860) but based on SDMA0 167 * base address (dw 0x1260). Therefore use mmSDMA0_RLC0_RB_CNTL 168 * instead of mmSDMA1_RLC0_RB_CNTL for the base address calc 169 * below 170 */ 171 SOC15_REG_OFFSET(SDMA1, 0, 172 mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL 173 }; 174 175 uint32_t retval = sdma_engine_reg_base[engine_id] 176 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 177 178 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 179 queue_id, retval); 180 181 return retval; 182 } 183 184 #if 0 185 static uint32_t get_watch_base_addr(struct amdgpu_device *adev) 186 { 187 uint32_t retval = SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_ADDR_H) - 188 mmTCP_WATCH0_ADDR_H; 189 190 pr_debug("kfd: reg watch base address: 0x%x\n", retval); 191 192 return retval; 193 } 194 #endif 195 196 static inline struct v10_compute_mqd *get_mqd(void *mqd) 197 { 198 return (struct v10_compute_mqd *)mqd; 199 } 200 201 static inline struct v10_sdma_mqd *get_sdma_mqd(void *mqd) 202 { 203 return (struct v10_sdma_mqd *)mqd; 204 } 205 206 static int kgd_hqd_load(struct amdgpu_device *adev, void *mqd, 207 uint32_t pipe_id, uint32_t queue_id, 208 uint32_t __user *wptr, uint32_t wptr_shift, 209 uint32_t wptr_mask, struct mm_struct *mm, uint32_t inst) 210 { 211 struct v10_compute_mqd *m; 212 uint32_t *mqd_hqd; 213 uint32_t reg, hqd_base, data; 214 215 m = get_mqd(mqd); 216 217 pr_debug("Load hqd of pipe %d queue %d\n", pipe_id, queue_id); 218 acquire_queue(adev, pipe_id, queue_id); 219 220 /* HQD registers extend from CP_MQD_BASE_ADDR to CP_HQD_EOP_WPTR_MEM. */ 221 mqd_hqd = &m->cp_mqd_base_addr_lo; 222 hqd_base = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 223 224 for (reg = hqd_base; 225 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 226 WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]); 227 228 229 /* Activate doorbell logic before triggering WPTR poll. */ 230 data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control, 231 CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1); 232 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data); 233 234 if (wptr) { 235 /* Don't read wptr with get_user because the user 236 * context may not be accessible (if this function 237 * runs in a work queue). Instead trigger a one-shot 238 * polling read from memory in the CP. This assumes 239 * that wptr is GPU-accessible in the queue's VMID via 240 * ATC or SVM. WPTR==RPTR before starting the poll so 241 * the CP starts fetching new commands from the right 242 * place. 243 * 244 * Guessing a 64-bit WPTR from a 32-bit RPTR is a bit 245 * tricky. Assume that the queue didn't overflow. The 246 * number of valid bits in the 32-bit RPTR depends on 247 * the queue size. The remaining bits are taken from 248 * the saved 64-bit WPTR. If the WPTR wrapped, add the 249 * queue size. 250 */ 251 uint32_t queue_size = 252 2 << REG_GET_FIELD(m->cp_hqd_pq_control, 253 CP_HQD_PQ_CONTROL, QUEUE_SIZE); 254 uint64_t guessed_wptr = m->cp_hqd_pq_rptr & (queue_size - 1); 255 256 if ((m->cp_hqd_pq_wptr_lo & (queue_size - 1)) < guessed_wptr) 257 guessed_wptr += queue_size; 258 guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1); 259 guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32; 260 261 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 262 lower_32_bits(guessed_wptr)); 263 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 264 upper_32_bits(guessed_wptr)); 265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR, 266 lower_32_bits((uint64_t)wptr)); 267 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI, 268 upper_32_bits((uint64_t)wptr)); 269 pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__, 270 (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); 271 WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1, 272 (uint32_t)get_queue_mask(adev, pipe_id, queue_id)); 273 } 274 275 /* Start the EOP fetcher */ 276 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR, 277 REG_SET_FIELD(m->cp_hqd_eop_rptr, 278 CP_HQD_EOP_RPTR, INIT_FETCHER, 1)); 279 280 data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1); 281 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); 282 283 release_queue(adev); 284 285 return 0; 286 } 287 288 static int kgd_hiq_mqd_load(struct amdgpu_device *adev, void *mqd, 289 uint32_t pipe_id, uint32_t queue_id, 290 uint32_t doorbell_off, uint32_t inst) 291 { 292 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; 293 struct v10_compute_mqd *m; 294 uint32_t mec, pipe; 295 int r; 296 297 m = get_mqd(mqd); 298 299 acquire_queue(adev, pipe_id, queue_id); 300 301 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; 302 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); 303 304 pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n", 305 mec, pipe, queue_id); 306 307 spin_lock(&adev->gfx.kiq[0].ring_lock); 308 r = amdgpu_ring_alloc(kiq_ring, 7); 309 if (r) { 310 pr_err("Failed to alloc KIQ (%d).\n", r); 311 goto out_unlock; 312 } 313 314 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5)); 315 amdgpu_ring_write(kiq_ring, 316 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */ 317 PACKET3_MAP_QUEUES_VMID(m->cp_hqd_vmid) | /* VMID */ 318 PACKET3_MAP_QUEUES_QUEUE(queue_id) | 319 PACKET3_MAP_QUEUES_PIPE(pipe) | 320 PACKET3_MAP_QUEUES_ME((mec - 1)) | 321 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ 322 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ 323 PACKET3_MAP_QUEUES_ENGINE_SEL(1) | /* engine_sel: hiq */ 324 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */ 325 amdgpu_ring_write(kiq_ring, 326 PACKET3_MAP_QUEUES_DOORBELL_OFFSET(doorbell_off)); 327 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_lo); 328 amdgpu_ring_write(kiq_ring, m->cp_mqd_base_addr_hi); 329 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_lo); 330 amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi); 331 amdgpu_ring_commit(kiq_ring); 332 333 out_unlock: 334 spin_unlock(&adev->gfx.kiq[0].ring_lock); 335 release_queue(adev); 336 337 return r; 338 } 339 340 static int kgd_hqd_dump(struct amdgpu_device *adev, 341 uint32_t pipe_id, uint32_t queue_id, 342 uint32_t (**dump)[2], uint32_t *n_regs, uint32_t inst) 343 { 344 uint32_t i = 0, reg; 345 #define HQD_N_REGS 56 346 #define DUMP_REG(addr) do { \ 347 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 348 break; \ 349 (*dump)[i][0] = (addr) << 2; \ 350 (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \ 351 } while (0) 352 353 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 354 if (*dump == NULL) 355 return -ENOMEM; 356 357 acquire_queue(adev, pipe_id, queue_id); 358 359 for (reg = SOC15_REG_OFFSET(GC, 0, mmCP_MQD_BASE_ADDR); 360 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) 361 DUMP_REG(reg); 362 363 release_queue(adev); 364 365 WARN_ON_ONCE(i != HQD_N_REGS); 366 *n_regs = i; 367 368 return 0; 369 } 370 371 static int kgd_hqd_sdma_load(struct amdgpu_device *adev, void *mqd, 372 uint32_t __user *wptr, struct mm_struct *mm) 373 { 374 struct v10_sdma_mqd *m; 375 uint32_t sdma_rlc_reg_offset; 376 unsigned long end_jiffies; 377 uint32_t data; 378 uint64_t data64; 379 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 380 381 m = get_sdma_mqd(mqd); 382 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 383 m->sdma_queue_id); 384 385 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 386 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 387 388 end_jiffies = msecs_to_jiffies(2000) + jiffies; 389 while (true) { 390 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 391 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 392 break; 393 if (time_after(jiffies, end_jiffies)) { 394 pr_err("SDMA RLC not idle in %s\n", __func__); 395 return -ETIME; 396 } 397 usleep_range(500, 1000); 398 } 399 400 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 401 m->sdmax_rlcx_doorbell_offset); 402 403 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 404 ENABLE, 1); 405 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 406 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 407 m->sdmax_rlcx_rb_rptr); 408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 409 m->sdmax_rlcx_rb_rptr_hi); 410 411 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 412 if (read_user_wptr(mm, wptr64, data64)) { 413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 414 lower_32_bits(data64)); 415 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 416 upper_32_bits(data64)); 417 } else { 418 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 419 m->sdmax_rlcx_rb_rptr); 420 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 421 m->sdmax_rlcx_rb_rptr_hi); 422 } 423 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 424 425 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 426 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 427 m->sdmax_rlcx_rb_base_hi); 428 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 429 m->sdmax_rlcx_rb_rptr_addr_lo); 430 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 431 m->sdmax_rlcx_rb_rptr_addr_hi); 432 433 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 434 RB_ENABLE, 1); 435 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 436 437 return 0; 438 } 439 440 static int kgd_hqd_sdma_dump(struct amdgpu_device *adev, 441 uint32_t engine_id, uint32_t queue_id, 442 uint32_t (**dump)[2], uint32_t *n_regs) 443 { 444 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 445 engine_id, queue_id); 446 uint32_t i = 0, reg; 447 #undef HQD_N_REGS 448 #define HQD_N_REGS (19+6+7+10) 449 450 *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL); 451 if (*dump == NULL) 452 return -ENOMEM; 453 454 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 455 DUMP_REG(sdma_rlc_reg_offset + reg); 456 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 457 DUMP_REG(sdma_rlc_reg_offset + reg); 458 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 459 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 460 DUMP_REG(sdma_rlc_reg_offset + reg); 461 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 462 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 463 DUMP_REG(sdma_rlc_reg_offset + reg); 464 465 WARN_ON_ONCE(i != HQD_N_REGS); 466 *n_regs = i; 467 468 return 0; 469 } 470 471 static bool kgd_hqd_is_occupied(struct amdgpu_device *adev, 472 uint64_t queue_address, uint32_t pipe_id, 473 uint32_t queue_id, uint32_t inst) 474 { 475 uint32_t act; 476 bool retval = false; 477 uint32_t low, high; 478 479 acquire_queue(adev, pipe_id, queue_id); 480 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); 481 if (act) { 482 low = lower_32_bits(queue_address >> 8); 483 high = upper_32_bits(queue_address >> 8); 484 485 if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) && 486 high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI)) 487 retval = true; 488 } 489 release_queue(adev); 490 return retval; 491 } 492 493 static bool kgd_hqd_sdma_is_occupied(struct amdgpu_device *adev, void *mqd) 494 { 495 struct v10_sdma_mqd *m; 496 uint32_t sdma_rlc_reg_offset; 497 uint32_t sdma_rlc_rb_cntl; 498 499 m = get_sdma_mqd(mqd); 500 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 501 m->sdma_queue_id); 502 503 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 504 505 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 506 return true; 507 508 return false; 509 } 510 511 static int kgd_hqd_destroy(struct amdgpu_device *adev, void *mqd, 512 enum kfd_preempt_type reset_type, 513 unsigned int utimeout, uint32_t pipe_id, 514 uint32_t queue_id, uint32_t inst) 515 { 516 enum hqd_dequeue_request_type type; 517 unsigned long end_jiffies; 518 uint32_t temp; 519 struct v10_compute_mqd *m = get_mqd(mqd); 520 521 if (amdgpu_in_reset(adev)) 522 return -EIO; 523 524 #if 0 525 unsigned long flags; 526 int retry; 527 #endif 528 529 acquire_queue(adev, pipe_id, queue_id); 530 531 if (m->cp_hqd_vmid == 0) 532 WREG32_FIELD15(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0); 533 534 switch (reset_type) { 535 case KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN: 536 type = DRAIN_PIPE; 537 break; 538 case KFD_PREEMPT_TYPE_WAVEFRONT_RESET: 539 type = RESET_WAVES; 540 break; 541 case KFD_PREEMPT_TYPE_WAVEFRONT_SAVE: 542 type = SAVE_WAVES; 543 break; 544 default: 545 type = DRAIN_PIPE; 546 break; 547 } 548 549 #if 0 /* Is this still needed? */ 550 /* Workaround: If IQ timer is active and the wait time is close to or 551 * equal to 0, dequeueing is not safe. Wait until either the wait time 552 * is larger or timer is cleared. Also, ensure that IQ_REQ_PEND is 553 * cleared before continuing. Also, ensure wait times are set to at 554 * least 0x3. 555 */ 556 local_irq_save(flags); 557 preempt_disable(); 558 retry = 5000; /* wait for 500 usecs at maximum */ 559 while (true) { 560 temp = RREG32(mmCP_HQD_IQ_TIMER); 561 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, PROCESSING_IQ)) { 562 pr_debug("HW is processing IQ\n"); 563 goto loop; 564 } 565 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, ACTIVE)) { 566 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, RETRY_TYPE) 567 == 3) /* SEM-rearm is safe */ 568 break; 569 /* Wait time 3 is safe for CP, but our MMIO read/write 570 * time is close to 1 microsecond, so check for 10 to 571 * leave more buffer room 572 */ 573 if (REG_GET_FIELD(temp, CP_HQD_IQ_TIMER, WAIT_TIME) 574 >= 10) 575 break; 576 pr_debug("IQ timer is active\n"); 577 } else 578 break; 579 loop: 580 if (!retry) { 581 pr_err("CP HQD IQ timer status time out\n"); 582 break; 583 } 584 ndelay(100); 585 --retry; 586 } 587 retry = 1000; 588 while (true) { 589 temp = RREG32(mmCP_HQD_DEQUEUE_REQUEST); 590 if (!(temp & CP_HQD_DEQUEUE_REQUEST__IQ_REQ_PEND_MASK)) 591 break; 592 pr_debug("Dequeue request is pending\n"); 593 594 if (!retry) { 595 pr_err("CP HQD dequeue request time out\n"); 596 break; 597 } 598 ndelay(100); 599 --retry; 600 } 601 local_irq_restore(flags); 602 preempt_enable(); 603 #endif 604 605 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type); 606 607 end_jiffies = (utimeout * HZ / 1000) + jiffies; 608 while (true) { 609 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); 610 if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK)) 611 break; 612 if (time_after(jiffies, end_jiffies)) { 613 pr_err("cp queue preemption time out.\n"); 614 release_queue(adev); 615 return -ETIME; 616 } 617 usleep_range(500, 1000); 618 } 619 620 release_queue(adev); 621 return 0; 622 } 623 624 static int kgd_hqd_sdma_destroy(struct amdgpu_device *adev, void *mqd, 625 unsigned int utimeout) 626 { 627 struct v10_sdma_mqd *m; 628 uint32_t sdma_rlc_reg_offset; 629 uint32_t temp; 630 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 631 632 m = get_sdma_mqd(mqd); 633 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 634 m->sdma_queue_id); 635 636 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 637 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 638 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 639 640 while (true) { 641 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 642 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 643 break; 644 if (time_after(jiffies, end_jiffies)) { 645 pr_err("SDMA RLC not idle in %s\n", __func__); 646 return -ETIME; 647 } 648 usleep_range(500, 1000); 649 } 650 651 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 652 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 653 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 654 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 655 656 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 657 m->sdmax_rlcx_rb_rptr_hi = 658 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 659 660 return 0; 661 } 662 663 static bool get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, 664 uint8_t vmid, uint16_t *p_pasid) 665 { 666 uint32_t value; 667 668 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) 669 + vmid); 670 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; 671 672 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); 673 } 674 675 static int kgd_wave_control_execute(struct amdgpu_device *adev, 676 uint32_t gfx_index_val, 677 uint32_t sq_cmd, uint32_t inst) 678 { 679 uint32_t data = 0; 680 681 mutex_lock(&adev->grbm_idx_mutex); 682 683 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val); 684 WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd); 685 686 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 687 INSTANCE_BROADCAST_WRITES, 1); 688 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 689 SA_BROADCAST_WRITES, 1); 690 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, 691 SE_BROADCAST_WRITES, 1); 692 693 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data); 694 mutex_unlock(&adev->grbm_idx_mutex); 695 696 return 0; 697 } 698 699 static void set_vm_context_page_table_base(struct amdgpu_device *adev, 700 uint32_t vmid, uint64_t page_table_base) 701 { 702 if (!amdgpu_amdkfd_is_kfd_vmid(adev, vmid)) { 703 pr_err("trying to set page table base for wrong VMID %u\n", 704 vmid); 705 return; 706 } 707 708 /* SDMA is on gfxhub as well for Navi1* series */ 709 adev->gfxhub.funcs->setup_vm_pt_regs(adev, vmid, page_table_base); 710 } 711 712 static void program_trap_handler_settings(struct amdgpu_device *adev, 713 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, 714 uint32_t inst) 715 { 716 lock_srbm(adev, 0, 0, 0, vmid); 717 718 /* 719 * Program TBA registers 720 */ 721 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_LO), 722 lower_32_bits(tba_addr >> 8)); 723 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TBA_HI), 724 upper_32_bits(tba_addr >> 8) | 725 (1 << SQ_SHADER_TBA_HI__TRAP_EN__SHIFT)); 726 727 /* 728 * Program TMA registers 729 */ 730 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_LO), 731 lower_32_bits(tma_addr >> 8)); 732 WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_SHADER_TMA_HI), 733 upper_32_bits(tma_addr >> 8)); 734 735 unlock_srbm(adev); 736 } 737 738 const struct kfd2kgd_calls gfx_v10_kfd2kgd = { 739 .program_sh_mem_settings = kgd_program_sh_mem_settings, 740 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping, 741 .init_interrupts = kgd_init_interrupts, 742 .hqd_load = kgd_hqd_load, 743 .hiq_mqd_load = kgd_hiq_mqd_load, 744 .hqd_sdma_load = kgd_hqd_sdma_load, 745 .hqd_dump = kgd_hqd_dump, 746 .hqd_sdma_dump = kgd_hqd_sdma_dump, 747 .hqd_is_occupied = kgd_hqd_is_occupied, 748 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 749 .hqd_destroy = kgd_hqd_destroy, 750 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 751 .wave_control_execute = kgd_wave_control_execute, 752 .get_atc_vmid_pasid_mapping_info = 753 get_atc_vmid_pasid_mapping_info, 754 .set_vm_context_page_table_base = set_vm_context_page_table_base, 755 .program_trap_handler_settings = program_trap_handler_settings, 756 }; 757