1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #undef pr_fmt 24 #define pr_fmt(fmt) "kfd2kgd: " fmt 25 26 #include <linux/module.h> 27 #include <linux/fdtable.h> 28 #include <linux/uaccess.h> 29 #include <linux/mmu_context.h> 30 #include <linux/firmware.h> 31 #include <drm/drmP.h> 32 #include "amdgpu.h" 33 #include "amdgpu_amdkfd.h" 34 #include "sdma0/sdma0_4_2_2_offset.h" 35 #include "sdma0/sdma0_4_2_2_sh_mask.h" 36 #include "sdma1/sdma1_4_2_2_offset.h" 37 #include "sdma1/sdma1_4_2_2_sh_mask.h" 38 #include "sdma2/sdma2_4_2_2_offset.h" 39 #include "sdma2/sdma2_4_2_2_sh_mask.h" 40 #include "sdma3/sdma3_4_2_2_offset.h" 41 #include "sdma3/sdma3_4_2_2_sh_mask.h" 42 #include "sdma4/sdma4_4_2_2_offset.h" 43 #include "sdma4/sdma4_4_2_2_sh_mask.h" 44 #include "sdma5/sdma5_4_2_2_offset.h" 45 #include "sdma5/sdma5_4_2_2_sh_mask.h" 46 #include "sdma6/sdma6_4_2_2_offset.h" 47 #include "sdma6/sdma6_4_2_2_sh_mask.h" 48 #include "sdma7/sdma7_4_2_2_offset.h" 49 #include "sdma7/sdma7_4_2_2_sh_mask.h" 50 #include "v9_structs.h" 51 #include "soc15.h" 52 #include "soc15d.h" 53 #include "amdgpu_amdkfd_gfx_v9.h" 54 55 #define HQD_N_REGS 56 56 #define DUMP_REG(addr) do { \ 57 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 58 break; \ 59 (*dump)[i][0] = (addr) << 2; \ 60 (*dump)[i++][1] = RREG32(addr); \ 61 } while (0) 62 63 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 64 { 65 return (struct amdgpu_device *)kgd; 66 } 67 68 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 69 { 70 return (struct v9_sdma_mqd *)mqd; 71 } 72 73 static uint32_t get_sdma_base_addr(struct amdgpu_device *adev, 74 unsigned int engine_id, 75 unsigned int queue_id) 76 { 77 uint32_t base[8] = { 78 SOC15_REG_OFFSET(SDMA0, 0, 79 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 80 SOC15_REG_OFFSET(SDMA1, 0, 81 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL, 82 SOC15_REG_OFFSET(SDMA2, 0, 83 mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL, 84 SOC15_REG_OFFSET(SDMA3, 0, 85 mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL, 86 SOC15_REG_OFFSET(SDMA4, 0, 87 mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL, 88 SOC15_REG_OFFSET(SDMA5, 0, 89 mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL, 90 SOC15_REG_OFFSET(SDMA6, 0, 91 mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL, 92 SOC15_REG_OFFSET(SDMA7, 0, 93 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL 94 }; 95 uint32_t retval; 96 97 retval = base[engine_id] + queue_id * (mmSDMA0_RLC1_RB_CNTL - 98 mmSDMA0_RLC0_RB_CNTL); 99 100 pr_debug("sdma base address: 0x%x\n", retval); 101 102 return retval; 103 } 104 105 static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev, 106 u32 instance, u32 offset) 107 { 108 switch (instance) { 109 case 0: 110 return (adev->reg_offset[SDMA0_HWIP][0][0] + offset); 111 case 1: 112 return (adev->reg_offset[SDMA1_HWIP][0][1] + offset); 113 case 2: 114 return (adev->reg_offset[SDMA2_HWIP][0][1] + offset); 115 case 3: 116 return (adev->reg_offset[SDMA3_HWIP][0][1] + offset); 117 case 4: 118 return (adev->reg_offset[SDMA4_HWIP][0][1] + offset); 119 case 5: 120 return (adev->reg_offset[SDMA5_HWIP][0][1] + offset); 121 case 6: 122 return (adev->reg_offset[SDMA6_HWIP][0][1] + offset); 123 case 7: 124 return (adev->reg_offset[SDMA7_HWIP][0][1] + offset); 125 default: 126 break; 127 } 128 return 0; 129 } 130 131 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 132 uint32_t __user *wptr, struct mm_struct *mm) 133 { 134 struct amdgpu_device *adev = get_amdgpu_device(kgd); 135 struct v9_sdma_mqd *m; 136 uint32_t sdma_base_addr, sdmax_gfx_context_cntl; 137 unsigned long end_jiffies; 138 uint32_t data; 139 uint64_t data64; 140 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 141 142 m = get_sdma_mqd(mqd); 143 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 144 m->sdma_queue_id); 145 sdmax_gfx_context_cntl = sdma_v4_0_get_reg_offset(adev, 146 m->sdma_engine_id, mmSDMA0_GFX_CONTEXT_CNTL); 147 148 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 149 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 150 151 end_jiffies = msecs_to_jiffies(2000) + jiffies; 152 while (true) { 153 data = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 154 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 155 break; 156 if (time_after(jiffies, end_jiffies)) 157 return -ETIME; 158 usleep_range(500, 1000); 159 } 160 data = RREG32(sdmax_gfx_context_cntl); 161 data = REG_SET_FIELD(data, SDMA0_GFX_CONTEXT_CNTL, 162 RESUME_CTX, 0); 163 WREG32(sdmax_gfx_context_cntl, data); 164 165 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL_OFFSET, 166 m->sdmax_rlcx_doorbell_offset); 167 168 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 169 ENABLE, 1); 170 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, data); 171 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, m->sdmax_rlcx_rb_rptr); 172 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI, 173 m->sdmax_rlcx_rb_rptr_hi); 174 175 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 176 if (read_user_wptr(mm, wptr64, data64)) { 177 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 178 lower_32_bits(data64)); 179 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 180 upper_32_bits(data64)); 181 } else { 182 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 183 m->sdmax_rlcx_rb_rptr); 184 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR_HI, 185 m->sdmax_rlcx_rb_rptr_hi); 186 } 187 WREG32(sdma_base_addr + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 188 189 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 190 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE_HI, 191 m->sdmax_rlcx_rb_base_hi); 192 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 193 m->sdmax_rlcx_rb_rptr_addr_lo); 194 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 195 m->sdmax_rlcx_rb_rptr_addr_hi); 196 197 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 198 RB_ENABLE, 1); 199 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, data); 200 201 return 0; 202 } 203 204 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 205 uint32_t engine_id, uint32_t queue_id, 206 uint32_t (**dump)[2], uint32_t *n_regs) 207 { 208 struct amdgpu_device *adev = get_amdgpu_device(kgd); 209 uint32_t sdma_base_addr = get_sdma_base_addr(adev, engine_id, queue_id); 210 uint32_t i = 0, reg; 211 #undef HQD_N_REGS 212 #define HQD_N_REGS (19+6+7+10) 213 214 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 215 if (*dump == NULL) 216 return -ENOMEM; 217 218 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 219 DUMP_REG(sdma_base_addr + reg); 220 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 221 DUMP_REG(sdma_base_addr + reg); 222 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 223 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 224 DUMP_REG(sdma_base_addr + reg); 225 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 226 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 227 DUMP_REG(sdma_base_addr + reg); 228 229 WARN_ON_ONCE(i != HQD_N_REGS); 230 *n_regs = i; 231 232 return 0; 233 } 234 235 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 236 { 237 struct amdgpu_device *adev = get_amdgpu_device(kgd); 238 struct v9_sdma_mqd *m; 239 uint32_t sdma_base_addr; 240 uint32_t sdma_rlc_rb_cntl; 241 242 m = get_sdma_mqd(mqd); 243 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 244 m->sdma_queue_id); 245 246 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 247 248 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 249 return true; 250 251 return false; 252 } 253 254 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 255 unsigned int utimeout) 256 { 257 struct amdgpu_device *adev = get_amdgpu_device(kgd); 258 struct v9_sdma_mqd *m; 259 uint32_t sdma_base_addr; 260 uint32_t temp; 261 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 262 263 m = get_sdma_mqd(mqd); 264 sdma_base_addr = get_sdma_base_addr(adev, m->sdma_engine_id, 265 m->sdma_queue_id); 266 267 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL); 268 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 269 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp); 270 271 while (true) { 272 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS); 273 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 274 break; 275 if (time_after(jiffies, end_jiffies)) 276 return -ETIME; 277 usleep_range(500, 1000); 278 } 279 280 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0); 281 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, 282 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL) | 283 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 284 285 m->sdmax_rlcx_rb_rptr = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR); 286 m->sdmax_rlcx_rb_rptr_hi = 287 RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR_HI); 288 289 return 0; 290 } 291 292 static const struct kfd2kgd_calls kfd2kgd = { 293 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 294 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 295 .init_interrupts = kgd_gfx_v9_init_interrupts, 296 .hqd_load = kgd_gfx_v9_hqd_load, 297 .hqd_sdma_load = kgd_hqd_sdma_load, 298 .hqd_dump = kgd_gfx_v9_hqd_dump, 299 .hqd_sdma_dump = kgd_hqd_sdma_dump, 300 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 301 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 302 .hqd_destroy = kgd_gfx_v9_hqd_destroy, 303 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 304 .address_watch_disable = kgd_gfx_v9_address_watch_disable, 305 .address_watch_execute = kgd_gfx_v9_address_watch_execute, 306 .wave_control_execute = kgd_gfx_v9_wave_control_execute, 307 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, 308 .get_atc_vmid_pasid_mapping_pasid = 309 kgd_gfx_v9_get_atc_vmid_pasid_mapping_pasid, 310 .get_atc_vmid_pasid_mapping_valid = 311 kgd_gfx_v9_get_atc_vmid_pasid_mapping_valid, 312 .set_scratch_backing_va = kgd_gfx_v9_set_scratch_backing_va, 313 .get_tile_config = kgd_gfx_v9_get_tile_config, 314 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 315 .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, 316 .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, 317 .get_hive_id = amdgpu_amdkfd_get_hive_id, 318 }; 319 320 struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void) 321 { 322 return (struct kfd2kgd_calls *)&kfd2kgd; 323 } 324 325