1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #undef pr_fmt 24 #define pr_fmt(fmt) "kfd2kgd: " fmt 25 26 #include <linux/module.h> 27 #include <linux/fdtable.h> 28 #include <linux/uaccess.h> 29 #include <linux/mmu_context.h> 30 #include <linux/firmware.h> 31 #include "amdgpu.h" 32 #include "amdgpu_amdkfd.h" 33 #include "sdma0/sdma0_4_2_2_offset.h" 34 #include "sdma0/sdma0_4_2_2_sh_mask.h" 35 #include "sdma1/sdma1_4_2_2_offset.h" 36 #include "sdma1/sdma1_4_2_2_sh_mask.h" 37 #include "sdma2/sdma2_4_2_2_offset.h" 38 #include "sdma2/sdma2_4_2_2_sh_mask.h" 39 #include "sdma3/sdma3_4_2_2_offset.h" 40 #include "sdma3/sdma3_4_2_2_sh_mask.h" 41 #include "sdma4/sdma4_4_2_2_offset.h" 42 #include "sdma4/sdma4_4_2_2_sh_mask.h" 43 #include "sdma5/sdma5_4_2_2_offset.h" 44 #include "sdma5/sdma5_4_2_2_sh_mask.h" 45 #include "sdma6/sdma6_4_2_2_offset.h" 46 #include "sdma6/sdma6_4_2_2_sh_mask.h" 47 #include "sdma7/sdma7_4_2_2_offset.h" 48 #include "sdma7/sdma7_4_2_2_sh_mask.h" 49 #include "v9_structs.h" 50 #include "soc15.h" 51 #include "soc15d.h" 52 #include "amdgpu_amdkfd_gfx_v9.h" 53 54 #define HQD_N_REGS 56 55 #define DUMP_REG(addr) do { \ 56 if (WARN_ON_ONCE(i >= HQD_N_REGS)) \ 57 break; \ 58 (*dump)[i][0] = (addr) << 2; \ 59 (*dump)[i++][1] = RREG32(addr); \ 60 } while (0) 61 62 static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd) 63 { 64 return (struct amdgpu_device *)kgd; 65 } 66 67 static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) 68 { 69 return (struct v9_sdma_mqd *)mqd; 70 } 71 72 static uint32_t get_sdma_rlc_reg_offset(struct amdgpu_device *adev, 73 unsigned int engine_id, 74 unsigned int queue_id) 75 { 76 uint32_t sdma_engine_reg_base[8] = { 77 SOC15_REG_OFFSET(SDMA0, 0, 78 mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL, 79 SOC15_REG_OFFSET(SDMA1, 0, 80 mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL, 81 SOC15_REG_OFFSET(SDMA2, 0, 82 mmSDMA2_RLC0_RB_CNTL) - mmSDMA2_RLC0_RB_CNTL, 83 SOC15_REG_OFFSET(SDMA3, 0, 84 mmSDMA3_RLC0_RB_CNTL) - mmSDMA3_RLC0_RB_CNTL, 85 SOC15_REG_OFFSET(SDMA4, 0, 86 mmSDMA4_RLC0_RB_CNTL) - mmSDMA4_RLC0_RB_CNTL, 87 SOC15_REG_OFFSET(SDMA5, 0, 88 mmSDMA5_RLC0_RB_CNTL) - mmSDMA5_RLC0_RB_CNTL, 89 SOC15_REG_OFFSET(SDMA6, 0, 90 mmSDMA6_RLC0_RB_CNTL) - mmSDMA6_RLC0_RB_CNTL, 91 SOC15_REG_OFFSET(SDMA7, 0, 92 mmSDMA7_RLC0_RB_CNTL) - mmSDMA7_RLC0_RB_CNTL 93 }; 94 95 uint32_t retval = sdma_engine_reg_base[engine_id] 96 + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL); 97 98 pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id, 99 queue_id, retval); 100 101 return retval; 102 } 103 104 static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd, 105 uint32_t __user *wptr, struct mm_struct *mm) 106 { 107 struct amdgpu_device *adev = get_amdgpu_device(kgd); 108 struct v9_sdma_mqd *m; 109 uint32_t sdma_rlc_reg_offset; 110 unsigned long end_jiffies; 111 uint32_t data; 112 uint64_t data64; 113 uint64_t __user *wptr64 = (uint64_t __user *)wptr; 114 115 m = get_sdma_mqd(mqd); 116 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 117 m->sdma_queue_id); 118 119 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 120 m->sdmax_rlcx_rb_cntl & (~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)); 121 122 end_jiffies = msecs_to_jiffies(2000) + jiffies; 123 while (true) { 124 data = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 125 if (data & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 126 break; 127 if (time_after(jiffies, end_jiffies)) { 128 pr_err("SDMA RLC not idle in %s\n", __func__); 129 return -ETIME; 130 } 131 usleep_range(500, 1000); 132 } 133 134 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL_OFFSET, 135 m->sdmax_rlcx_doorbell_offset); 136 137 data = REG_SET_FIELD(m->sdmax_rlcx_doorbell, SDMA0_RLC0_DOORBELL, 138 ENABLE, 1); 139 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data); 140 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, 141 m->sdmax_rlcx_rb_rptr); 142 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI, 143 m->sdmax_rlcx_rb_rptr_hi); 144 145 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 1); 146 if (read_user_wptr(mm, wptr64, data64)) { 147 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 148 lower_32_bits(data64)); 149 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 150 upper_32_bits(data64)); 151 } else { 152 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, 153 m->sdmax_rlcx_rb_rptr); 154 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR_HI, 155 m->sdmax_rlcx_rb_rptr_hi); 156 } 157 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_MINOR_PTR_UPDATE, 0); 158 159 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base); 160 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI, 161 m->sdmax_rlcx_rb_base_hi); 162 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO, 163 m->sdmax_rlcx_rb_rptr_addr_lo); 164 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI, 165 m->sdmax_rlcx_rb_rptr_addr_hi); 166 167 data = REG_SET_FIELD(m->sdmax_rlcx_rb_cntl, SDMA0_RLC0_RB_CNTL, 168 RB_ENABLE, 1); 169 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data); 170 171 return 0; 172 } 173 174 static int kgd_hqd_sdma_dump(struct kgd_dev *kgd, 175 uint32_t engine_id, uint32_t queue_id, 176 uint32_t (**dump)[2], uint32_t *n_regs) 177 { 178 struct amdgpu_device *adev = get_amdgpu_device(kgd); 179 uint32_t sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, 180 engine_id, queue_id); 181 uint32_t i = 0, reg; 182 #undef HQD_N_REGS 183 #define HQD_N_REGS (19+6+7+10) 184 185 *dump = kmalloc_array(HQD_N_REGS * 2, sizeof(uint32_t), GFP_KERNEL); 186 if (*dump == NULL) 187 return -ENOMEM; 188 189 for (reg = mmSDMA0_RLC0_RB_CNTL; reg <= mmSDMA0_RLC0_DOORBELL; reg++) 190 DUMP_REG(sdma_rlc_reg_offset + reg); 191 for (reg = mmSDMA0_RLC0_STATUS; reg <= mmSDMA0_RLC0_CSA_ADDR_HI; reg++) 192 DUMP_REG(sdma_rlc_reg_offset + reg); 193 for (reg = mmSDMA0_RLC0_IB_SUB_REMAIN; 194 reg <= mmSDMA0_RLC0_MINOR_PTR_UPDATE; reg++) 195 DUMP_REG(sdma_rlc_reg_offset + reg); 196 for (reg = mmSDMA0_RLC0_MIDCMD_DATA0; 197 reg <= mmSDMA0_RLC0_MIDCMD_CNTL; reg++) 198 DUMP_REG(sdma_rlc_reg_offset + reg); 199 200 WARN_ON_ONCE(i != HQD_N_REGS); 201 *n_regs = i; 202 203 return 0; 204 } 205 206 static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd) 207 { 208 struct amdgpu_device *adev = get_amdgpu_device(kgd); 209 struct v9_sdma_mqd *m; 210 uint32_t sdma_rlc_reg_offset; 211 uint32_t sdma_rlc_rb_cntl; 212 213 m = get_sdma_mqd(mqd); 214 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 215 m->sdma_queue_id); 216 217 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 218 219 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK) 220 return true; 221 222 return false; 223 } 224 225 static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd, 226 unsigned int utimeout) 227 { 228 struct amdgpu_device *adev = get_amdgpu_device(kgd); 229 struct v9_sdma_mqd *m; 230 uint32_t sdma_rlc_reg_offset; 231 uint32_t temp; 232 unsigned long end_jiffies = (utimeout * HZ / 1000) + jiffies; 233 234 m = get_sdma_mqd(mqd); 235 sdma_rlc_reg_offset = get_sdma_rlc_reg_offset(adev, m->sdma_engine_id, 236 m->sdma_queue_id); 237 238 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL); 239 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK; 240 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp); 241 242 while (true) { 243 temp = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_CONTEXT_STATUS); 244 if (temp & SDMA0_RLC0_CONTEXT_STATUS__IDLE_MASK) 245 break; 246 if (time_after(jiffies, end_jiffies)) { 247 pr_err("SDMA RLC not idle in %s\n", __func__); 248 return -ETIME; 249 } 250 usleep_range(500, 1000); 251 } 252 253 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0); 254 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, 255 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL) | 256 SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK); 257 258 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); 259 m->sdmax_rlcx_rb_rptr_hi = 260 RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_HI); 261 262 return 0; 263 } 264 265 const struct kfd2kgd_calls arcturus_kfd2kgd = { 266 .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, 267 .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, 268 .init_interrupts = kgd_gfx_v9_init_interrupts, 269 .hqd_load = kgd_gfx_v9_hqd_load, 270 .hqd_sdma_load = kgd_hqd_sdma_load, 271 .hqd_dump = kgd_gfx_v9_hqd_dump, 272 .hqd_sdma_dump = kgd_hqd_sdma_dump, 273 .hqd_is_occupied = kgd_gfx_v9_hqd_is_occupied, 274 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied, 275 .hqd_destroy = kgd_gfx_v9_hqd_destroy, 276 .hqd_sdma_destroy = kgd_hqd_sdma_destroy, 277 .address_watch_disable = kgd_gfx_v9_address_watch_disable, 278 .address_watch_execute = kgd_gfx_v9_address_watch_execute, 279 .wave_control_execute = kgd_gfx_v9_wave_control_execute, 280 .address_watch_get_offset = kgd_gfx_v9_address_watch_get_offset, 281 .get_atc_vmid_pasid_mapping_info = 282 kgd_gfx_v9_get_atc_vmid_pasid_mapping_info, 283 .get_tile_config = kgd_gfx_v9_get_tile_config, 284 .set_vm_context_page_table_base = kgd_gfx_v9_set_vm_context_page_table_base, 285 .invalidate_tlbs = kgd_gfx_v9_invalidate_tlbs, 286 .invalidate_tlbs_vmid = kgd_gfx_v9_invalidate_tlbs_vmid, 287 .get_hive_id = amdgpu_amdkfd_get_hive_id, 288 }; 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