1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <linux/mmu_notifier.h> 33 #include <kgd_kfd_interface.h> 34 #include <drm/ttm/ttm_execbuf_util.h> 35 #include "amdgpu_sync.h" 36 #include "amdgpu_vm.h" 37 38 extern uint64_t amdgpu_amdkfd_total_mem_size; 39 40 enum TLB_FLUSH_TYPE { 41 TLB_FLUSH_LEGACY = 0, 42 TLB_FLUSH_LIGHTWEIGHT, 43 TLB_FLUSH_HEAVYWEIGHT 44 }; 45 46 struct amdgpu_device; 47 48 enum kfd_mem_attachment_type { 49 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 50 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 51 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 52 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 53 }; 54 55 struct kfd_mem_attachment { 56 struct list_head list; 57 enum kfd_mem_attachment_type type; 58 bool is_mapped; 59 struct amdgpu_bo_va *bo_va; 60 struct amdgpu_device *adev; 61 uint64_t va; 62 uint64_t pte_flags; 63 }; 64 65 struct kgd_mem { 66 struct mutex lock; 67 struct amdgpu_bo *bo; 68 struct dma_buf *dmabuf; 69 struct hmm_range *range; 70 struct list_head attachments; 71 /* protected by amdkfd_process_info.lock */ 72 struct ttm_validate_buffer validate_list; 73 struct ttm_validate_buffer resv_list; 74 uint32_t domain; 75 unsigned int mapped_to_gpu_memory; 76 uint64_t va; 77 78 uint32_t alloc_flags; 79 80 uint32_t invalid; 81 struct amdkfd_process_info *process_info; 82 83 struct amdgpu_sync sync; 84 85 bool aql_queue; 86 bool is_imported; 87 }; 88 89 /* KFD Memory Eviction */ 90 struct amdgpu_amdkfd_fence { 91 struct dma_fence base; 92 struct mm_struct *mm; 93 spinlock_t lock; 94 char timeline_name[TASK_COMM_LEN]; 95 struct svm_range_bo *svm_bo; 96 }; 97 98 struct amdgpu_kfd_dev { 99 struct kfd_dev *dev; 100 int64_t vram_used; 101 uint64_t vram_used_aligned; 102 bool init_complete; 103 struct work_struct reset_work; 104 }; 105 106 enum kgd_engine_type { 107 KGD_ENGINE_PFP = 1, 108 KGD_ENGINE_ME, 109 KGD_ENGINE_CE, 110 KGD_ENGINE_MEC1, 111 KGD_ENGINE_MEC2, 112 KGD_ENGINE_RLC, 113 KGD_ENGINE_SDMA1, 114 KGD_ENGINE_SDMA2, 115 KGD_ENGINE_MAX 116 }; 117 118 119 struct amdkfd_process_info { 120 /* List head of all VMs that belong to a KFD process */ 121 struct list_head vm_list_head; 122 /* List head for all KFD BOs that belong to a KFD process. */ 123 struct list_head kfd_bo_list; 124 /* List of userptr BOs that are valid or invalid */ 125 struct list_head userptr_valid_list; 126 struct list_head userptr_inval_list; 127 /* Lock to protect kfd_bo_list */ 128 struct mutex lock; 129 130 /* Number of VMs */ 131 unsigned int n_vms; 132 /* Eviction Fence */ 133 struct amdgpu_amdkfd_fence *eviction_fence; 134 135 /* MMU-notifier related fields */ 136 struct mutex notifier_lock; 137 uint32_t evicted_bos; 138 struct delayed_work restore_userptr_work; 139 struct pid *pid; 140 bool block_mmu_notifications; 141 }; 142 143 int amdgpu_amdkfd_init(void); 144 void amdgpu_amdkfd_fini(void); 145 146 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 147 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); 148 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 149 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 150 const void *ih_ring_entry); 151 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 152 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 153 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 154 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 155 enum kgd_engine_type engine, 156 uint32_t vmid, uint64_t gpu_addr, 157 uint32_t *ib_cmd, uint32_t ib_len); 158 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 159 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 160 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 161 uint16_t vmid); 162 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 163 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type); 164 165 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 166 167 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 168 169 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 170 171 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 172 173 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 174 int queue_bit); 175 176 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 177 struct mm_struct *mm, 178 struct svm_range_bo *svm_bo); 179 #if defined(CONFIG_DEBUG_FS) 180 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 181 #endif 182 #if IS_ENABLED(CONFIG_HSA_AMD) 183 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 184 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 185 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 186 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 187 unsigned long cur_seq, struct kgd_mem *mem); 188 #else 189 static inline 190 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 191 { 192 return false; 193 } 194 195 static inline 196 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 197 { 198 return NULL; 199 } 200 201 static inline 202 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 203 { 204 return 0; 205 } 206 207 static inline 208 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 209 unsigned long cur_seq, struct kgd_mem *mem) 210 { 211 return 0; 212 } 213 #endif 214 /* Shared API */ 215 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 216 void **mem_obj, uint64_t *gpu_addr, 217 void **cpu_ptr, bool mqd_gfx9); 218 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj); 219 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 220 void **mem_obj); 221 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 222 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 223 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 224 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 225 enum kgd_engine_type type); 226 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 227 struct kfd_local_mem_info *mem_info); 228 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 229 230 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 231 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, 232 struct kfd_cu_info *cu_info); 233 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 234 struct amdgpu_device **dmabuf_adev, 235 uint64_t *bo_size, void *metadata_buffer, 236 size_t buffer_size, uint32_t *metadata_size, 237 uint32_t *flags); 238 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 239 struct amdgpu_device *src); 240 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 241 struct amdgpu_device *src, 242 bool is_min); 243 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 244 245 /* Read user wptr from a specified user address space with page fault 246 * disabled. The memory must be pinned and mapped to the hardware when 247 * this is called in hqd_load functions, so it should never fault in 248 * the first place. This resolves a circular lock dependency involving 249 * four locks, including the DQM lock and mmap_lock. 250 */ 251 #define read_user_wptr(mmptr, wptr, dst) \ 252 ({ \ 253 bool valid = false; \ 254 if ((mmptr) && (wptr)) { \ 255 pagefault_disable(); \ 256 if ((mmptr) == current->mm) { \ 257 valid = !get_user((dst), (wptr)); \ 258 } else if (current->flags & PF_KTHREAD) { \ 259 kthread_use_mm(mmptr); \ 260 valid = !get_user((dst), (wptr)); \ 261 kthread_unuse_mm(mmptr); \ 262 } \ 263 pagefault_enable(); \ 264 } \ 265 valid; \ 266 }) 267 268 /* GPUVM API */ 269 #define drm_priv_to_vm(drm_priv) \ 270 (&((struct amdgpu_fpriv *) \ 271 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 272 273 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev, 274 struct amdgpu_vm *avm, u32 pasid); 275 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 276 struct amdgpu_vm *avm, 277 void **process_info, 278 struct dma_fence **ef); 279 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 280 void *drm_priv); 281 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 282 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev); 283 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 284 struct amdgpu_device *adev, uint64_t va, uint64_t size, 285 void *drm_priv, struct kgd_mem **mem, 286 uint64_t *offset, uint32_t flags, bool criu_resume); 287 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 288 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 289 uint64_t *size); 290 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 291 struct kgd_mem *mem, void *drm_priv); 292 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 293 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 294 int amdgpu_amdkfd_gpuvm_sync_memory( 295 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 296 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 297 void **kptr, uint64_t *size); 298 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 299 300 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo); 301 302 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 303 struct dma_fence **ef); 304 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 305 struct kfd_vm_fault_info *info); 306 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 307 struct dma_buf *dmabuf, 308 uint64_t va, void *drm_priv, 309 struct kgd_mem **mem, uint64_t *size, 310 uint64_t *mmap_offset); 311 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 312 struct dma_buf **dmabuf); 313 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 314 struct tile_config *config); 315 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 316 bool reset); 317 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem); 318 void amdgpu_amdkfd_block_mmu_notifications(void *p); 319 int amdgpu_amdkfd_criu_resume(void *p); 320 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev); 321 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 322 uint64_t size, u32 alloc_flag); 323 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 324 uint64_t size, u32 alloc_flag); 325 326 #if IS_ENABLED(CONFIG_HSA_AMD) 327 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 328 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 329 struct amdgpu_vm *vm); 330 331 /** 332 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 333 * 334 * Allows KFD to release its resources associated with the GEM object. 335 */ 336 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 337 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 338 #else 339 static inline 340 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 341 { 342 } 343 344 static inline 345 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 346 struct amdgpu_vm *vm) 347 { 348 } 349 350 static inline 351 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 352 { 353 } 354 #endif 355 /* KGD2KFD callbacks */ 356 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 357 int kgd2kfd_resume_mm(struct mm_struct *mm); 358 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 359 struct dma_fence *fence); 360 #if IS_ENABLED(CONFIG_HSA_AMD) 361 int kgd2kfd_init(void); 362 void kgd2kfd_exit(void); 363 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 364 bool kgd2kfd_device_init(struct kfd_dev *kfd, 365 const struct kgd2kfd_shared_resources *gpu_resources); 366 void kgd2kfd_device_exit(struct kfd_dev *kfd); 367 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 368 int kgd2kfd_resume_iommu(struct kfd_dev *kfd); 369 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 370 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 371 int kgd2kfd_post_reset(struct kfd_dev *kfd); 372 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 373 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 374 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 375 #else 376 static inline int kgd2kfd_init(void) 377 { 378 return -ENOENT; 379 } 380 381 static inline void kgd2kfd_exit(void) 382 { 383 } 384 385 static inline 386 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 387 { 388 return NULL; 389 } 390 391 static inline 392 bool kgd2kfd_device_init(struct kfd_dev *kfd, 393 const struct kgd2kfd_shared_resources *gpu_resources) 394 { 395 return false; 396 } 397 398 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 399 { 400 } 401 402 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 403 { 404 } 405 406 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) 407 { 408 return 0; 409 } 410 411 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 412 { 413 return 0; 414 } 415 416 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 417 { 418 return 0; 419 } 420 421 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 422 { 423 return 0; 424 } 425 426 static inline 427 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 428 { 429 } 430 431 static inline 432 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 433 { 434 } 435 436 static inline 437 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 438 { 439 } 440 #endif 441 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 442