1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <linux/mmu_notifier.h> 33 #include <linux/memremap.h> 34 #include <kgd_kfd_interface.h> 35 #include <drm/ttm/ttm_execbuf_util.h> 36 #include "amdgpu_sync.h" 37 #include "amdgpu_vm.h" 38 #include "amdgpu_xcp.h" 39 40 extern uint64_t amdgpu_amdkfd_total_mem_size; 41 42 enum TLB_FLUSH_TYPE { 43 TLB_FLUSH_LEGACY = 0, 44 TLB_FLUSH_LIGHTWEIGHT, 45 TLB_FLUSH_HEAVYWEIGHT 46 }; 47 48 struct amdgpu_device; 49 50 enum kfd_mem_attachment_type { 51 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 52 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 53 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 54 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 55 }; 56 57 struct kfd_mem_attachment { 58 struct list_head list; 59 enum kfd_mem_attachment_type type; 60 bool is_mapped; 61 struct amdgpu_bo_va *bo_va; 62 struct amdgpu_device *adev; 63 uint64_t va; 64 uint64_t pte_flags; 65 }; 66 67 struct kgd_mem { 68 struct mutex lock; 69 struct amdgpu_bo *bo; 70 struct dma_buf *dmabuf; 71 struct hmm_range *range; 72 struct list_head attachments; 73 /* protected by amdkfd_process_info.lock */ 74 struct ttm_validate_buffer validate_list; 75 struct ttm_validate_buffer resv_list; 76 uint32_t domain; 77 unsigned int mapped_to_gpu_memory; 78 uint64_t va; 79 80 uint32_t alloc_flags; 81 82 uint32_t invalid; 83 struct amdkfd_process_info *process_info; 84 85 struct amdgpu_sync sync; 86 87 bool aql_queue; 88 bool is_imported; 89 }; 90 91 /* KFD Memory Eviction */ 92 struct amdgpu_amdkfd_fence { 93 struct dma_fence base; 94 struct mm_struct *mm; 95 spinlock_t lock; 96 char timeline_name[TASK_COMM_LEN]; 97 struct svm_range_bo *svm_bo; 98 }; 99 100 struct amdgpu_kfd_dev { 101 struct kfd_dev *dev; 102 int64_t vram_used[MAX_XCP]; 103 uint64_t vram_used_aligned[MAX_XCP]; 104 bool init_complete; 105 struct work_struct reset_work; 106 107 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */ 108 struct dev_pagemap pgmap; 109 }; 110 111 enum kgd_engine_type { 112 KGD_ENGINE_PFP = 1, 113 KGD_ENGINE_ME, 114 KGD_ENGINE_CE, 115 KGD_ENGINE_MEC1, 116 KGD_ENGINE_MEC2, 117 KGD_ENGINE_RLC, 118 KGD_ENGINE_SDMA1, 119 KGD_ENGINE_SDMA2, 120 KGD_ENGINE_MAX 121 }; 122 123 124 struct amdkfd_process_info { 125 /* List head of all VMs that belong to a KFD process */ 126 struct list_head vm_list_head; 127 /* List head for all KFD BOs that belong to a KFD process. */ 128 struct list_head kfd_bo_list; 129 /* List of userptr BOs that are valid or invalid */ 130 struct list_head userptr_valid_list; 131 struct list_head userptr_inval_list; 132 /* Lock to protect kfd_bo_list */ 133 struct mutex lock; 134 135 /* Number of VMs */ 136 unsigned int n_vms; 137 /* Eviction Fence */ 138 struct amdgpu_amdkfd_fence *eviction_fence; 139 140 /* MMU-notifier related fields */ 141 struct mutex notifier_lock; 142 uint32_t evicted_bos; 143 struct delayed_work restore_userptr_work; 144 struct pid *pid; 145 bool block_mmu_notifications; 146 }; 147 148 int amdgpu_amdkfd_init(void); 149 void amdgpu_amdkfd_fini(void); 150 151 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 152 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); 153 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 154 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 155 const void *ih_ring_entry); 156 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 157 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 158 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 159 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev); 160 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev); 161 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 162 enum kgd_engine_type engine, 163 uint32_t vmid, uint64_t gpu_addr, 164 uint32_t *ib_cmd, uint32_t ib_len); 165 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 166 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 167 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 168 uint16_t vmid); 169 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 170 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type, 171 uint32_t inst); 172 173 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 174 175 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 176 177 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 178 179 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 180 181 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 182 int queue_bit); 183 184 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 185 struct mm_struct *mm, 186 struct svm_range_bo *svm_bo); 187 #if defined(CONFIG_DEBUG_FS) 188 int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); 189 #endif 190 #if IS_ENABLED(CONFIG_HSA_AMD) 191 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 192 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 193 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 194 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 195 unsigned long cur_seq, struct kgd_mem *mem); 196 #else 197 static inline 198 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 199 { 200 return false; 201 } 202 203 static inline 204 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 205 { 206 return NULL; 207 } 208 209 static inline 210 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 211 { 212 return 0; 213 } 214 215 static inline 216 int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, 217 unsigned long cur_seq, struct kgd_mem *mem) 218 { 219 return 0; 220 } 221 #endif 222 /* Shared API */ 223 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 224 void **mem_obj, uint64_t *gpu_addr, 225 void **cpu_ptr, bool mqd_gfx9); 226 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj); 227 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 228 void **mem_obj); 229 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 230 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 231 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 232 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 233 enum kgd_engine_type type); 234 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 235 struct kfd_local_mem_info *mem_info, 236 struct amdgpu_xcp *xcp); 237 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 238 239 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 240 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, 241 struct kfd_cu_info *cu_info); 242 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 243 struct amdgpu_device **dmabuf_adev, 244 uint64_t *bo_size, void *metadata_buffer, 245 size_t buffer_size, uint32_t *metadata_size, 246 uint32_t *flags, int8_t *xcp_id); 247 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 248 struct amdgpu_device *src); 249 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 250 struct amdgpu_device *src, 251 bool is_min); 252 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 253 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 254 uint32_t *payload); 255 256 /* Read user wptr from a specified user address space with page fault 257 * disabled. The memory must be pinned and mapped to the hardware when 258 * this is called in hqd_load functions, so it should never fault in 259 * the first place. This resolves a circular lock dependency involving 260 * four locks, including the DQM lock and mmap_lock. 261 */ 262 #define read_user_wptr(mmptr, wptr, dst) \ 263 ({ \ 264 bool valid = false; \ 265 if ((mmptr) && (wptr)) { \ 266 pagefault_disable(); \ 267 if ((mmptr) == current->mm) { \ 268 valid = !get_user((dst), (wptr)); \ 269 } else if (current->flags & PF_KTHREAD) { \ 270 kthread_use_mm(mmptr); \ 271 valid = !get_user((dst), (wptr)); \ 272 kthread_unuse_mm(mmptr); \ 273 } \ 274 pagefault_enable(); \ 275 } \ 276 valid; \ 277 }) 278 279 /* GPUVM API */ 280 #define drm_priv_to_vm(drm_priv) \ 281 (&((struct amdgpu_fpriv *) \ 282 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 283 284 int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev, 285 struct amdgpu_vm *avm, u32 pasid); 286 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 287 struct amdgpu_vm *avm, 288 void **process_info, 289 struct dma_fence **ef); 290 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 291 void *drm_priv); 292 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 293 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, 294 uint8_t xcp_id); 295 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 296 struct amdgpu_device *adev, uint64_t va, uint64_t size, 297 void *drm_priv, struct kgd_mem **mem, 298 uint64_t *offset, uint32_t flags, bool criu_resume); 299 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 300 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 301 uint64_t *size); 302 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 303 struct kgd_mem *mem, void *drm_priv); 304 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 305 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 306 int amdgpu_amdkfd_gpuvm_sync_memory( 307 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 308 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 309 void **kptr, uint64_t *size); 310 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 311 312 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo); 313 314 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 315 struct dma_fence **ef); 316 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 317 struct kfd_vm_fault_info *info); 318 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 319 struct dma_buf *dmabuf, 320 uint64_t va, void *drm_priv, 321 struct kgd_mem **mem, uint64_t *size, 322 uint64_t *mmap_offset); 323 int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, 324 struct dma_buf **dmabuf); 325 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); 326 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 327 struct tile_config *config); 328 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 329 bool reset); 330 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem); 331 void amdgpu_amdkfd_block_mmu_notifications(void *p); 332 int amdgpu_amdkfd_criu_resume(void *p); 333 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev); 334 int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, 335 uint64_t size, u32 alloc_flag, int8_t xcp_id); 336 void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, 337 uint64_t size, u32 alloc_flag, int8_t xcp_id); 338 339 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id); 340 341 #define KFD_XCP_MEM_ID(adev, xcp_id) \ 342 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\ 343 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1) 344 345 #define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id)) 346 347 348 #if IS_ENABLED(CONFIG_HSA_AMD) 349 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 350 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 351 struct amdgpu_vm *vm); 352 353 /** 354 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 355 * 356 * Allows KFD to release its resources associated with the GEM object. 357 */ 358 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 359 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 360 #else 361 static inline 362 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 363 { 364 } 365 366 static inline 367 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 368 struct amdgpu_vm *vm) 369 { 370 } 371 372 static inline 373 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 374 { 375 } 376 #endif 377 378 #if IS_ENABLED(CONFIG_HSA_AMD_SVM) 379 int kgd2kfd_init_zone_device(struct amdgpu_device *adev); 380 #else 381 static inline 382 int kgd2kfd_init_zone_device(struct amdgpu_device *adev) 383 { 384 return 0; 385 } 386 #endif 387 388 /* KGD2KFD callbacks */ 389 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 390 int kgd2kfd_resume_mm(struct mm_struct *mm); 391 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 392 struct dma_fence *fence); 393 #if IS_ENABLED(CONFIG_HSA_AMD) 394 int kgd2kfd_init(void); 395 void kgd2kfd_exit(void); 396 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 397 bool kgd2kfd_device_init(struct kfd_dev *kfd, 398 const struct kgd2kfd_shared_resources *gpu_resources); 399 void kgd2kfd_device_exit(struct kfd_dev *kfd); 400 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 401 int kgd2kfd_resume_iommu(struct kfd_dev *kfd); 402 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 403 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 404 int kgd2kfd_post_reset(struct kfd_dev *kfd); 405 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 406 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 407 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 408 int kgd2kfd_check_and_lock_kfd(void); 409 void kgd2kfd_unlock_kfd(void); 410 #else 411 static inline int kgd2kfd_init(void) 412 { 413 return -ENOENT; 414 } 415 416 static inline void kgd2kfd_exit(void) 417 { 418 } 419 420 static inline 421 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 422 { 423 return NULL; 424 } 425 426 static inline 427 bool kgd2kfd_device_init(struct kfd_dev *kfd, 428 const struct kgd2kfd_shared_resources *gpu_resources) 429 { 430 return false; 431 } 432 433 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 434 { 435 } 436 437 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 438 { 439 } 440 441 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) 442 { 443 return 0; 444 } 445 446 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 447 { 448 return 0; 449 } 450 451 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 452 { 453 return 0; 454 } 455 456 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 457 { 458 return 0; 459 } 460 461 static inline 462 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 463 { 464 } 465 466 static inline 467 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 468 { 469 } 470 471 static inline 472 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 473 { 474 } 475 476 static inline int kgd2kfd_check_and_lock_kfd(void) 477 { 478 return 0; 479 } 480 481 static inline void kgd2kfd_unlock_kfd(void) 482 { 483 } 484 #endif 485 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 486