1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <kgd_kfd_interface.h> 33 #include <drm/ttm/ttm_execbuf_util.h> 34 #include "amdgpu_sync.h" 35 #include "amdgpu_vm.h" 36 37 extern uint64_t amdgpu_amdkfd_total_mem_size; 38 39 struct amdgpu_device; 40 41 struct kfd_bo_va_list { 42 struct list_head bo_list; 43 struct amdgpu_bo_va *bo_va; 44 void *kgd_dev; 45 bool is_mapped; 46 uint64_t va; 47 uint64_t pte_flags; 48 }; 49 50 struct kgd_mem { 51 struct mutex lock; 52 struct amdgpu_bo *bo; 53 struct list_head bo_va_list; 54 /* protected by amdkfd_process_info.lock */ 55 struct ttm_validate_buffer validate_list; 56 struct ttm_validate_buffer resv_list; 57 uint32_t domain; 58 unsigned int mapped_to_gpu_memory; 59 uint64_t va; 60 61 uint32_t alloc_flags; 62 63 atomic_t invalid; 64 struct amdkfd_process_info *process_info; 65 66 struct amdgpu_sync sync; 67 68 bool aql_queue; 69 bool is_imported; 70 }; 71 72 /* KFD Memory Eviction */ 73 struct amdgpu_amdkfd_fence { 74 struct dma_fence base; 75 struct mm_struct *mm; 76 spinlock_t lock; 77 char timeline_name[TASK_COMM_LEN]; 78 }; 79 80 struct amdgpu_kfd_dev { 81 struct kfd_dev *dev; 82 uint64_t vram_used; 83 }; 84 85 enum kgd_engine_type { 86 KGD_ENGINE_PFP = 1, 87 KGD_ENGINE_ME, 88 KGD_ENGINE_CE, 89 KGD_ENGINE_MEC1, 90 KGD_ENGINE_MEC2, 91 KGD_ENGINE_RLC, 92 KGD_ENGINE_SDMA1, 93 KGD_ENGINE_SDMA2, 94 KGD_ENGINE_MAX 95 }; 96 97 98 struct amdkfd_process_info { 99 /* List head of all VMs that belong to a KFD process */ 100 struct list_head vm_list_head; 101 /* List head for all KFD BOs that belong to a KFD process. */ 102 struct list_head kfd_bo_list; 103 /* List of userptr BOs that are valid or invalid */ 104 struct list_head userptr_valid_list; 105 struct list_head userptr_inval_list; 106 /* Lock to protect kfd_bo_list */ 107 struct mutex lock; 108 109 /* Number of VMs */ 110 unsigned int n_vms; 111 /* Eviction Fence */ 112 struct amdgpu_amdkfd_fence *eviction_fence; 113 114 /* MMU-notifier related fields */ 115 atomic_t evicted_bos; 116 struct delayed_work restore_userptr_work; 117 struct pid *pid; 118 }; 119 120 int amdgpu_amdkfd_init(void); 121 void amdgpu_amdkfd_fini(void); 122 123 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 124 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 125 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 126 const void *ih_ring_entry); 127 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 128 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 129 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev); 130 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 131 uint32_t vmid, uint64_t gpu_addr, 132 uint32_t *ib_cmd, uint32_t ib_len); 133 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle); 134 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd); 135 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid); 136 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid); 137 138 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 139 140 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 141 142 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 143 144 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd); 145 146 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 147 int queue_bit); 148 149 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 150 struct mm_struct *mm); 151 #if IS_ENABLED(CONFIG_HSA_AMD) 152 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 153 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 154 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 155 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); 156 #else 157 static inline 158 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 159 { 160 return false; 161 } 162 163 static inline 164 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 165 { 166 return NULL; 167 } 168 169 static inline 170 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 171 { 172 return 0; 173 } 174 175 static inline 176 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 177 { 178 return 0; 179 } 180 #endif 181 /* Shared API */ 182 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 183 void **mem_obj, uint64_t *gpu_addr, 184 void **cpu_ptr, bool mqd_gfx9); 185 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); 186 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj); 187 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj); 188 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 189 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 190 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 191 enum kgd_engine_type type); 192 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 193 struct kfd_local_mem_info *mem_info); 194 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd); 195 196 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd); 197 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); 198 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 199 struct kgd_dev **dmabuf_kgd, 200 uint64_t *bo_size, void *metadata_buffer, 201 size_t buffer_size, uint32_t *metadata_size, 202 uint32_t *flags); 203 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd); 204 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd); 205 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd); 206 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); 207 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd); 208 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd); 209 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd); 210 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src); 211 212 /* Read user wptr from a specified user address space with page fault 213 * disabled. The memory must be pinned and mapped to the hardware when 214 * this is called in hqd_load functions, so it should never fault in 215 * the first place. This resolves a circular lock dependency involving 216 * four locks, including the DQM lock and mmap_lock. 217 */ 218 #define read_user_wptr(mmptr, wptr, dst) \ 219 ({ \ 220 bool valid = false; \ 221 if ((mmptr) && (wptr)) { \ 222 pagefault_disable(); \ 223 if ((mmptr) == current->mm) { \ 224 valid = !get_user((dst), (wptr)); \ 225 } else if (current->flags & PF_KTHREAD) { \ 226 kthread_use_mm(mmptr); \ 227 valid = !get_user((dst), (wptr)); \ 228 kthread_unuse_mm(mmptr); \ 229 } \ 230 pagefault_enable(); \ 231 } \ 232 valid; \ 233 }) 234 235 /* GPUVM API */ 236 int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, u32 pasid, 237 void **vm, void **process_info, 238 struct dma_fence **ef); 239 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, 240 struct file *filp, u32 pasid, 241 void **vm, void **process_info, 242 struct dma_fence **ef); 243 void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm); 244 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *vm); 245 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm); 246 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 247 struct kgd_dev *kgd, uint64_t va, uint64_t size, 248 void *vm, struct kgd_mem **mem, 249 uint64_t *offset, uint32_t flags); 250 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 251 struct kgd_dev *kgd, struct kgd_mem *mem, uint64_t *size); 252 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 253 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm); 254 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 255 struct kgd_dev *kgd, struct kgd_mem *mem, void *vm); 256 int amdgpu_amdkfd_gpuvm_sync_memory( 257 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr); 258 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, 259 struct kgd_mem *mem, void **kptr, uint64_t *size); 260 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 261 struct dma_fence **ef); 262 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, 263 struct kfd_vm_fault_info *info); 264 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, 265 struct dma_buf *dmabuf, 266 uint64_t va, void *vm, 267 struct kgd_mem **mem, uint64_t *size, 268 uint64_t *mmap_offset); 269 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 270 struct tile_config *config); 271 #if IS_ENABLED(CONFIG_HSA_AMD) 272 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 273 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 274 struct amdgpu_vm *vm); 275 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); 276 #else 277 static inline 278 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 279 { 280 } 281 282 static inline 283 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 284 struct amdgpu_vm *vm) 285 { 286 } 287 288 static inline 289 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) 290 { 291 } 292 #endif 293 /* KGD2KFD callbacks */ 294 int kgd2kfd_quiesce_mm(struct mm_struct *mm); 295 int kgd2kfd_resume_mm(struct mm_struct *mm); 296 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 297 struct dma_fence *fence); 298 #if IS_ENABLED(CONFIG_HSA_AMD) 299 int kgd2kfd_init(void); 300 void kgd2kfd_exit(void); 301 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 302 unsigned int asic_type, bool vf); 303 bool kgd2kfd_device_init(struct kfd_dev *kfd, 304 struct drm_device *ddev, 305 const struct kgd2kfd_shared_resources *gpu_resources); 306 void kgd2kfd_device_exit(struct kfd_dev *kfd); 307 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 308 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 309 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 310 int kgd2kfd_post_reset(struct kfd_dev *kfd); 311 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 312 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 313 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask); 314 #else 315 static inline int kgd2kfd_init(void) 316 { 317 return -ENOENT; 318 } 319 320 static inline void kgd2kfd_exit(void) 321 { 322 } 323 324 static inline 325 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 326 unsigned int asic_type, bool vf) 327 { 328 return NULL; 329 } 330 331 static inline 332 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, 333 const struct kgd2kfd_shared_resources *gpu_resources) 334 { 335 return false; 336 } 337 338 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 339 { 340 } 341 342 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 343 { 344 } 345 346 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 347 { 348 return 0; 349 } 350 351 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 352 { 353 return 0; 354 } 355 356 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 357 { 358 return 0; 359 } 360 361 static inline 362 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 363 { 364 } 365 366 static inline 367 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 368 { 369 } 370 371 static inline 372 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) 373 { 374 } 375 #endif 376 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 377