1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <kgd_kfd_interface.h> 33 #include <drm/ttm/ttm_execbuf_util.h> 34 #include "amdgpu_sync.h" 35 #include "amdgpu_vm.h" 36 37 extern uint64_t amdgpu_amdkfd_total_mem_size; 38 39 enum TLB_FLUSH_TYPE { 40 TLB_FLUSH_LEGACY = 0, 41 TLB_FLUSH_LIGHTWEIGHT, 42 TLB_FLUSH_HEAVYWEIGHT 43 }; 44 45 struct amdgpu_device; 46 47 enum kfd_mem_attachment_type { 48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */ 49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */ 50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */ 51 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */ 52 }; 53 54 struct kfd_mem_attachment { 55 struct list_head list; 56 enum kfd_mem_attachment_type type; 57 bool is_mapped; 58 struct amdgpu_bo_va *bo_va; 59 struct amdgpu_device *adev; 60 uint64_t va; 61 uint64_t pte_flags; 62 }; 63 64 struct kgd_mem { 65 struct mutex lock; 66 struct amdgpu_bo *bo; 67 struct dma_buf *dmabuf; 68 struct list_head attachments; 69 /* protected by amdkfd_process_info.lock */ 70 struct ttm_validate_buffer validate_list; 71 struct ttm_validate_buffer resv_list; 72 uint32_t domain; 73 unsigned int mapped_to_gpu_memory; 74 uint64_t va; 75 76 uint32_t alloc_flags; 77 78 atomic_t invalid; 79 struct amdkfd_process_info *process_info; 80 81 struct amdgpu_sync sync; 82 83 bool aql_queue; 84 bool is_imported; 85 }; 86 87 /* KFD Memory Eviction */ 88 struct amdgpu_amdkfd_fence { 89 struct dma_fence base; 90 struct mm_struct *mm; 91 spinlock_t lock; 92 char timeline_name[TASK_COMM_LEN]; 93 struct svm_range_bo *svm_bo; 94 }; 95 96 struct amdgpu_kfd_dev { 97 struct kfd_dev *dev; 98 uint64_t vram_used; 99 bool init_complete; 100 struct work_struct reset_work; 101 }; 102 103 enum kgd_engine_type { 104 KGD_ENGINE_PFP = 1, 105 KGD_ENGINE_ME, 106 KGD_ENGINE_CE, 107 KGD_ENGINE_MEC1, 108 KGD_ENGINE_MEC2, 109 KGD_ENGINE_RLC, 110 KGD_ENGINE_SDMA1, 111 KGD_ENGINE_SDMA2, 112 KGD_ENGINE_MAX 113 }; 114 115 116 struct amdkfd_process_info { 117 /* List head of all VMs that belong to a KFD process */ 118 struct list_head vm_list_head; 119 /* List head for all KFD BOs that belong to a KFD process. */ 120 struct list_head kfd_bo_list; 121 /* List of userptr BOs that are valid or invalid */ 122 struct list_head userptr_valid_list; 123 struct list_head userptr_inval_list; 124 /* Lock to protect kfd_bo_list */ 125 struct mutex lock; 126 127 /* Number of VMs */ 128 unsigned int n_vms; 129 /* Eviction Fence */ 130 struct amdgpu_amdkfd_fence *eviction_fence; 131 132 /* MMU-notifier related fields */ 133 atomic_t evicted_bos; 134 struct delayed_work restore_userptr_work; 135 struct pid *pid; 136 bool block_mmu_notifications; 137 }; 138 139 int amdgpu_amdkfd_init(void); 140 void amdgpu_amdkfd_fini(void); 141 142 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 143 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev); 144 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 145 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 146 const void *ih_ring_entry); 147 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 148 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 149 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev); 150 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 151 enum kgd_engine_type engine, 152 uint32_t vmid, uint64_t gpu_addr, 153 uint32_t *ib_cmd, uint32_t ib_len); 154 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); 155 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); 156 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 157 uint16_t vmid); 158 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 159 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type); 160 161 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 162 163 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 164 165 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 166 167 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev); 168 169 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 170 int queue_bit); 171 172 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 173 struct mm_struct *mm, 174 struct svm_range_bo *svm_bo); 175 #if IS_ENABLED(CONFIG_HSA_AMD) 176 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 177 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 178 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 179 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); 180 #else 181 static inline 182 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 183 { 184 return false; 185 } 186 187 static inline 188 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 189 { 190 return NULL; 191 } 192 193 static inline 194 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 195 { 196 return 0; 197 } 198 199 static inline 200 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 201 { 202 return 0; 203 } 204 #endif 205 /* Shared API */ 206 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 207 void **mem_obj, uint64_t *gpu_addr, 208 void **cpu_ptr, bool mqd_gfx9); 209 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj); 210 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 211 void **mem_obj); 212 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj); 213 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 214 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 215 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 216 enum kgd_engine_type type); 217 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 218 struct kfd_local_mem_info *mem_info); 219 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev); 220 221 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev); 222 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, 223 struct kfd_cu_info *cu_info); 224 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 225 struct amdgpu_device **dmabuf_adev, 226 uint64_t *bo_size, void *metadata_buffer, 227 size_t buffer_size, uint32_t *metadata_size, 228 uint32_t *flags); 229 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 230 struct amdgpu_device *src); 231 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 232 struct amdgpu_device *src, 233 bool is_min); 234 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min); 235 236 /* Read user wptr from a specified user address space with page fault 237 * disabled. The memory must be pinned and mapped to the hardware when 238 * this is called in hqd_load functions, so it should never fault in 239 * the first place. This resolves a circular lock dependency involving 240 * four locks, including the DQM lock and mmap_lock. 241 */ 242 #define read_user_wptr(mmptr, wptr, dst) \ 243 ({ \ 244 bool valid = false; \ 245 if ((mmptr) && (wptr)) { \ 246 pagefault_disable(); \ 247 if ((mmptr) == current->mm) { \ 248 valid = !get_user((dst), (wptr)); \ 249 } else if (current->flags & PF_KTHREAD) { \ 250 kthread_use_mm(mmptr); \ 251 valid = !get_user((dst), (wptr)); \ 252 kthread_unuse_mm(mmptr); \ 253 } \ 254 pagefault_enable(); \ 255 } \ 256 valid; \ 257 }) 258 259 /* GPUVM API */ 260 #define drm_priv_to_vm(drm_priv) \ 261 (&((struct amdgpu_fpriv *) \ 262 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 263 264 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev, 265 struct file *filp, u32 pasid, 266 void **process_info, 267 struct dma_fence **ef); 268 void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev, 269 void *drm_priv); 270 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 271 size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev); 272 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 273 struct amdgpu_device *adev, uint64_t va, uint64_t size, 274 void *drm_priv, struct kgd_mem **mem, 275 uint64_t *offset, uint32_t flags, bool criu_resume); 276 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 277 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, 278 uint64_t *size); 279 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev, 280 struct kgd_mem *mem, void *drm_priv); 281 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 282 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv); 283 int amdgpu_amdkfd_gpuvm_sync_memory( 284 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr); 285 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem, 286 void **kptr, uint64_t *size); 287 void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); 288 289 int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo); 290 291 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 292 struct dma_fence **ef); 293 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, 294 struct kfd_vm_fault_info *info); 295 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, 296 struct dma_buf *dmabuf, 297 uint64_t va, void *drm_priv, 298 struct kgd_mem **mem, uint64_t *size, 299 uint64_t *mmap_offset); 300 int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, 301 struct tile_config *config); 302 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, 303 bool reset); 304 bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem); 305 void amdgpu_amdkfd_block_mmu_notifications(void *p); 306 int amdgpu_amdkfd_criu_resume(void *p); 307 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev); 308 309 #if IS_ENABLED(CONFIG_HSA_AMD) 310 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 311 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 312 struct amdgpu_vm *vm); 313 314 /** 315 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released 316 * 317 * Allows KFD to release its resources associated with the GEM object. 318 */ 319 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo); 320 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 321 #else 322 static inline 323 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 324 { 325 } 326 327 static inline 328 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 329 struct amdgpu_vm *vm) 330 { 331 } 332 333 static inline 334 void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) 335 { 336 } 337 #endif 338 /* KGD2KFD callbacks */ 339 int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); 340 int kgd2kfd_resume_mm(struct mm_struct *mm); 341 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 342 struct dma_fence *fence); 343 #if IS_ENABLED(CONFIG_HSA_AMD) 344 int kgd2kfd_init(void); 345 void kgd2kfd_exit(void); 346 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); 347 bool kgd2kfd_device_init(struct kfd_dev *kfd, 348 struct drm_device *ddev, 349 const struct kgd2kfd_shared_resources *gpu_resources); 350 void kgd2kfd_device_exit(struct kfd_dev *kfd); 351 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 352 int kgd2kfd_resume_iommu(struct kfd_dev *kfd); 353 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 354 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 355 int kgd2kfd_post_reset(struct kfd_dev *kfd); 356 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 357 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 358 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); 359 #else 360 static inline int kgd2kfd_init(void) 361 { 362 return -ENOENT; 363 } 364 365 static inline void kgd2kfd_exit(void) 366 { 367 } 368 369 static inline 370 struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf) 371 { 372 return NULL; 373 } 374 375 static inline 376 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, 377 const struct kgd2kfd_shared_resources *gpu_resources) 378 { 379 return false; 380 } 381 382 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 383 { 384 } 385 386 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 387 { 388 } 389 390 static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd) 391 { 392 return 0; 393 } 394 395 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 396 { 397 return 0; 398 } 399 400 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 401 { 402 return 0; 403 } 404 405 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 406 { 407 return 0; 408 } 409 410 static inline 411 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 412 { 413 } 414 415 static inline 416 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 417 { 418 } 419 420 static inline 421 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) 422 { 423 } 424 #endif 425 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 426