1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 /* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */ 24 25 #ifndef AMDGPU_AMDKFD_H_INCLUDED 26 #define AMDGPU_AMDKFD_H_INCLUDED 27 28 #include <linux/types.h> 29 #include <linux/mm.h> 30 #include <linux/kthread.h> 31 #include <linux/workqueue.h> 32 #include <kgd_kfd_interface.h> 33 #include <drm/ttm/ttm_execbuf_util.h> 34 #include "amdgpu_sync.h" 35 #include "amdgpu_vm.h" 36 37 extern uint64_t amdgpu_amdkfd_total_mem_size; 38 39 enum TLB_FLUSH_TYPE { 40 TLB_FLUSH_LEGACY = 0, 41 TLB_FLUSH_LIGHTWEIGHT, 42 TLB_FLUSH_HEAVYWEIGHT 43 }; 44 45 struct amdgpu_device; 46 47 struct kfd_bo_va_list { 48 struct list_head bo_list; 49 struct amdgpu_bo_va *bo_va; 50 void *kgd_dev; 51 bool is_mapped; 52 uint64_t va; 53 uint64_t pte_flags; 54 }; 55 56 struct kgd_mem { 57 struct mutex lock; 58 struct amdgpu_bo *bo; 59 struct list_head bo_va_list; 60 /* protected by amdkfd_process_info.lock */ 61 struct ttm_validate_buffer validate_list; 62 struct ttm_validate_buffer resv_list; 63 uint32_t domain; 64 unsigned int mapped_to_gpu_memory; 65 uint64_t va; 66 67 uint32_t alloc_flags; 68 69 atomic_t invalid; 70 struct amdkfd_process_info *process_info; 71 72 struct amdgpu_sync sync; 73 74 bool aql_queue; 75 bool is_imported; 76 }; 77 78 /* KFD Memory Eviction */ 79 struct amdgpu_amdkfd_fence { 80 struct dma_fence base; 81 struct mm_struct *mm; 82 spinlock_t lock; 83 char timeline_name[TASK_COMM_LEN]; 84 struct svm_range_bo *svm_bo; 85 }; 86 87 struct amdgpu_kfd_dev { 88 struct kfd_dev *dev; 89 uint64_t vram_used; 90 bool init_complete; 91 }; 92 93 enum kgd_engine_type { 94 KGD_ENGINE_PFP = 1, 95 KGD_ENGINE_ME, 96 KGD_ENGINE_CE, 97 KGD_ENGINE_MEC1, 98 KGD_ENGINE_MEC2, 99 KGD_ENGINE_RLC, 100 KGD_ENGINE_SDMA1, 101 KGD_ENGINE_SDMA2, 102 KGD_ENGINE_MAX 103 }; 104 105 106 struct amdkfd_process_info { 107 /* List head of all VMs that belong to a KFD process */ 108 struct list_head vm_list_head; 109 /* List head for all KFD BOs that belong to a KFD process. */ 110 struct list_head kfd_bo_list; 111 /* List of userptr BOs that are valid or invalid */ 112 struct list_head userptr_valid_list; 113 struct list_head userptr_inval_list; 114 /* Lock to protect kfd_bo_list */ 115 struct mutex lock; 116 117 /* Number of VMs */ 118 unsigned int n_vms; 119 /* Eviction Fence */ 120 struct amdgpu_amdkfd_fence *eviction_fence; 121 122 /* MMU-notifier related fields */ 123 atomic_t evicted_bos; 124 struct delayed_work restore_userptr_work; 125 struct pid *pid; 126 }; 127 128 int amdgpu_amdkfd_init(void); 129 void amdgpu_amdkfd_fini(void); 130 131 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm); 132 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm); 133 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 134 const void *ih_ring_entry); 135 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev); 136 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev); 137 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev); 138 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 139 uint32_t vmid, uint64_t gpu_addr, 140 uint32_t *ib_cmd, uint32_t ib_len); 141 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle); 142 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd); 143 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid); 144 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, 145 enum TLB_FLUSH_TYPE flush_type); 146 147 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); 148 149 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev); 150 151 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev); 152 153 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd); 154 155 int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev, 156 int queue_bit); 157 158 struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context, 159 struct mm_struct *mm, 160 struct svm_range_bo *svm_bo); 161 #if IS_ENABLED(CONFIG_HSA_AMD) 162 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); 163 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); 164 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); 165 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); 166 #else 167 static inline 168 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 169 { 170 return false; 171 } 172 173 static inline 174 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 175 { 176 return NULL; 177 } 178 179 static inline 180 int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) 181 { 182 return 0; 183 } 184 185 static inline 186 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 187 { 188 return 0; 189 } 190 #endif 191 /* Shared API */ 192 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 193 void **mem_obj, uint64_t *gpu_addr, 194 void **cpu_ptr, bool mqd_gfx9); 195 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj); 196 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj); 197 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj); 198 int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem); 199 int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem); 200 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 201 enum kgd_engine_type type); 202 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 203 struct kfd_local_mem_info *mem_info); 204 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd); 205 206 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd); 207 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info); 208 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 209 struct kgd_dev **dmabuf_kgd, 210 uint64_t *bo_size, void *metadata_buffer, 211 size_t buffer_size, uint32_t *metadata_size, 212 uint32_t *flags); 213 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd); 214 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd); 215 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd); 216 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd); 217 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd); 218 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd); 219 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd); 220 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src); 221 222 /* Read user wptr from a specified user address space with page fault 223 * disabled. The memory must be pinned and mapped to the hardware when 224 * this is called in hqd_load functions, so it should never fault in 225 * the first place. This resolves a circular lock dependency involving 226 * four locks, including the DQM lock and mmap_lock. 227 */ 228 #define read_user_wptr(mmptr, wptr, dst) \ 229 ({ \ 230 bool valid = false; \ 231 if ((mmptr) && (wptr)) { \ 232 pagefault_disable(); \ 233 if ((mmptr) == current->mm) { \ 234 valid = !get_user((dst), (wptr)); \ 235 } else if (current->flags & PF_KTHREAD) { \ 236 kthread_use_mm(mmptr); \ 237 valid = !get_user((dst), (wptr)); \ 238 kthread_unuse_mm(mmptr); \ 239 } \ 240 pagefault_enable(); \ 241 } \ 242 valid; \ 243 }) 244 245 /* GPUVM API */ 246 #define drm_priv_to_vm(drm_priv) \ 247 (&((struct amdgpu_fpriv *) \ 248 ((struct drm_file *)(drm_priv))->driver_priv)->vm) 249 250 int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd, 251 struct file *filp, u32 pasid, 252 void **process_info, 253 struct dma_fence **ef); 254 void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv); 255 uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv); 256 int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( 257 struct kgd_dev *kgd, uint64_t va, uint64_t size, 258 void *drm_priv, struct kgd_mem **mem, 259 uint64_t *offset, uint32_t flags); 260 int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( 261 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv, 262 uint64_t *size); 263 int amdgpu_amdkfd_gpuvm_map_memory_to_gpu( 264 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); 265 int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( 266 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv); 267 int amdgpu_amdkfd_gpuvm_sync_memory( 268 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr); 269 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, 270 struct kgd_mem *mem, void **kptr, uint64_t *size); 271 int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, 272 struct dma_fence **ef); 273 int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd, 274 struct kfd_vm_fault_info *info); 275 int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, 276 struct dma_buf *dmabuf, 277 uint64_t va, void *drm_priv, 278 struct kgd_mem **mem, uint64_t *size, 279 uint64_t *mmap_offset); 280 int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd, 281 struct tile_config *config); 282 #if IS_ENABLED(CONFIG_HSA_AMD) 283 void amdgpu_amdkfd_gpuvm_init_mem_limits(void); 284 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 285 struct amdgpu_vm *vm); 286 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo); 287 void amdgpu_amdkfd_reserve_system_mem(uint64_t size); 288 #else 289 static inline 290 void amdgpu_amdkfd_gpuvm_init_mem_limits(void) 291 { 292 } 293 294 static inline 295 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 296 struct amdgpu_vm *vm) 297 { 298 } 299 300 static inline 301 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) 302 { 303 } 304 #endif 305 /* KGD2KFD callbacks */ 306 int kgd2kfd_quiesce_mm(struct mm_struct *mm); 307 int kgd2kfd_resume_mm(struct mm_struct *mm); 308 int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, 309 struct dma_fence *fence); 310 #if IS_ENABLED(CONFIG_HSA_AMD) 311 int kgd2kfd_init(void); 312 void kgd2kfd_exit(void); 313 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 314 unsigned int asic_type, bool vf); 315 bool kgd2kfd_device_init(struct kfd_dev *kfd, 316 struct drm_device *ddev, 317 const struct kgd2kfd_shared_resources *gpu_resources); 318 void kgd2kfd_device_exit(struct kfd_dev *kfd); 319 void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); 320 int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); 321 int kgd2kfd_pre_reset(struct kfd_dev *kfd); 322 int kgd2kfd_post_reset(struct kfd_dev *kfd); 323 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry); 324 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); 325 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask); 326 #else 327 static inline int kgd2kfd_init(void) 328 { 329 return -ENOENT; 330 } 331 332 static inline void kgd2kfd_exit(void) 333 { 334 } 335 336 static inline 337 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 338 unsigned int asic_type, bool vf) 339 { 340 return NULL; 341 } 342 343 static inline 344 bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev, 345 const struct kgd2kfd_shared_resources *gpu_resources) 346 { 347 return false; 348 } 349 350 static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) 351 { 352 } 353 354 static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) 355 { 356 } 357 358 static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) 359 { 360 return 0; 361 } 362 363 static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd) 364 { 365 return 0; 366 } 367 368 static inline int kgd2kfd_post_reset(struct kfd_dev *kfd) 369 { 370 return 0; 371 } 372 373 static inline 374 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 375 { 376 } 377 378 static inline 379 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 380 { 381 } 382 383 static inline 384 void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask) 385 { 386 } 387 #endif 388 #endif /* AMDGPU_AMDKFD_H_INCLUDED */ 389