1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_pcie.h" 25 #include "amd_shared.h" 26 27 #include "amdgpu.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_dma_buf.h" 30 #include <linux/module.h> 31 #include <linux/dma-buf.h> 32 #include "amdgpu_xgmi.h" 33 #include <uapi/linux/kfd_ioctl.h> 34 35 /* Total memory size in system memory and all GPU VRAM. Used to 36 * estimate worst case amount of memory to reserve for page tables 37 */ 38 uint64_t amdgpu_amdkfd_total_mem_size; 39 40 static bool kfd_initialized; 41 42 int amdgpu_amdkfd_init(void) 43 { 44 struct sysinfo si; 45 int ret; 46 47 si_meminfo(&si); 48 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 49 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 50 51 ret = kgd2kfd_init(); 52 amdgpu_amdkfd_gpuvm_init_mem_limits(); 53 kfd_initialized = !ret; 54 55 return ret; 56 } 57 58 void amdgpu_amdkfd_fini(void) 59 { 60 if (kfd_initialized) { 61 kgd2kfd_exit(); 62 kfd_initialized = false; 63 } 64 } 65 66 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 67 { 68 bool vf = amdgpu_sriov_vf(adev); 69 70 if (!kfd_initialized) 71 return; 72 73 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 74 adev->pdev, adev->asic_type, vf); 75 76 if (adev->kfd.dev) 77 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 78 } 79 80 /** 81 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 82 * setup amdkfd 83 * 84 * @adev: amdgpu_device pointer 85 * @aperture_base: output returning doorbell aperture base physical address 86 * @aperture_size: output returning doorbell aperture size in bytes 87 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 88 * 89 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 90 * takes doorbells required for its own rings and reports the setup to amdkfd. 91 * amdgpu reserved doorbells are at the start of the doorbell aperture. 92 */ 93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 94 phys_addr_t *aperture_base, 95 size_t *aperture_size, 96 size_t *start_offset) 97 { 98 /* 99 * The first num_doorbells are used by amdgpu. 100 * amdkfd takes whatever's left in the aperture. 101 */ 102 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 103 *aperture_base = adev->doorbell.base; 104 *aperture_size = adev->doorbell.size; 105 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 106 } else { 107 *aperture_base = 0; 108 *aperture_size = 0; 109 *start_offset = 0; 110 } 111 } 112 113 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 114 { 115 int i; 116 int last_valid_bit; 117 118 if (adev->kfd.dev) { 119 struct kgd2kfd_shared_resources gpu_resources = { 120 .compute_vmid_bitmap = 121 ((1 << AMDGPU_NUM_VMID) - 1) - 122 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 123 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 124 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 125 .gpuvm_size = min(adev->vm_manager.max_pfn 126 << AMDGPU_GPU_PAGE_SHIFT, 127 AMDGPU_GMC_HOLE_START), 128 .drm_render_minor = adev_to_drm(adev)->render->index, 129 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 130 131 }; 132 133 /* this is going to have a few of the MSBs set that we need to 134 * clear 135 */ 136 bitmap_complement(gpu_resources.cp_queue_bitmap, 137 adev->gfx.mec.queue_bitmap, 138 KGD_MAX_QUEUES); 139 140 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 141 * nbits is not compile time constant 142 */ 143 last_valid_bit = 1 /* only first MEC can have compute queues */ 144 * adev->gfx.mec.num_pipe_per_mec 145 * adev->gfx.mec.num_queue_per_pipe; 146 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 147 clear_bit(i, gpu_resources.cp_queue_bitmap); 148 149 amdgpu_doorbell_get_kfd_info(adev, 150 &gpu_resources.doorbell_physical_address, 151 &gpu_resources.doorbell_aperture_size, 152 &gpu_resources.doorbell_start_offset); 153 154 /* Since SOC15, BIF starts to statically use the 155 * lower 12 bits of doorbell addresses for routing 156 * based on settings in registers like 157 * SDMA0_DOORBELL_RANGE etc.. 158 * In order to route a doorbell to CP engine, the lower 159 * 12 bits of its address has to be outside the range 160 * set for SDMA, VCN, and IH blocks. 161 */ 162 if (adev->asic_type >= CHIP_VEGA10) { 163 gpu_resources.non_cp_doorbells_start = 164 adev->doorbell_index.first_non_cp; 165 gpu_resources.non_cp_doorbells_end = 166 adev->doorbell_index.last_non_cp; 167 } 168 169 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 170 adev_to_drm(adev), &gpu_resources); 171 } 172 } 173 174 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 175 { 176 if (adev->kfd.dev) { 177 kgd2kfd_device_exit(adev->kfd.dev); 178 adev->kfd.dev = NULL; 179 } 180 } 181 182 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 183 const void *ih_ring_entry) 184 { 185 if (adev->kfd.dev) 186 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 187 } 188 189 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 190 { 191 if (adev->kfd.dev) 192 kgd2kfd_suspend(adev->kfd.dev, run_pm); 193 } 194 195 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 196 { 197 int r = 0; 198 199 if (adev->kfd.dev) 200 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 201 202 return r; 203 } 204 205 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 206 { 207 int r = 0; 208 209 if (adev->kfd.dev) 210 r = kgd2kfd_pre_reset(adev->kfd.dev); 211 212 return r; 213 } 214 215 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 216 { 217 int r = 0; 218 219 if (adev->kfd.dev) 220 r = kgd2kfd_post_reset(adev->kfd.dev); 221 222 return r; 223 } 224 225 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 226 { 227 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 228 229 if (amdgpu_device_should_recover_gpu(adev)) 230 amdgpu_device_gpu_recover(adev, NULL); 231 } 232 233 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 234 void **mem_obj, uint64_t *gpu_addr, 235 void **cpu_ptr, bool cp_mqd_gfx9) 236 { 237 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 238 struct amdgpu_bo *bo = NULL; 239 struct amdgpu_bo_param bp; 240 int r; 241 void *cpu_ptr_tmp = NULL; 242 243 memset(&bp, 0, sizeof(bp)); 244 bp.size = size; 245 bp.byte_align = PAGE_SIZE; 246 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 247 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 248 bp.type = ttm_bo_type_kernel; 249 bp.resv = NULL; 250 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 251 252 if (cp_mqd_gfx9) 253 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 254 255 r = amdgpu_bo_create(adev, &bp, &bo); 256 if (r) { 257 dev_err(adev->dev, 258 "failed to allocate BO for amdkfd (%d)\n", r); 259 return r; 260 } 261 262 /* map the buffer */ 263 r = amdgpu_bo_reserve(bo, true); 264 if (r) { 265 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 266 goto allocate_mem_reserve_bo_failed; 267 } 268 269 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 270 if (r) { 271 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 272 goto allocate_mem_pin_bo_failed; 273 } 274 275 r = amdgpu_ttm_alloc_gart(&bo->tbo); 276 if (r) { 277 dev_err(adev->dev, "%p bind failed\n", bo); 278 goto allocate_mem_kmap_bo_failed; 279 } 280 281 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 282 if (r) { 283 dev_err(adev->dev, 284 "(%d) failed to map bo to kernel for amdkfd\n", r); 285 goto allocate_mem_kmap_bo_failed; 286 } 287 288 *mem_obj = bo; 289 *gpu_addr = amdgpu_bo_gpu_offset(bo); 290 *cpu_ptr = cpu_ptr_tmp; 291 292 amdgpu_bo_unreserve(bo); 293 294 return 0; 295 296 allocate_mem_kmap_bo_failed: 297 amdgpu_bo_unpin(bo); 298 allocate_mem_pin_bo_failed: 299 amdgpu_bo_unreserve(bo); 300 allocate_mem_reserve_bo_failed: 301 amdgpu_bo_unref(&bo); 302 303 return r; 304 } 305 306 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 307 { 308 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 309 310 amdgpu_bo_reserve(bo, true); 311 amdgpu_bo_kunmap(bo); 312 amdgpu_bo_unpin(bo); 313 amdgpu_bo_unreserve(bo); 314 amdgpu_bo_unref(&(bo)); 315 } 316 317 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 318 void **mem_obj) 319 { 320 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 321 struct amdgpu_bo *bo = NULL; 322 struct amdgpu_bo_user *ubo; 323 struct amdgpu_bo_param bp; 324 int r; 325 326 memset(&bp, 0, sizeof(bp)); 327 bp.size = size; 328 bp.byte_align = 1; 329 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 330 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 331 bp.type = ttm_bo_type_device; 332 bp.resv = NULL; 333 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 334 335 r = amdgpu_bo_create_user(adev, &bp, &ubo); 336 if (r) { 337 dev_err(adev->dev, 338 "failed to allocate gws BO for amdkfd (%d)\n", r); 339 return r; 340 } 341 342 bo = &ubo->bo; 343 *mem_obj = bo; 344 return 0; 345 } 346 347 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 348 { 349 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 350 351 amdgpu_bo_unref(&bo); 352 } 353 354 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 355 enum kgd_engine_type type) 356 { 357 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 358 359 switch (type) { 360 case KGD_ENGINE_PFP: 361 return adev->gfx.pfp_fw_version; 362 363 case KGD_ENGINE_ME: 364 return adev->gfx.me_fw_version; 365 366 case KGD_ENGINE_CE: 367 return adev->gfx.ce_fw_version; 368 369 case KGD_ENGINE_MEC1: 370 return adev->gfx.mec_fw_version; 371 372 case KGD_ENGINE_MEC2: 373 return adev->gfx.mec2_fw_version; 374 375 case KGD_ENGINE_RLC: 376 return adev->gfx.rlc_fw_version; 377 378 case KGD_ENGINE_SDMA1: 379 return adev->sdma.instance[0].fw_version; 380 381 case KGD_ENGINE_SDMA2: 382 return adev->sdma.instance[1].fw_version; 383 384 default: 385 return 0; 386 } 387 388 return 0; 389 } 390 391 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 392 struct kfd_local_mem_info *mem_info) 393 { 394 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 395 396 memset(mem_info, 0, sizeof(*mem_info)); 397 398 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 399 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 400 adev->gmc.visible_vram_size; 401 402 mem_info->vram_width = adev->gmc.vram_width; 403 404 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 405 &adev->gmc.aper_base, 406 mem_info->local_mem_size_public, 407 mem_info->local_mem_size_private); 408 409 if (amdgpu_sriov_vf(adev)) 410 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 411 else if (adev->pm.dpm_enabled) { 412 if (amdgpu_emu_mode == 1) 413 mem_info->mem_clk_max = 0; 414 else 415 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 416 } else 417 mem_info->mem_clk_max = 100; 418 } 419 420 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 421 { 422 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 423 424 if (adev->gfx.funcs->get_gpu_clock_counter) 425 return adev->gfx.funcs->get_gpu_clock_counter(adev); 426 return 0; 427 } 428 429 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 430 { 431 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 432 433 /* the sclk is in quantas of 10kHz */ 434 if (amdgpu_sriov_vf(adev)) 435 return adev->clock.default_sclk / 100; 436 else if (adev->pm.dpm_enabled) 437 return amdgpu_dpm_get_sclk(adev, false) / 100; 438 else 439 return 100; 440 } 441 442 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 443 { 444 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 445 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 446 447 memset(cu_info, 0, sizeof(*cu_info)); 448 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 449 return; 450 451 cu_info->cu_active_number = acu_info.number; 452 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 453 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 454 sizeof(acu_info.bitmap)); 455 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 456 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 457 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 458 cu_info->simd_per_cu = acu_info.simd_per_cu; 459 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 460 cu_info->wave_front_size = acu_info.wave_front_size; 461 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 462 cu_info->lds_size = acu_info.lds_size; 463 } 464 465 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 466 struct kgd_dev **dma_buf_kgd, 467 uint64_t *bo_size, void *metadata_buffer, 468 size_t buffer_size, uint32_t *metadata_size, 469 uint32_t *flags) 470 { 471 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 472 struct dma_buf *dma_buf; 473 struct drm_gem_object *obj; 474 struct amdgpu_bo *bo; 475 uint64_t metadata_flags; 476 int r = -EINVAL; 477 478 dma_buf = dma_buf_get(dma_buf_fd); 479 if (IS_ERR(dma_buf)) 480 return PTR_ERR(dma_buf); 481 482 if (dma_buf->ops != &amdgpu_dmabuf_ops) 483 /* Can't handle non-graphics buffers */ 484 goto out_put; 485 486 obj = dma_buf->priv; 487 if (obj->dev->driver != adev_to_drm(adev)->driver) 488 /* Can't handle buffers from different drivers */ 489 goto out_put; 490 491 adev = drm_to_adev(obj->dev); 492 bo = gem_to_amdgpu_bo(obj); 493 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 494 AMDGPU_GEM_DOMAIN_GTT))) 495 /* Only VRAM and GTT BOs are supported */ 496 goto out_put; 497 498 r = 0; 499 if (dma_buf_kgd) 500 *dma_buf_kgd = (struct kgd_dev *)adev; 501 if (bo_size) 502 *bo_size = amdgpu_bo_size(bo); 503 if (metadata_buffer) 504 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 505 metadata_size, &metadata_flags); 506 if (flags) { 507 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 508 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 509 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 510 511 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 512 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 513 } 514 515 out_put: 516 dma_buf_put(dma_buf); 517 return r; 518 } 519 520 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 521 { 522 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 523 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 524 525 return amdgpu_vram_mgr_usage(vram_man); 526 } 527 528 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 529 { 530 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 531 532 return adev->gmc.xgmi.hive_id; 533 } 534 535 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd) 536 { 537 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 538 539 return adev->unique_id; 540 } 541 542 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 543 { 544 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 545 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 546 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 547 548 if (ret < 0) { 549 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 550 adev->gmc.xgmi.physical_node_id, 551 peer_adev->gmc.xgmi.physical_node_id, ret); 552 ret = 0; 553 } 554 return (uint8_t)ret; 555 } 556 557 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct kgd_dev *dst, struct kgd_dev *src, bool is_min) 558 { 559 struct amdgpu_device *adev = (struct amdgpu_device *)dst, *peer_adev; 560 int num_links; 561 562 if (adev->asic_type != CHIP_ALDEBARAN) 563 return 0; 564 565 if (src) 566 peer_adev = (struct amdgpu_device *)src; 567 568 /* num links returns 0 for indirect peers since indirect route is unknown. */ 569 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 570 if (num_links < 0) { 571 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 572 adev->gmc.xgmi.physical_node_id, 573 peer_adev->gmc.xgmi.physical_node_id, num_links); 574 num_links = 0; 575 } 576 577 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 578 return (num_links * 16 * 25000)/BITS_PER_BYTE; 579 } 580 581 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct kgd_dev *dev, bool is_min) 582 { 583 struct amdgpu_device *adev = (struct amdgpu_device *)dev; 584 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 585 fls(adev->pm.pcie_mlw_mask)) - 1; 586 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 587 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 588 fls(adev->pm.pcie_gen_mask & 589 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 590 uint32_t num_lanes_mask = 1 << num_lanes_shift; 591 uint32_t gen_speed_mask = 1 << gen_speed_shift; 592 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 593 594 switch (num_lanes_mask) { 595 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 596 num_lanes_factor = 1; 597 break; 598 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 599 num_lanes_factor = 2; 600 break; 601 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 602 num_lanes_factor = 4; 603 break; 604 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 605 num_lanes_factor = 8; 606 break; 607 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 608 num_lanes_factor = 12; 609 break; 610 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 611 num_lanes_factor = 16; 612 break; 613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 614 num_lanes_factor = 32; 615 break; 616 } 617 618 switch (gen_speed_mask) { 619 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 620 gen_speed_mbits_factor = 2500; 621 break; 622 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 623 gen_speed_mbits_factor = 5000; 624 break; 625 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 626 gen_speed_mbits_factor = 8000; 627 break; 628 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 629 gen_speed_mbits_factor = 16000; 630 break; 631 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 632 gen_speed_mbits_factor = 32000; 633 break; 634 } 635 636 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 637 } 638 639 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 640 { 641 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 642 643 return adev->rmmio_remap.bus_addr; 644 } 645 646 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 647 { 648 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 649 650 return adev->gds.gws_size; 651 } 652 653 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd) 654 { 655 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 656 657 return adev->rev_id; 658 } 659 660 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd) 661 { 662 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 663 664 return adev->gmc.noretry; 665 } 666 667 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 668 uint32_t vmid, uint64_t gpu_addr, 669 uint32_t *ib_cmd, uint32_t ib_len) 670 { 671 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 672 struct amdgpu_job *job; 673 struct amdgpu_ib *ib; 674 struct amdgpu_ring *ring; 675 struct dma_fence *f = NULL; 676 int ret; 677 678 switch (engine) { 679 case KGD_ENGINE_MEC1: 680 ring = &adev->gfx.compute_ring[0]; 681 break; 682 case KGD_ENGINE_SDMA1: 683 ring = &adev->sdma.instance[0].ring; 684 break; 685 case KGD_ENGINE_SDMA2: 686 ring = &adev->sdma.instance[1].ring; 687 break; 688 default: 689 pr_err("Invalid engine in IB submission: %d\n", engine); 690 ret = -EINVAL; 691 goto err; 692 } 693 694 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 695 if (ret) 696 goto err; 697 698 ib = &job->ibs[0]; 699 memset(ib, 0, sizeof(struct amdgpu_ib)); 700 701 ib->gpu_addr = gpu_addr; 702 ib->ptr = ib_cmd; 703 ib->length_dw = ib_len; 704 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 705 job->vmid = vmid; 706 707 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 708 709 if (ret) { 710 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 711 goto err_ib_sched; 712 } 713 714 ret = dma_fence_wait(f, false); 715 716 err_ib_sched: 717 dma_fence_put(f); 718 amdgpu_job_free(job); 719 err: 720 return ret; 721 } 722 723 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 724 { 725 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 726 727 amdgpu_dpm_switch_power_profile(adev, 728 PP_SMC_POWER_PROFILE_COMPUTE, 729 !idle); 730 } 731 732 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 733 { 734 if (adev->kfd.dev) 735 return vmid >= adev->vm_manager.first_kfd_vmid; 736 737 return false; 738 } 739 740 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) 741 { 742 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 743 744 if (adev->family == AMDGPU_FAMILY_AI) { 745 int i; 746 747 for (i = 0; i < adev->num_vmhubs; i++) 748 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 749 } else { 750 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 751 } 752 753 return 0; 754 } 755 756 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid, 757 enum TLB_FLUSH_TYPE flush_type) 758 { 759 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 760 bool all_hub = false; 761 762 if (adev->family == AMDGPU_FAMILY_AI) 763 all_hub = true; 764 765 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 766 } 767 768 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 769 { 770 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 771 772 return adev->have_atomics_support; 773 } 774