1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include <linux/module.h>
29 
30 const struct kgd2kfd_calls *kgd2kfd;
31 
32 static const unsigned int compute_vmid_bitmap = 0xFF00;
33 
34 int amdgpu_amdkfd_init(void)
35 {
36 	int ret;
37 
38 #ifdef CONFIG_HSA_AMD
39 	ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
40 	if (ret)
41 		kgd2kfd = NULL;
42 	amdgpu_amdkfd_gpuvm_init_mem_limits();
43 #else
44 	kgd2kfd = NULL;
45 	ret = -ENOENT;
46 #endif
47 
48 	return ret;
49 }
50 
51 void amdgpu_amdkfd_fini(void)
52 {
53 	if (kgd2kfd)
54 		kgd2kfd->exit();
55 }
56 
57 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
58 {
59 	const struct kfd2kgd_calls *kfd2kgd;
60 
61 	if (!kgd2kfd)
62 		return;
63 
64 	switch (adev->asic_type) {
65 #ifdef CONFIG_DRM_AMDGPU_CIK
66 	case CHIP_KAVERI:
67 	case CHIP_HAWAII:
68 		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
69 		break;
70 #endif
71 	case CHIP_CARRIZO:
72 	case CHIP_TONGA:
73 	case CHIP_FIJI:
74 	case CHIP_POLARIS10:
75 	case CHIP_POLARIS11:
76 	case CHIP_POLARIS12:
77 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
78 		break;
79 	case CHIP_VEGA10:
80 	case CHIP_VEGA12:
81 	case CHIP_VEGA20:
82 	case CHIP_RAVEN:
83 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
84 		break;
85 	default:
86 		dev_info(adev->dev, "kfd not supported on this ASIC\n");
87 		return;
88 	}
89 
90 	adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
91 				   adev->pdev, kfd2kgd);
92 }
93 
94 /**
95  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
96  *                                setup amdkfd
97  *
98  * @adev: amdgpu_device pointer
99  * @aperture_base: output returning doorbell aperture base physical address
100  * @aperture_size: output returning doorbell aperture size in bytes
101  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
102  *
103  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
104  * takes doorbells required for its own rings and reports the setup to amdkfd.
105  * amdgpu reserved doorbells are at the start of the doorbell aperture.
106  */
107 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
108 					 phys_addr_t *aperture_base,
109 					 size_t *aperture_size,
110 					 size_t *start_offset)
111 {
112 	/*
113 	 * The first num_doorbells are used by amdgpu.
114 	 * amdkfd takes whatever's left in the aperture.
115 	 */
116 	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
117 		*aperture_base = adev->doorbell.base;
118 		*aperture_size = adev->doorbell.size;
119 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
120 	} else {
121 		*aperture_base = 0;
122 		*aperture_size = 0;
123 		*start_offset = 0;
124 	}
125 }
126 
127 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
128 {
129 	int i, n;
130 	int last_valid_bit;
131 	if (adev->kfd) {
132 		struct kgd2kfd_shared_resources gpu_resources = {
133 			.compute_vmid_bitmap = compute_vmid_bitmap,
134 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
135 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
136 			.gpuvm_size = min(adev->vm_manager.max_pfn
137 					  << AMDGPU_GPU_PAGE_SHIFT,
138 					  AMDGPU_GMC_HOLE_START),
139 			.drm_render_minor = adev->ddev->render->index
140 		};
141 
142 		/* this is going to have a few of the MSBs set that we need to
143 		 * clear */
144 		bitmap_complement(gpu_resources.queue_bitmap,
145 				  adev->gfx.mec.queue_bitmap,
146 				  KGD_MAX_QUEUES);
147 
148 		/* remove the KIQ bit as well */
149 		if (adev->gfx.kiq.ring.sched.ready)
150 			clear_bit(amdgpu_gfx_queue_to_bit(adev,
151 							  adev->gfx.kiq.ring.me - 1,
152 							  adev->gfx.kiq.ring.pipe,
153 							  adev->gfx.kiq.ring.queue),
154 				  gpu_resources.queue_bitmap);
155 
156 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
157 		 * nbits is not compile time constant */
158 		last_valid_bit = 1 /* only first MEC can have compute queues */
159 				* adev->gfx.mec.num_pipe_per_mec
160 				* adev->gfx.mec.num_queue_per_pipe;
161 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
162 			clear_bit(i, gpu_resources.queue_bitmap);
163 
164 		amdgpu_doorbell_get_kfd_info(adev,
165 				&gpu_resources.doorbell_physical_address,
166 				&gpu_resources.doorbell_aperture_size,
167 				&gpu_resources.doorbell_start_offset);
168 
169 		if (adev->asic_type < CHIP_VEGA10) {
170 			kgd2kfd->device_init(adev->kfd, &gpu_resources);
171 			return;
172 		}
173 
174 		n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
175 
176 		for (i = 0; i < n; i += 2) {
177 			/* On SOC15 the BIF is involved in routing
178 			 * doorbells using the low 12 bits of the
179 			 * address. Communicate the assignments to
180 			 * KFD. KFD uses two doorbell pages per
181 			 * process in case of 64-bit doorbells so we
182 			 * can use each doorbell assignment twice.
183 			 */
184 			gpu_resources.sdma_doorbell[0][i] =
185 				adev->doorbell_index.sdma_engine0 + (i >> 1);
186 			gpu_resources.sdma_doorbell[0][i+1] =
187 				adev->doorbell_index.sdma_engine0 + 0x200 + (i >> 1);
188 			gpu_resources.sdma_doorbell[1][i] =
189 				adev->doorbell_index.sdma_engine1 + (i >> 1);
190 			gpu_resources.sdma_doorbell[1][i+1] =
191 				adev->doorbell_index.sdma_engine1 + 0x200 + (i >> 1);
192 		}
193 		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
194 		 * SDMA, IH and VCN. So don't use them for the CP.
195 		 */
196 		gpu_resources.reserved_doorbell_mask = 0x1e0;
197 		gpu_resources.reserved_doorbell_val  = 0x0e0;
198 
199 		kgd2kfd->device_init(adev->kfd, &gpu_resources);
200 	}
201 }
202 
203 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
204 {
205 	if (adev->kfd) {
206 		kgd2kfd->device_exit(adev->kfd);
207 		adev->kfd = NULL;
208 	}
209 }
210 
211 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
212 		const void *ih_ring_entry)
213 {
214 	if (adev->kfd)
215 		kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
216 }
217 
218 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
219 {
220 	if (adev->kfd)
221 		kgd2kfd->suspend(adev->kfd);
222 }
223 
224 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
225 {
226 	int r = 0;
227 
228 	if (adev->kfd)
229 		r = kgd2kfd->resume(adev->kfd);
230 
231 	return r;
232 }
233 
234 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
235 {
236 	int r = 0;
237 
238 	if (adev->kfd)
239 		r = kgd2kfd->pre_reset(adev->kfd);
240 
241 	return r;
242 }
243 
244 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
245 {
246 	int r = 0;
247 
248 	if (adev->kfd)
249 		r = kgd2kfd->post_reset(adev->kfd);
250 
251 	return r;
252 }
253 
254 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
255 {
256 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
257 
258 	if (amdgpu_device_should_recover_gpu(adev))
259 		amdgpu_device_gpu_recover(adev, NULL);
260 }
261 
262 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
263 				void **mem_obj, uint64_t *gpu_addr,
264 				void **cpu_ptr, bool mqd_gfx9)
265 {
266 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
267 	struct amdgpu_bo *bo = NULL;
268 	struct amdgpu_bo_param bp;
269 	int r;
270 	void *cpu_ptr_tmp = NULL;
271 
272 	memset(&bp, 0, sizeof(bp));
273 	bp.size = size;
274 	bp.byte_align = PAGE_SIZE;
275 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
276 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
277 	bp.type = ttm_bo_type_kernel;
278 	bp.resv = NULL;
279 
280 	if (mqd_gfx9)
281 		bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
282 
283 	r = amdgpu_bo_create(adev, &bp, &bo);
284 	if (r) {
285 		dev_err(adev->dev,
286 			"failed to allocate BO for amdkfd (%d)\n", r);
287 		return r;
288 	}
289 
290 	/* map the buffer */
291 	r = amdgpu_bo_reserve(bo, true);
292 	if (r) {
293 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
294 		goto allocate_mem_reserve_bo_failed;
295 	}
296 
297 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
298 	if (r) {
299 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
300 		goto allocate_mem_pin_bo_failed;
301 	}
302 
303 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
304 	if (r) {
305 		dev_err(adev->dev, "%p bind failed\n", bo);
306 		goto allocate_mem_kmap_bo_failed;
307 	}
308 
309 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
310 	if (r) {
311 		dev_err(adev->dev,
312 			"(%d) failed to map bo to kernel for amdkfd\n", r);
313 		goto allocate_mem_kmap_bo_failed;
314 	}
315 
316 	*mem_obj = bo;
317 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
318 	*cpu_ptr = cpu_ptr_tmp;
319 
320 	amdgpu_bo_unreserve(bo);
321 
322 	return 0;
323 
324 allocate_mem_kmap_bo_failed:
325 	amdgpu_bo_unpin(bo);
326 allocate_mem_pin_bo_failed:
327 	amdgpu_bo_unreserve(bo);
328 allocate_mem_reserve_bo_failed:
329 	amdgpu_bo_unref(&bo);
330 
331 	return r;
332 }
333 
334 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
335 {
336 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
337 
338 	amdgpu_bo_reserve(bo, true);
339 	amdgpu_bo_kunmap(bo);
340 	amdgpu_bo_unpin(bo);
341 	amdgpu_bo_unreserve(bo);
342 	amdgpu_bo_unref(&(bo));
343 }
344 
345 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
346 				      struct kfd_local_mem_info *mem_info)
347 {
348 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
349 	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
350 					     ~((1ULL << 32) - 1);
351 	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
352 
353 	memset(mem_info, 0, sizeof(*mem_info));
354 	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
355 		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
356 		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
357 				adev->gmc.visible_vram_size;
358 	} else {
359 		mem_info->local_mem_size_public = 0;
360 		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
361 	}
362 	mem_info->vram_width = adev->gmc.vram_width;
363 
364 	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
365 			&adev->gmc.aper_base, &aper_limit,
366 			mem_info->local_mem_size_public,
367 			mem_info->local_mem_size_private);
368 
369 	if (amdgpu_sriov_vf(adev))
370 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
371 	else if (adev->powerplay.pp_funcs)
372 		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
373 	else
374 		mem_info->mem_clk_max = 100;
375 }
376 
377 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
378 {
379 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
380 
381 	if (adev->gfx.funcs->get_gpu_clock_counter)
382 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
383 	return 0;
384 }
385 
386 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
387 {
388 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
389 
390 	/* the sclk is in quantas of 10kHz */
391 	if (amdgpu_sriov_vf(adev))
392 		return adev->clock.default_sclk / 100;
393 	else if (adev->powerplay.pp_funcs)
394 		return amdgpu_dpm_get_sclk(adev, false) / 100;
395 	else
396 		return 100;
397 }
398 
399 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
400 {
401 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
402 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
403 
404 	memset(cu_info, 0, sizeof(*cu_info));
405 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
406 		return;
407 
408 	cu_info->cu_active_number = acu_info.number;
409 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
410 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
411 	       sizeof(acu_info.bitmap));
412 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
413 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
414 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
415 	cu_info->simd_per_cu = acu_info.simd_per_cu;
416 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
417 	cu_info->wave_front_size = acu_info.wave_front_size;
418 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
419 	cu_info->lds_size = acu_info.lds_size;
420 }
421 
422 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
423 {
424 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
425 
426 	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
427 }
428 
429 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
430 {
431 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
432 
433 	return adev->gmc.xgmi.hive_id;
434 }
435 
436 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
437 				uint32_t vmid, uint64_t gpu_addr,
438 				uint32_t *ib_cmd, uint32_t ib_len)
439 {
440 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
441 	struct amdgpu_job *job;
442 	struct amdgpu_ib *ib;
443 	struct amdgpu_ring *ring;
444 	struct dma_fence *f = NULL;
445 	int ret;
446 
447 	switch (engine) {
448 	case KGD_ENGINE_MEC1:
449 		ring = &adev->gfx.compute_ring[0];
450 		break;
451 	case KGD_ENGINE_SDMA1:
452 		ring = &adev->sdma.instance[0].ring;
453 		break;
454 	case KGD_ENGINE_SDMA2:
455 		ring = &adev->sdma.instance[1].ring;
456 		break;
457 	default:
458 		pr_err("Invalid engine in IB submission: %d\n", engine);
459 		ret = -EINVAL;
460 		goto err;
461 	}
462 
463 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
464 	if (ret)
465 		goto err;
466 
467 	ib = &job->ibs[0];
468 	memset(ib, 0, sizeof(struct amdgpu_ib));
469 
470 	ib->gpu_addr = gpu_addr;
471 	ib->ptr = ib_cmd;
472 	ib->length_dw = ib_len;
473 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
474 	job->vmid = vmid;
475 
476 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
477 	if (ret) {
478 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
479 		goto err_ib_sched;
480 	}
481 
482 	ret = dma_fence_wait(f, false);
483 
484 err_ib_sched:
485 	dma_fence_put(f);
486 	amdgpu_job_free(job);
487 err:
488 	return ret;
489 }
490 
491 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
492 {
493 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
494 
495 	amdgpu_dpm_switch_power_profile(adev,
496 					PP_SMC_POWER_PROFILE_COMPUTE, !idle);
497 }
498 
499 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
500 {
501 	if (adev->kfd) {
502 		if ((1 << vmid) & compute_vmid_bitmap)
503 			return true;
504 	}
505 
506 	return false;
507 }
508 
509 #ifndef CONFIG_HSA_AMD
510 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
511 {
512 	return false;
513 }
514 
515 void amdgpu_amdkfd_unreserve_system_memory_limit(struct amdgpu_bo *bo)
516 {
517 }
518 
519 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
520 					struct amdgpu_vm *vm)
521 {
522 }
523 
524 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
525 {
526 	return NULL;
527 }
528 
529 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
530 {
531 	return 0;
532 }
533 
534 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
535 {
536 	return NULL;
537 }
538 
539 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
540 {
541 	return NULL;
542 }
543 
544 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
545 {
546 	return NULL;
547 }
548 #endif
549