1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_shared.h" 25 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "amdgpu_dma_buf.h" 29 #include <linux/module.h> 30 #include <linux/dma-buf.h> 31 #include "amdgpu_xgmi.h" 32 33 static const unsigned int compute_vmid_bitmap = 0xFF00; 34 35 /* Total memory size in system memory and all GPU VRAM. Used to 36 * estimate worst case amount of memory to reserve for page tables 37 */ 38 uint64_t amdgpu_amdkfd_total_mem_size; 39 40 int amdgpu_amdkfd_init(void) 41 { 42 struct sysinfo si; 43 int ret; 44 45 si_meminfo(&si); 46 amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh; 47 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 48 49 #ifdef CONFIG_HSA_AMD 50 ret = kgd2kfd_init(); 51 amdgpu_amdkfd_gpuvm_init_mem_limits(); 52 #else 53 ret = -ENOENT; 54 #endif 55 56 return ret; 57 } 58 59 void amdgpu_amdkfd_fini(void) 60 { 61 kgd2kfd_exit(); 62 } 63 64 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 65 { 66 const struct kfd2kgd_calls *kfd2kgd; 67 68 switch (adev->asic_type) { 69 #ifdef CONFIG_DRM_AMDGPU_CIK 70 case CHIP_KAVERI: 71 case CHIP_HAWAII: 72 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions(); 73 break; 74 #endif 75 case CHIP_CARRIZO: 76 case CHIP_TONGA: 77 case CHIP_FIJI: 78 case CHIP_POLARIS10: 79 case CHIP_POLARIS11: 80 case CHIP_POLARIS12: 81 case CHIP_VEGAM: 82 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions(); 83 break; 84 case CHIP_VEGA10: 85 case CHIP_VEGA12: 86 case CHIP_VEGA20: 87 case CHIP_RAVEN: 88 kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions(); 89 break; 90 case CHIP_ARCTURUS: 91 kfd2kgd = amdgpu_amdkfd_arcturus_get_functions(); 92 break; 93 case CHIP_NAVI10: 94 kfd2kgd = amdgpu_amdkfd_gfx_10_0_get_functions(); 95 break; 96 default: 97 dev_info(adev->dev, "kfd not supported on this ASIC\n"); 98 return; 99 } 100 101 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 102 adev->pdev, kfd2kgd); 103 104 if (adev->kfd.dev) 105 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 106 } 107 108 /** 109 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 110 * setup amdkfd 111 * 112 * @adev: amdgpu_device pointer 113 * @aperture_base: output returning doorbell aperture base physical address 114 * @aperture_size: output returning doorbell aperture size in bytes 115 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 116 * 117 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 118 * takes doorbells required for its own rings and reports the setup to amdkfd. 119 * amdgpu reserved doorbells are at the start of the doorbell aperture. 120 */ 121 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 122 phys_addr_t *aperture_base, 123 size_t *aperture_size, 124 size_t *start_offset) 125 { 126 /* 127 * The first num_doorbells are used by amdgpu. 128 * amdkfd takes whatever's left in the aperture. 129 */ 130 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 131 *aperture_base = adev->doorbell.base; 132 *aperture_size = adev->doorbell.size; 133 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 134 } else { 135 *aperture_base = 0; 136 *aperture_size = 0; 137 *start_offset = 0; 138 } 139 } 140 141 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 142 { 143 int i; 144 int last_valid_bit; 145 146 if (adev->kfd.dev) { 147 struct kgd2kfd_shared_resources gpu_resources = { 148 .compute_vmid_bitmap = compute_vmid_bitmap, 149 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 150 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 151 .gpuvm_size = min(adev->vm_manager.max_pfn 152 << AMDGPU_GPU_PAGE_SHIFT, 153 AMDGPU_GMC_HOLE_START), 154 .drm_render_minor = adev->ddev->render->index, 155 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 156 157 }; 158 159 /* this is going to have a few of the MSBs set that we need to 160 * clear 161 */ 162 bitmap_complement(gpu_resources.queue_bitmap, 163 adev->gfx.mec.queue_bitmap, 164 KGD_MAX_QUEUES); 165 166 /* remove the KIQ bit as well */ 167 if (adev->gfx.kiq.ring.sched.ready) 168 clear_bit(amdgpu_gfx_mec_queue_to_bit(adev, 169 adev->gfx.kiq.ring.me - 1, 170 adev->gfx.kiq.ring.pipe, 171 adev->gfx.kiq.ring.queue), 172 gpu_resources.queue_bitmap); 173 174 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 175 * nbits is not compile time constant 176 */ 177 last_valid_bit = 1 /* only first MEC can have compute queues */ 178 * adev->gfx.mec.num_pipe_per_mec 179 * adev->gfx.mec.num_queue_per_pipe; 180 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 181 clear_bit(i, gpu_resources.queue_bitmap); 182 183 amdgpu_doorbell_get_kfd_info(adev, 184 &gpu_resources.doorbell_physical_address, 185 &gpu_resources.doorbell_aperture_size, 186 &gpu_resources.doorbell_start_offset); 187 188 /* Since SOC15, BIF starts to statically use the 189 * lower 12 bits of doorbell addresses for routing 190 * based on settings in registers like 191 * SDMA0_DOORBELL_RANGE etc.. 192 * In order to route a doorbell to CP engine, the lower 193 * 12 bits of its address has to be outside the range 194 * set for SDMA, VCN, and IH blocks. 195 */ 196 if (adev->asic_type >= CHIP_VEGA10) { 197 gpu_resources.non_cp_doorbells_start = 198 adev->doorbell_index.first_non_cp; 199 gpu_resources.non_cp_doorbells_end = 200 adev->doorbell_index.last_non_cp; 201 } 202 203 kgd2kfd_device_init(adev->kfd.dev, &gpu_resources); 204 } 205 } 206 207 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) 208 { 209 if (adev->kfd.dev) { 210 kgd2kfd_device_exit(adev->kfd.dev); 211 adev->kfd.dev = NULL; 212 } 213 } 214 215 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 216 const void *ih_ring_entry) 217 { 218 if (adev->kfd.dev) 219 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 220 } 221 222 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev) 223 { 224 if (adev->kfd.dev) 225 kgd2kfd_suspend(adev->kfd.dev); 226 } 227 228 int amdgpu_amdkfd_resume(struct amdgpu_device *adev) 229 { 230 int r = 0; 231 232 if (adev->kfd.dev) 233 r = kgd2kfd_resume(adev->kfd.dev); 234 235 return r; 236 } 237 238 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 239 { 240 int r = 0; 241 242 if (adev->kfd.dev) 243 r = kgd2kfd_pre_reset(adev->kfd.dev); 244 245 return r; 246 } 247 248 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 249 { 250 int r = 0; 251 252 if (adev->kfd.dev) 253 r = kgd2kfd_post_reset(adev->kfd.dev); 254 255 return r; 256 } 257 258 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 259 { 260 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 261 262 if (amdgpu_device_should_recover_gpu(adev)) 263 amdgpu_device_gpu_recover(adev, NULL); 264 } 265 266 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 267 void **mem_obj, uint64_t *gpu_addr, 268 void **cpu_ptr, bool mqd_gfx9) 269 { 270 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 271 struct amdgpu_bo *bo = NULL; 272 struct amdgpu_bo_param bp; 273 int r; 274 void *cpu_ptr_tmp = NULL; 275 276 memset(&bp, 0, sizeof(bp)); 277 bp.size = size; 278 bp.byte_align = PAGE_SIZE; 279 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 280 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 281 bp.type = ttm_bo_type_kernel; 282 bp.resv = NULL; 283 284 if (mqd_gfx9) 285 bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9; 286 287 r = amdgpu_bo_create(adev, &bp, &bo); 288 if (r) { 289 dev_err(adev->dev, 290 "failed to allocate BO for amdkfd (%d)\n", r); 291 return r; 292 } 293 294 /* map the buffer */ 295 r = amdgpu_bo_reserve(bo, true); 296 if (r) { 297 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 298 goto allocate_mem_reserve_bo_failed; 299 } 300 301 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 302 if (r) { 303 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 304 goto allocate_mem_pin_bo_failed; 305 } 306 307 r = amdgpu_ttm_alloc_gart(&bo->tbo); 308 if (r) { 309 dev_err(adev->dev, "%p bind failed\n", bo); 310 goto allocate_mem_kmap_bo_failed; 311 } 312 313 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 314 if (r) { 315 dev_err(adev->dev, 316 "(%d) failed to map bo to kernel for amdkfd\n", r); 317 goto allocate_mem_kmap_bo_failed; 318 } 319 320 *mem_obj = bo; 321 *gpu_addr = amdgpu_bo_gpu_offset(bo); 322 *cpu_ptr = cpu_ptr_tmp; 323 324 amdgpu_bo_unreserve(bo); 325 326 return 0; 327 328 allocate_mem_kmap_bo_failed: 329 amdgpu_bo_unpin(bo); 330 allocate_mem_pin_bo_failed: 331 amdgpu_bo_unreserve(bo); 332 allocate_mem_reserve_bo_failed: 333 amdgpu_bo_unref(&bo); 334 335 return r; 336 } 337 338 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 339 { 340 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 341 342 amdgpu_bo_reserve(bo, true); 343 amdgpu_bo_kunmap(bo); 344 amdgpu_bo_unpin(bo); 345 amdgpu_bo_unreserve(bo); 346 amdgpu_bo_unref(&(bo)); 347 } 348 349 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 350 void **mem_obj) 351 { 352 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 353 struct amdgpu_bo *bo = NULL; 354 struct amdgpu_bo_param bp; 355 int r; 356 357 memset(&bp, 0, sizeof(bp)); 358 bp.size = size; 359 bp.byte_align = 1; 360 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 361 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 362 bp.type = ttm_bo_type_device; 363 bp.resv = NULL; 364 365 r = amdgpu_bo_create(adev, &bp, &bo); 366 if (r) { 367 dev_err(adev->dev, 368 "failed to allocate gws BO for amdkfd (%d)\n", r); 369 return r; 370 } 371 372 *mem_obj = bo; 373 return 0; 374 } 375 376 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 377 { 378 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 379 380 amdgpu_bo_unref(&bo); 381 } 382 383 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 384 enum kgd_engine_type type) 385 { 386 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 387 388 switch (type) { 389 case KGD_ENGINE_PFP: 390 return adev->gfx.pfp_fw_version; 391 392 case KGD_ENGINE_ME: 393 return adev->gfx.me_fw_version; 394 395 case KGD_ENGINE_CE: 396 return adev->gfx.ce_fw_version; 397 398 case KGD_ENGINE_MEC1: 399 return adev->gfx.mec_fw_version; 400 401 case KGD_ENGINE_MEC2: 402 return adev->gfx.mec2_fw_version; 403 404 case KGD_ENGINE_RLC: 405 return adev->gfx.rlc_fw_version; 406 407 case KGD_ENGINE_SDMA1: 408 return adev->sdma.instance[0].fw_version; 409 410 case KGD_ENGINE_SDMA2: 411 return adev->sdma.instance[1].fw_version; 412 413 default: 414 return 0; 415 } 416 417 return 0; 418 } 419 420 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 421 struct kfd_local_mem_info *mem_info) 422 { 423 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 424 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask : 425 ~((1ULL << 32) - 1); 426 resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size; 427 428 memset(mem_info, 0, sizeof(*mem_info)); 429 if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) { 430 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 431 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 432 adev->gmc.visible_vram_size; 433 } else { 434 mem_info->local_mem_size_public = 0; 435 mem_info->local_mem_size_private = adev->gmc.real_vram_size; 436 } 437 mem_info->vram_width = adev->gmc.vram_width; 438 439 pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n", 440 &adev->gmc.aper_base, &aper_limit, 441 mem_info->local_mem_size_public, 442 mem_info->local_mem_size_private); 443 444 if (amdgpu_sriov_vf(adev)) 445 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 446 else if (adev->powerplay.pp_funcs) { 447 if (amdgpu_emu_mode == 1) 448 mem_info->mem_clk_max = 0; 449 else 450 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 451 } else 452 mem_info->mem_clk_max = 100; 453 } 454 455 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 456 { 457 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 458 459 if (adev->gfx.funcs->get_gpu_clock_counter) 460 return adev->gfx.funcs->get_gpu_clock_counter(adev); 461 return 0; 462 } 463 464 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 465 { 466 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 467 468 /* the sclk is in quantas of 10kHz */ 469 if (amdgpu_sriov_vf(adev)) 470 return adev->clock.default_sclk / 100; 471 else if (adev->powerplay.pp_funcs) 472 return amdgpu_dpm_get_sclk(adev, false) / 100; 473 else 474 return 100; 475 } 476 477 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 478 { 479 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 480 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 481 482 memset(cu_info, 0, sizeof(*cu_info)); 483 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 484 return; 485 486 cu_info->cu_active_number = acu_info.number; 487 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 488 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 489 sizeof(acu_info.bitmap)); 490 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 491 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 492 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 493 cu_info->simd_per_cu = acu_info.simd_per_cu; 494 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 495 cu_info->wave_front_size = acu_info.wave_front_size; 496 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 497 cu_info->lds_size = acu_info.lds_size; 498 } 499 500 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 501 struct kgd_dev **dma_buf_kgd, 502 uint64_t *bo_size, void *metadata_buffer, 503 size_t buffer_size, uint32_t *metadata_size, 504 uint32_t *flags) 505 { 506 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 507 struct dma_buf *dma_buf; 508 struct drm_gem_object *obj; 509 struct amdgpu_bo *bo; 510 uint64_t metadata_flags; 511 int r = -EINVAL; 512 513 dma_buf = dma_buf_get(dma_buf_fd); 514 if (IS_ERR(dma_buf)) 515 return PTR_ERR(dma_buf); 516 517 if (dma_buf->ops != &amdgpu_dmabuf_ops) 518 /* Can't handle non-graphics buffers */ 519 goto out_put; 520 521 obj = dma_buf->priv; 522 if (obj->dev->driver != adev->ddev->driver) 523 /* Can't handle buffers from different drivers */ 524 goto out_put; 525 526 adev = obj->dev->dev_private; 527 bo = gem_to_amdgpu_bo(obj); 528 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 529 AMDGPU_GEM_DOMAIN_GTT))) 530 /* Only VRAM and GTT BOs are supported */ 531 goto out_put; 532 533 r = 0; 534 if (dma_buf_kgd) 535 *dma_buf_kgd = (struct kgd_dev *)adev; 536 if (bo_size) 537 *bo_size = amdgpu_bo_size(bo); 538 if (metadata_size) 539 *metadata_size = bo->metadata_size; 540 if (metadata_buffer) 541 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 542 metadata_size, &metadata_flags); 543 if (flags) { 544 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 545 ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT; 546 547 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 548 *flags |= ALLOC_MEM_FLAGS_PUBLIC; 549 } 550 551 out_put: 552 dma_buf_put(dma_buf); 553 return r; 554 } 555 556 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 557 { 558 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 559 560 return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]); 561 } 562 563 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 564 { 565 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 566 567 return adev->gmc.xgmi.hive_id; 568 } 569 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 570 { 571 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 572 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 573 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 574 575 if (ret < 0) { 576 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 577 adev->gmc.xgmi.physical_node_id, 578 peer_adev->gmc.xgmi.physical_node_id, ret); 579 ret = 0; 580 } 581 return (uint8_t)ret; 582 } 583 584 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 585 { 586 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 587 588 return adev->rmmio_remap.bus_addr; 589 } 590 591 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 592 { 593 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 594 595 return adev->gds.gws_size; 596 } 597 598 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 599 uint32_t vmid, uint64_t gpu_addr, 600 uint32_t *ib_cmd, uint32_t ib_len) 601 { 602 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 603 struct amdgpu_job *job; 604 struct amdgpu_ib *ib; 605 struct amdgpu_ring *ring; 606 struct dma_fence *f = NULL; 607 int ret; 608 609 switch (engine) { 610 case KGD_ENGINE_MEC1: 611 ring = &adev->gfx.compute_ring[0]; 612 break; 613 case KGD_ENGINE_SDMA1: 614 ring = &adev->sdma.instance[0].ring; 615 break; 616 case KGD_ENGINE_SDMA2: 617 ring = &adev->sdma.instance[1].ring; 618 break; 619 default: 620 pr_err("Invalid engine in IB submission: %d\n", engine); 621 ret = -EINVAL; 622 goto err; 623 } 624 625 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 626 if (ret) 627 goto err; 628 629 ib = &job->ibs[0]; 630 memset(ib, 0, sizeof(struct amdgpu_ib)); 631 632 ib->gpu_addr = gpu_addr; 633 ib->ptr = ib_cmd; 634 ib->length_dw = ib_len; 635 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 636 job->vmid = vmid; 637 638 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 639 if (ret) { 640 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 641 goto err_ib_sched; 642 } 643 644 ret = dma_fence_wait(f, false); 645 646 err_ib_sched: 647 dma_fence_put(f); 648 amdgpu_job_free(job); 649 err: 650 return ret; 651 } 652 653 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 654 { 655 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 656 657 if (adev->powerplay.pp_funcs && 658 adev->powerplay.pp_funcs->switch_power_profile) 659 amdgpu_dpm_switch_power_profile(adev, 660 PP_SMC_POWER_PROFILE_COMPUTE, 661 !idle); 662 } 663 664 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 665 { 666 if (adev->kfd.dev) { 667 if ((1 << vmid) & compute_vmid_bitmap) 668 return true; 669 } 670 671 return false; 672 } 673 674 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 675 { 676 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 677 678 return adev->have_atomics_support; 679 } 680 681 #ifndef CONFIG_HSA_AMD 682 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm) 683 { 684 return false; 685 } 686 687 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo) 688 { 689 } 690 691 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev, 692 struct amdgpu_vm *vm) 693 { 694 } 695 696 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f) 697 { 698 return NULL; 699 } 700 701 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) 702 { 703 return 0; 704 } 705 706 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void) 707 { 708 return NULL; 709 } 710 711 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void) 712 { 713 return NULL; 714 } 715 716 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void) 717 { 718 return NULL; 719 } 720 721 struct kfd2kgd_calls *amdgpu_amdkfd_arcturus_get_functions(void) 722 { 723 return NULL; 724 } 725 726 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_10_0_get_functions(void) 727 { 728 return NULL; 729 } 730 731 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev, 732 const struct kfd2kgd_calls *f2g) 733 { 734 return NULL; 735 } 736 737 bool kgd2kfd_device_init(struct kfd_dev *kfd, 738 const struct kgd2kfd_shared_resources *gpu_resources) 739 { 740 return false; 741 } 742 743 void kgd2kfd_device_exit(struct kfd_dev *kfd) 744 { 745 } 746 747 void kgd2kfd_exit(void) 748 { 749 } 750 751 void kgd2kfd_suspend(struct kfd_dev *kfd) 752 { 753 } 754 755 int kgd2kfd_resume(struct kfd_dev *kfd) 756 { 757 return 0; 758 } 759 760 int kgd2kfd_pre_reset(struct kfd_dev *kfd) 761 { 762 return 0; 763 } 764 765 int kgd2kfd_post_reset(struct kfd_dev *kfd) 766 { 767 return 0; 768 } 769 770 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry) 771 { 772 } 773 774 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd) 775 { 776 } 777 #endif 778