1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <linux/module.h> 32 #include <linux/dma-buf.h> 33 #include "amdgpu_xgmi.h" 34 #include <uapi/linux/kfd_ioctl.h> 35 #include "amdgpu_ras.h" 36 #include "amdgpu_umc.h" 37 #include "amdgpu_reset.h" 38 39 /* Total memory size in system memory and all GPU VRAM. Used to 40 * estimate worst case amount of memory to reserve for page tables 41 */ 42 uint64_t amdgpu_amdkfd_total_mem_size; 43 44 static bool kfd_initialized; 45 46 int amdgpu_amdkfd_init(void) 47 { 48 struct sysinfo si; 49 int ret; 50 51 si_meminfo(&si); 52 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 53 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 54 55 ret = kgd2kfd_init(); 56 kfd_initialized = !ret; 57 58 return ret; 59 } 60 61 void amdgpu_amdkfd_fini(void) 62 { 63 if (kfd_initialized) { 64 kgd2kfd_exit(); 65 kfd_initialized = false; 66 } 67 } 68 69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 70 { 71 bool vf = amdgpu_sriov_vf(adev); 72 73 if (!kfd_initialized) 74 return; 75 76 adev->kfd.dev = kgd2kfd_probe(adev, vf); 77 } 78 79 /** 80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 81 * setup amdkfd 82 * 83 * @adev: amdgpu_device pointer 84 * @aperture_base: output returning doorbell aperture base physical address 85 * @aperture_size: output returning doorbell aperture size in bytes 86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 87 * 88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 89 * takes doorbells required for its own rings and reports the setup to amdkfd. 90 * amdgpu reserved doorbells are at the start of the doorbell aperture. 91 */ 92 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 93 phys_addr_t *aperture_base, 94 size_t *aperture_size, 95 size_t *start_offset) 96 { 97 /* 98 * The first num_kernel_doorbells are used by amdgpu. 99 * amdkfd takes whatever's left in the aperture. 100 */ 101 if (adev->enable_mes) { 102 /* 103 * With MES enabled, we only need to initialize 104 * the base address. The size and offset are 105 * not initialized as AMDGPU manages the whole 106 * doorbell space. 107 */ 108 *aperture_base = adev->doorbell.base; 109 *aperture_size = 0; 110 *start_offset = 0; 111 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 112 sizeof(u32)) { 113 *aperture_base = adev->doorbell.base; 114 *aperture_size = adev->doorbell.size; 115 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 116 } else { 117 *aperture_base = 0; 118 *aperture_size = 0; 119 *start_offset = 0; 120 } 121 } 122 123 124 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 125 { 126 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 127 kfd.reset_work); 128 129 struct amdgpu_reset_context reset_context; 130 131 memset(&reset_context, 0, sizeof(reset_context)); 132 133 reset_context.method = AMD_RESET_METHOD_NONE; 134 reset_context.reset_req_dev = adev; 135 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 136 137 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 138 } 139 140 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 141 { 142 int i; 143 int last_valid_bit; 144 145 amdgpu_amdkfd_gpuvm_init_mem_limits(); 146 147 if (adev->kfd.dev) { 148 struct kgd2kfd_shared_resources gpu_resources = { 149 .compute_vmid_bitmap = 150 ((1 << AMDGPU_NUM_VMID) - 1) - 151 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 152 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 153 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 154 .gpuvm_size = min(adev->vm_manager.max_pfn 155 << AMDGPU_GPU_PAGE_SHIFT, 156 AMDGPU_GMC_HOLE_START), 157 .drm_render_minor = adev_to_drm(adev)->render->index, 158 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 159 .enable_mes = adev->enable_mes, 160 }; 161 162 /* this is going to have a few of the MSBs set that we need to 163 * clear 164 */ 165 bitmap_complement(gpu_resources.cp_queue_bitmap, 166 adev->gfx.mec_bitmap[0].queue_bitmap, 167 KGD_MAX_QUEUES); 168 169 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 170 * nbits is not compile time constant 171 */ 172 last_valid_bit = 1 /* only first MEC can have compute queues */ 173 * adev->gfx.mec.num_pipe_per_mec 174 * adev->gfx.mec.num_queue_per_pipe; 175 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 176 clear_bit(i, gpu_resources.cp_queue_bitmap); 177 178 amdgpu_doorbell_get_kfd_info(adev, 179 &gpu_resources.doorbell_physical_address, 180 &gpu_resources.doorbell_aperture_size, 181 &gpu_resources.doorbell_start_offset); 182 183 /* Since SOC15, BIF starts to statically use the 184 * lower 12 bits of doorbell addresses for routing 185 * based on settings in registers like 186 * SDMA0_DOORBELL_RANGE etc.. 187 * In order to route a doorbell to CP engine, the lower 188 * 12 bits of its address has to be outside the range 189 * set for SDMA, VCN, and IH blocks. 190 */ 191 if (adev->asic_type >= CHIP_VEGA10) { 192 gpu_resources.non_cp_doorbells_start = 193 adev->doorbell_index.first_non_cp; 194 gpu_resources.non_cp_doorbells_end = 195 adev->doorbell_index.last_non_cp; 196 } 197 198 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 199 &gpu_resources); 200 201 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 202 203 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 204 } 205 } 206 207 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 208 { 209 if (adev->kfd.dev) { 210 kgd2kfd_device_exit(adev->kfd.dev); 211 adev->kfd.dev = NULL; 212 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 213 } 214 } 215 216 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 217 const void *ih_ring_entry) 218 { 219 if (adev->kfd.dev) 220 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 221 } 222 223 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 224 { 225 if (adev->kfd.dev) 226 kgd2kfd_suspend(adev->kfd.dev, run_pm); 227 } 228 229 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 230 { 231 int r = 0; 232 233 if (adev->kfd.dev) 234 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 235 236 return r; 237 } 238 239 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 240 { 241 int r = 0; 242 243 if (adev->kfd.dev) 244 r = kgd2kfd_pre_reset(adev->kfd.dev); 245 246 return r; 247 } 248 249 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 250 { 251 int r = 0; 252 253 if (adev->kfd.dev) 254 r = kgd2kfd_post_reset(adev->kfd.dev); 255 256 return r; 257 } 258 259 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 260 { 261 if (amdgpu_device_should_recover_gpu(adev)) 262 amdgpu_reset_domain_schedule(adev->reset_domain, 263 &adev->kfd.reset_work); 264 } 265 266 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 267 void **mem_obj, uint64_t *gpu_addr, 268 void **cpu_ptr, bool cp_mqd_gfx9) 269 { 270 struct amdgpu_bo *bo = NULL; 271 struct amdgpu_bo_param bp; 272 int r; 273 void *cpu_ptr_tmp = NULL; 274 275 memset(&bp, 0, sizeof(bp)); 276 bp.size = size; 277 bp.byte_align = PAGE_SIZE; 278 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 279 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 280 bp.type = ttm_bo_type_kernel; 281 bp.resv = NULL; 282 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 283 284 if (cp_mqd_gfx9) 285 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 286 287 r = amdgpu_bo_create(adev, &bp, &bo); 288 if (r) { 289 dev_err(adev->dev, 290 "failed to allocate BO for amdkfd (%d)\n", r); 291 return r; 292 } 293 294 /* map the buffer */ 295 r = amdgpu_bo_reserve(bo, true); 296 if (r) { 297 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 298 goto allocate_mem_reserve_bo_failed; 299 } 300 301 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 302 if (r) { 303 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 304 goto allocate_mem_pin_bo_failed; 305 } 306 307 r = amdgpu_ttm_alloc_gart(&bo->tbo); 308 if (r) { 309 dev_err(adev->dev, "%p bind failed\n", bo); 310 goto allocate_mem_kmap_bo_failed; 311 } 312 313 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 314 if (r) { 315 dev_err(adev->dev, 316 "(%d) failed to map bo to kernel for amdkfd\n", r); 317 goto allocate_mem_kmap_bo_failed; 318 } 319 320 *mem_obj = bo; 321 *gpu_addr = amdgpu_bo_gpu_offset(bo); 322 *cpu_ptr = cpu_ptr_tmp; 323 324 amdgpu_bo_unreserve(bo); 325 326 return 0; 327 328 allocate_mem_kmap_bo_failed: 329 amdgpu_bo_unpin(bo); 330 allocate_mem_pin_bo_failed: 331 amdgpu_bo_unreserve(bo); 332 allocate_mem_reserve_bo_failed: 333 amdgpu_bo_unref(&bo); 334 335 return r; 336 } 337 338 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 339 { 340 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 341 342 amdgpu_bo_reserve(bo, true); 343 amdgpu_bo_kunmap(bo); 344 amdgpu_bo_unpin(bo); 345 amdgpu_bo_unreserve(bo); 346 amdgpu_bo_unref(&(bo)); 347 } 348 349 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 350 void **mem_obj) 351 { 352 struct amdgpu_bo *bo = NULL; 353 struct amdgpu_bo_user *ubo; 354 struct amdgpu_bo_param bp; 355 int r; 356 357 memset(&bp, 0, sizeof(bp)); 358 bp.size = size; 359 bp.byte_align = 1; 360 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 361 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 362 bp.type = ttm_bo_type_device; 363 bp.resv = NULL; 364 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 365 366 r = amdgpu_bo_create_user(adev, &bp, &ubo); 367 if (r) { 368 dev_err(adev->dev, 369 "failed to allocate gws BO for amdkfd (%d)\n", r); 370 return r; 371 } 372 373 bo = &ubo->bo; 374 *mem_obj = bo; 375 return 0; 376 } 377 378 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 379 { 380 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 381 382 amdgpu_bo_unref(&bo); 383 } 384 385 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 386 enum kgd_engine_type type) 387 { 388 switch (type) { 389 case KGD_ENGINE_PFP: 390 return adev->gfx.pfp_fw_version; 391 392 case KGD_ENGINE_ME: 393 return adev->gfx.me_fw_version; 394 395 case KGD_ENGINE_CE: 396 return adev->gfx.ce_fw_version; 397 398 case KGD_ENGINE_MEC1: 399 return adev->gfx.mec_fw_version; 400 401 case KGD_ENGINE_MEC2: 402 return adev->gfx.mec2_fw_version; 403 404 case KGD_ENGINE_RLC: 405 return adev->gfx.rlc_fw_version; 406 407 case KGD_ENGINE_SDMA1: 408 return adev->sdma.instance[0].fw_version; 409 410 case KGD_ENGINE_SDMA2: 411 return adev->sdma.instance[1].fw_version; 412 413 default: 414 return 0; 415 } 416 417 return 0; 418 } 419 420 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 421 struct kfd_local_mem_info *mem_info, 422 struct amdgpu_xcp *xcp) 423 { 424 memset(mem_info, 0, sizeof(*mem_info)); 425 426 if (xcp) { 427 if (adev->gmc.real_vram_size == adev->gmc.visible_vram_size) 428 mem_info->local_mem_size_public = 429 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 430 else 431 mem_info->local_mem_size_private = 432 KFD_XCP_MEMORY_SIZE(adev, xcp->id); 433 } else { 434 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 435 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 436 adev->gmc.visible_vram_size; 437 } 438 mem_info->vram_width = adev->gmc.vram_width; 439 440 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 441 &adev->gmc.aper_base, 442 mem_info->local_mem_size_public, 443 mem_info->local_mem_size_private); 444 445 if (amdgpu_sriov_vf(adev)) 446 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 447 else if (adev->pm.dpm_enabled) { 448 if (amdgpu_emu_mode == 1) 449 mem_info->mem_clk_max = 0; 450 else 451 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 452 } else 453 mem_info->mem_clk_max = 100; 454 } 455 456 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 457 { 458 if (adev->gfx.funcs->get_gpu_clock_counter) 459 return adev->gfx.funcs->get_gpu_clock_counter(adev); 460 return 0; 461 } 462 463 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 464 { 465 /* the sclk is in quantas of 10kHz */ 466 if (amdgpu_sriov_vf(adev)) 467 return adev->clock.default_sclk / 100; 468 else if (adev->pm.dpm_enabled) 469 return amdgpu_dpm_get_sclk(adev, false) / 100; 470 else 471 return 100; 472 } 473 474 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info) 475 { 476 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 477 478 memset(cu_info, 0, sizeof(*cu_info)); 479 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 480 return; 481 482 cu_info->cu_active_number = acu_info.number; 483 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 484 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 485 sizeof(acu_info.bitmap)); 486 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 487 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 488 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 489 cu_info->simd_per_cu = acu_info.simd_per_cu; 490 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 491 cu_info->wave_front_size = acu_info.wave_front_size; 492 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 493 cu_info->lds_size = acu_info.lds_size; 494 } 495 496 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 497 struct amdgpu_device **dmabuf_adev, 498 uint64_t *bo_size, void *metadata_buffer, 499 size_t buffer_size, uint32_t *metadata_size, 500 uint32_t *flags, int8_t *xcp_id) 501 { 502 struct dma_buf *dma_buf; 503 struct drm_gem_object *obj; 504 struct amdgpu_bo *bo; 505 uint64_t metadata_flags; 506 int r = -EINVAL; 507 508 dma_buf = dma_buf_get(dma_buf_fd); 509 if (IS_ERR(dma_buf)) 510 return PTR_ERR(dma_buf); 511 512 if (dma_buf->ops != &amdgpu_dmabuf_ops) 513 /* Can't handle non-graphics buffers */ 514 goto out_put; 515 516 obj = dma_buf->priv; 517 if (obj->dev->driver != adev_to_drm(adev)->driver) 518 /* Can't handle buffers from different drivers */ 519 goto out_put; 520 521 adev = drm_to_adev(obj->dev); 522 bo = gem_to_amdgpu_bo(obj); 523 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 524 AMDGPU_GEM_DOMAIN_GTT))) 525 /* Only VRAM and GTT BOs are supported */ 526 goto out_put; 527 528 r = 0; 529 if (dmabuf_adev) 530 *dmabuf_adev = adev; 531 if (bo_size) 532 *bo_size = amdgpu_bo_size(bo); 533 if (metadata_buffer) 534 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 535 metadata_size, &metadata_flags); 536 if (flags) { 537 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 538 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 539 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 540 541 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 542 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 543 } 544 if (xcp_id) 545 *xcp_id = bo->xcp_id; 546 547 out_put: 548 dma_buf_put(dma_buf); 549 return r; 550 } 551 552 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 553 struct amdgpu_device *src) 554 { 555 struct amdgpu_device *peer_adev = src; 556 struct amdgpu_device *adev = dst; 557 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 558 559 if (ret < 0) { 560 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 561 adev->gmc.xgmi.physical_node_id, 562 peer_adev->gmc.xgmi.physical_node_id, ret); 563 ret = 0; 564 } 565 return (uint8_t)ret; 566 } 567 568 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 569 struct amdgpu_device *src, 570 bool is_min) 571 { 572 struct amdgpu_device *adev = dst, *peer_adev; 573 int num_links; 574 575 if (adev->asic_type != CHIP_ALDEBARAN) 576 return 0; 577 578 if (src) 579 peer_adev = src; 580 581 /* num links returns 0 for indirect peers since indirect route is unknown. */ 582 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 583 if (num_links < 0) { 584 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 585 adev->gmc.xgmi.physical_node_id, 586 peer_adev->gmc.xgmi.physical_node_id, num_links); 587 num_links = 0; 588 } 589 590 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 591 return (num_links * 16 * 25000)/BITS_PER_BYTE; 592 } 593 594 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 595 { 596 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 597 fls(adev->pm.pcie_mlw_mask)) - 1; 598 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 599 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 600 fls(adev->pm.pcie_gen_mask & 601 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 602 uint32_t num_lanes_mask = 1 << num_lanes_shift; 603 uint32_t gen_speed_mask = 1 << gen_speed_shift; 604 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 605 606 switch (num_lanes_mask) { 607 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 608 num_lanes_factor = 1; 609 break; 610 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 611 num_lanes_factor = 2; 612 break; 613 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 614 num_lanes_factor = 4; 615 break; 616 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 617 num_lanes_factor = 8; 618 break; 619 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 620 num_lanes_factor = 12; 621 break; 622 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 623 num_lanes_factor = 16; 624 break; 625 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 626 num_lanes_factor = 32; 627 break; 628 } 629 630 switch (gen_speed_mask) { 631 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 632 gen_speed_mbits_factor = 2500; 633 break; 634 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 635 gen_speed_mbits_factor = 5000; 636 break; 637 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 638 gen_speed_mbits_factor = 8000; 639 break; 640 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 641 gen_speed_mbits_factor = 16000; 642 break; 643 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 644 gen_speed_mbits_factor = 32000; 645 break; 646 } 647 648 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 649 } 650 651 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 652 enum kgd_engine_type engine, 653 uint32_t vmid, uint64_t gpu_addr, 654 uint32_t *ib_cmd, uint32_t ib_len) 655 { 656 struct amdgpu_job *job; 657 struct amdgpu_ib *ib; 658 struct amdgpu_ring *ring; 659 struct dma_fence *f = NULL; 660 int ret; 661 662 switch (engine) { 663 case KGD_ENGINE_MEC1: 664 ring = &adev->gfx.compute_ring[0]; 665 break; 666 case KGD_ENGINE_SDMA1: 667 ring = &adev->sdma.instance[0].ring; 668 break; 669 case KGD_ENGINE_SDMA2: 670 ring = &adev->sdma.instance[1].ring; 671 break; 672 default: 673 pr_err("Invalid engine in IB submission: %d\n", engine); 674 ret = -EINVAL; 675 goto err; 676 } 677 678 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 679 if (ret) 680 goto err; 681 682 ib = &job->ibs[0]; 683 memset(ib, 0, sizeof(struct amdgpu_ib)); 684 685 ib->gpu_addr = gpu_addr; 686 ib->ptr = ib_cmd; 687 ib->length_dw = ib_len; 688 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 689 job->vmid = vmid; 690 job->num_ibs = 1; 691 692 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 693 694 if (ret) { 695 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 696 goto err_ib_sched; 697 } 698 699 /* Drop the initial kref_init count (see drm_sched_main as example) */ 700 dma_fence_put(f); 701 ret = dma_fence_wait(f, false); 702 703 err_ib_sched: 704 amdgpu_job_free(job); 705 err: 706 return ret; 707 } 708 709 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 710 { 711 /* Temporary workaround to fix issues observed in some 712 * compute applications when GFXOFF is enabled on GFX11. 713 */ 714 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) { 715 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 716 amdgpu_gfx_off_ctrl(adev, idle); 717 } 718 amdgpu_dpm_switch_power_profile(adev, 719 PP_SMC_POWER_PROFILE_COMPUTE, 720 !idle); 721 } 722 723 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 724 { 725 if (adev->kfd.dev) 726 return vmid >= adev->vm_manager.first_kfd_vmid; 727 728 return false; 729 } 730 731 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 732 uint16_t vmid) 733 { 734 if (adev->family == AMDGPU_FAMILY_AI) { 735 int i; 736 737 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 738 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 739 } else { 740 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0); 741 } 742 743 return 0; 744 } 745 746 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 747 uint16_t pasid, 748 enum TLB_FLUSH_TYPE flush_type, 749 uint32_t inst) 750 { 751 bool all_hub = false; 752 753 if (adev->family == AMDGPU_FAMILY_AI || 754 adev->family == AMDGPU_FAMILY_RV) 755 all_hub = true; 756 757 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst); 758 } 759 760 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 761 { 762 return adev->have_atomics_support; 763 } 764 765 void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev) 766 { 767 amdgpu_device_flush_hdp(adev, NULL); 768 } 769 770 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 771 { 772 amdgpu_umc_poison_handler(adev, reset); 773 } 774 775 int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, 776 uint32_t *payload) 777 { 778 int ret; 779 780 /* Device or IH ring is not ready so bail. */ 781 ret = amdgpu_ih_wait_on_checkpoint_process_ts(adev, &adev->irq.ih); 782 if (ret) 783 return ret; 784 785 /* Send payload to fence KFD interrupts */ 786 amdgpu_amdkfd_interrupt(adev, payload); 787 788 return 0; 789 } 790 791 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 792 { 793 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 794 return adev->gfx.ras->query_utcl2_poison_status(adev); 795 else 796 return false; 797 } 798 799 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 800 { 801 return kgd2kfd_check_and_lock_kfd(); 802 } 803 804 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 805 { 806 kgd2kfd_unlock_kfd(); 807 } 808 809 810 u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id) 811 { 812 u64 tmp; 813 s8 mem_id = KFD_XCP_MEM_ID(adev, xcp_id); 814 815 if (adev->gmc.num_mem_partitions && xcp_id >= 0 && mem_id >= 0) { 816 tmp = adev->gmc.mem_partitions[mem_id].size; 817 do_div(tmp, adev->xcp_mgr->num_xcp_per_mem_partition); 818 return ALIGN_DOWN(tmp, PAGE_SIZE); 819 } else { 820 return adev->gmc.real_vram_size; 821 } 822 } 823 824 int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, 825 u32 inst) 826 { 827 struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst]; 828 struct amdgpu_ring *kiq_ring = &kiq->ring; 829 struct amdgpu_ring_funcs *ring_funcs; 830 struct amdgpu_ring *ring; 831 int r = 0; 832 833 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) 834 return -EINVAL; 835 836 ring_funcs = kzalloc(sizeof(*ring_funcs), GFP_KERNEL); 837 if (!ring_funcs) 838 return -ENOMEM; 839 840 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 841 if (!ring) { 842 r = -ENOMEM; 843 goto free_ring_funcs; 844 } 845 846 ring_funcs->type = AMDGPU_RING_TYPE_COMPUTE; 847 ring->doorbell_index = doorbell_off; 848 ring->funcs = ring_funcs; 849 850 spin_lock(&kiq->ring_lock); 851 852 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { 853 spin_unlock(&kiq->ring_lock); 854 r = -ENOMEM; 855 goto free_ring; 856 } 857 858 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); 859 860 if (kiq_ring->sched.ready && !adev->job_hang) 861 r = amdgpu_ring_test_helper(kiq_ring); 862 863 spin_unlock(&kiq->ring_lock); 864 865 free_ring: 866 kfree(ring); 867 868 free_ring_funcs: 869 kfree(ring_funcs); 870 871 return r; 872 } 873