1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright 2014 Advanced Micro Devices, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include "amdgpu_amdkfd.h"
25 #include "amd_pcie.h"
26 #include "amd_shared.h"
27 
28 #include "amdgpu.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_dma_buf.h"
31 #include <linux/module.h>
32 #include <linux/dma-buf.h>
33 #include "amdgpu_xgmi.h"
34 #include <uapi/linux/kfd_ioctl.h>
35 #include "amdgpu_ras.h"
36 #include "amdgpu_umc.h"
37 #include "amdgpu_reset.h"
38 
39 /* Total memory size in system memory and all GPU VRAM. Used to
40  * estimate worst case amount of memory to reserve for page tables
41  */
42 uint64_t amdgpu_amdkfd_total_mem_size;
43 
44 static bool kfd_initialized;
45 
46 int amdgpu_amdkfd_init(void)
47 {
48 	struct sysinfo si;
49 	int ret;
50 
51 	si_meminfo(&si);
52 	amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
53 	amdgpu_amdkfd_total_mem_size *= si.mem_unit;
54 
55 	ret = kgd2kfd_init();
56 	amdgpu_amdkfd_gpuvm_init_mem_limits();
57 	kfd_initialized = !ret;
58 
59 	return ret;
60 }
61 
62 void amdgpu_amdkfd_fini(void)
63 {
64 	if (kfd_initialized) {
65 		kgd2kfd_exit();
66 		kfd_initialized = false;
67 	}
68 }
69 
70 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
71 {
72 	bool vf = amdgpu_sriov_vf(adev);
73 
74 	if (!kfd_initialized)
75 		return;
76 
77 	adev->kfd.dev = kgd2kfd_probe(adev, vf);
78 }
79 
80 /**
81  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
82  *                                setup amdkfd
83  *
84  * @adev: amdgpu_device pointer
85  * @aperture_base: output returning doorbell aperture base physical address
86  * @aperture_size: output returning doorbell aperture size in bytes
87  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
88  *
89  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
90  * takes doorbells required for its own rings and reports the setup to amdkfd.
91  * amdgpu reserved doorbells are at the start of the doorbell aperture.
92  */
93 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
94 					 phys_addr_t *aperture_base,
95 					 size_t *aperture_size,
96 					 size_t *start_offset)
97 {
98 	/*
99 	 * The first num_doorbells are used by amdgpu.
100 	 * amdkfd takes whatever's left in the aperture.
101 	 */
102 	if (adev->enable_mes) {
103 		/*
104 		 * With MES enabled, we only need to initialize
105 		 * the base address. The size and offset are
106 		 * not initialized as AMDGPU manages the whole
107 		 * doorbell space.
108 		 */
109 		*aperture_base = adev->doorbell.base;
110 		*aperture_size = 0;
111 		*start_offset = 0;
112 	} else if (adev->doorbell.size > adev->doorbell.num_doorbells *
113 						sizeof(u32)) {
114 		*aperture_base = adev->doorbell.base;
115 		*aperture_size = adev->doorbell.size;
116 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
117 	} else {
118 		*aperture_base = 0;
119 		*aperture_size = 0;
120 		*start_offset = 0;
121 	}
122 }
123 
124 
125 static void amdgpu_amdkfd_reset_work(struct work_struct *work)
126 {
127 	struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
128 						  kfd.reset_work);
129 
130 	struct amdgpu_reset_context reset_context;
131 
132 	memset(&reset_context, 0, sizeof(reset_context));
133 
134 	reset_context.method = AMD_RESET_METHOD_NONE;
135 	reset_context.reset_req_dev = adev;
136 	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
137 
138 	amdgpu_device_gpu_recover(adev, NULL, &reset_context);
139 }
140 
141 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
142 {
143 	int i;
144 	int last_valid_bit;
145 
146 	if (adev->kfd.dev) {
147 		struct kgd2kfd_shared_resources gpu_resources = {
148 			.compute_vmid_bitmap =
149 				((1 << AMDGPU_NUM_VMID) - 1) -
150 				((1 << adev->vm_manager.first_kfd_vmid) - 1),
151 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
152 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
153 			.gpuvm_size = min(adev->vm_manager.max_pfn
154 					  << AMDGPU_GPU_PAGE_SHIFT,
155 					  AMDGPU_GMC_HOLE_START),
156 			.drm_render_minor = adev_to_drm(adev)->render->index,
157 			.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
158 			.enable_mes = adev->enable_mes,
159 		};
160 
161 		/* this is going to have a few of the MSBs set that we need to
162 		 * clear
163 		 */
164 		bitmap_complement(gpu_resources.cp_queue_bitmap,
165 				  adev->gfx.mec.queue_bitmap,
166 				  KGD_MAX_QUEUES);
167 
168 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
169 		 * nbits is not compile time constant
170 		 */
171 		last_valid_bit = 1 /* only first MEC can have compute queues */
172 				* adev->gfx.mec.num_pipe_per_mec
173 				* adev->gfx.mec.num_queue_per_pipe;
174 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
175 			clear_bit(i, gpu_resources.cp_queue_bitmap);
176 
177 		amdgpu_doorbell_get_kfd_info(adev,
178 				&gpu_resources.doorbell_physical_address,
179 				&gpu_resources.doorbell_aperture_size,
180 				&gpu_resources.doorbell_start_offset);
181 
182 		/* Since SOC15, BIF starts to statically use the
183 		 * lower 12 bits of doorbell addresses for routing
184 		 * based on settings in registers like
185 		 * SDMA0_DOORBELL_RANGE etc..
186 		 * In order to route a doorbell to CP engine, the lower
187 		 * 12 bits of its address has to be outside the range
188 		 * set for SDMA, VCN, and IH blocks.
189 		 */
190 		if (adev->asic_type >= CHIP_VEGA10) {
191 			gpu_resources.non_cp_doorbells_start =
192 					adev->doorbell_index.first_non_cp;
193 			gpu_resources.non_cp_doorbells_end =
194 					adev->doorbell_index.last_non_cp;
195 		}
196 
197 		adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
198 						adev_to_drm(adev), &gpu_resources);
199 
200 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
201 
202 		INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work);
203 	}
204 }
205 
206 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
207 {
208 	if (adev->kfd.dev) {
209 		kgd2kfd_device_exit(adev->kfd.dev);
210 		adev->kfd.dev = NULL;
211 		amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size;
212 	}
213 }
214 
215 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
216 		const void *ih_ring_entry)
217 {
218 	if (adev->kfd.dev)
219 		kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
220 }
221 
222 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
223 {
224 	if (adev->kfd.dev)
225 		kgd2kfd_suspend(adev->kfd.dev, run_pm);
226 }
227 
228 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
229 {
230 	int r = 0;
231 
232 	if (adev->kfd.dev)
233 		r = kgd2kfd_resume_iommu(adev->kfd.dev);
234 
235 	return r;
236 }
237 
238 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
239 {
240 	int r = 0;
241 
242 	if (adev->kfd.dev)
243 		r = kgd2kfd_resume(adev->kfd.dev, run_pm);
244 
245 	return r;
246 }
247 
248 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
249 {
250 	int r = 0;
251 
252 	if (adev->kfd.dev)
253 		r = kgd2kfd_pre_reset(adev->kfd.dev);
254 
255 	return r;
256 }
257 
258 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
259 {
260 	int r = 0;
261 
262 	if (adev->kfd.dev)
263 		r = kgd2kfd_post_reset(adev->kfd.dev);
264 
265 	return r;
266 }
267 
268 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev)
269 {
270 	if (amdgpu_device_should_recover_gpu(adev))
271 		amdgpu_reset_domain_schedule(adev->reset_domain,
272 					     &adev->kfd.reset_work);
273 }
274 
275 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
276 				void **mem_obj, uint64_t *gpu_addr,
277 				void **cpu_ptr, bool cp_mqd_gfx9)
278 {
279 	struct amdgpu_bo *bo = NULL;
280 	struct amdgpu_bo_param bp;
281 	int r;
282 	void *cpu_ptr_tmp = NULL;
283 
284 	memset(&bp, 0, sizeof(bp));
285 	bp.size = size;
286 	bp.byte_align = PAGE_SIZE;
287 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
288 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
289 	bp.type = ttm_bo_type_kernel;
290 	bp.resv = NULL;
291 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
292 
293 	if (cp_mqd_gfx9)
294 		bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
295 
296 	r = amdgpu_bo_create(adev, &bp, &bo);
297 	if (r) {
298 		dev_err(adev->dev,
299 			"failed to allocate BO for amdkfd (%d)\n", r);
300 		return r;
301 	}
302 
303 	/* map the buffer */
304 	r = amdgpu_bo_reserve(bo, true);
305 	if (r) {
306 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
307 		goto allocate_mem_reserve_bo_failed;
308 	}
309 
310 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
311 	if (r) {
312 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
313 		goto allocate_mem_pin_bo_failed;
314 	}
315 
316 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
317 	if (r) {
318 		dev_err(adev->dev, "%p bind failed\n", bo);
319 		goto allocate_mem_kmap_bo_failed;
320 	}
321 
322 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
323 	if (r) {
324 		dev_err(adev->dev,
325 			"(%d) failed to map bo to kernel for amdkfd\n", r);
326 		goto allocate_mem_kmap_bo_failed;
327 	}
328 
329 	*mem_obj = bo;
330 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
331 	*cpu_ptr = cpu_ptr_tmp;
332 
333 	amdgpu_bo_unreserve(bo);
334 
335 	return 0;
336 
337 allocate_mem_kmap_bo_failed:
338 	amdgpu_bo_unpin(bo);
339 allocate_mem_pin_bo_failed:
340 	amdgpu_bo_unreserve(bo);
341 allocate_mem_reserve_bo_failed:
342 	amdgpu_bo_unref(&bo);
343 
344 	return r;
345 }
346 
347 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj)
348 {
349 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
350 
351 	amdgpu_bo_reserve(bo, true);
352 	amdgpu_bo_kunmap(bo);
353 	amdgpu_bo_unpin(bo);
354 	amdgpu_bo_unreserve(bo);
355 	amdgpu_bo_unref(&(bo));
356 }
357 
358 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
359 				void **mem_obj)
360 {
361 	struct amdgpu_bo *bo = NULL;
362 	struct amdgpu_bo_user *ubo;
363 	struct amdgpu_bo_param bp;
364 	int r;
365 
366 	memset(&bp, 0, sizeof(bp));
367 	bp.size = size;
368 	bp.byte_align = 1;
369 	bp.domain = AMDGPU_GEM_DOMAIN_GWS;
370 	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
371 	bp.type = ttm_bo_type_device;
372 	bp.resv = NULL;
373 	bp.bo_ptr_size = sizeof(struct amdgpu_bo);
374 
375 	r = amdgpu_bo_create_user(adev, &bp, &ubo);
376 	if (r) {
377 		dev_err(adev->dev,
378 			"failed to allocate gws BO for amdkfd (%d)\n", r);
379 		return r;
380 	}
381 
382 	bo = &ubo->bo;
383 	*mem_obj = bo;
384 	return 0;
385 }
386 
387 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj)
388 {
389 	struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
390 
391 	amdgpu_bo_unref(&bo);
392 }
393 
394 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
395 				      enum kgd_engine_type type)
396 {
397 	switch (type) {
398 	case KGD_ENGINE_PFP:
399 		return adev->gfx.pfp_fw_version;
400 
401 	case KGD_ENGINE_ME:
402 		return adev->gfx.me_fw_version;
403 
404 	case KGD_ENGINE_CE:
405 		return adev->gfx.ce_fw_version;
406 
407 	case KGD_ENGINE_MEC1:
408 		return adev->gfx.mec_fw_version;
409 
410 	case KGD_ENGINE_MEC2:
411 		return adev->gfx.mec2_fw_version;
412 
413 	case KGD_ENGINE_RLC:
414 		return adev->gfx.rlc_fw_version;
415 
416 	case KGD_ENGINE_SDMA1:
417 		return adev->sdma.instance[0].fw_version;
418 
419 	case KGD_ENGINE_SDMA2:
420 		return adev->sdma.instance[1].fw_version;
421 
422 	default:
423 		return 0;
424 	}
425 
426 	return 0;
427 }
428 
429 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
430 				      struct kfd_local_mem_info *mem_info)
431 {
432 	memset(mem_info, 0, sizeof(*mem_info));
433 
434 	mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
435 	mem_info->local_mem_size_private = adev->gmc.real_vram_size -
436 						adev->gmc.visible_vram_size;
437 
438 	mem_info->vram_width = adev->gmc.vram_width;
439 
440 	pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
441 			&adev->gmc.aper_base,
442 			mem_info->local_mem_size_public,
443 			mem_info->local_mem_size_private);
444 
445 	if (amdgpu_sriov_vf(adev))
446 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
447 	else if (adev->pm.dpm_enabled) {
448 		if (amdgpu_emu_mode == 1)
449 			mem_info->mem_clk_max = 0;
450 		else
451 			mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
452 	} else
453 		mem_info->mem_clk_max = 100;
454 }
455 
456 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev)
457 {
458 	if (adev->gfx.funcs->get_gpu_clock_counter)
459 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
460 	return 0;
461 }
462 
463 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev)
464 {
465 	/* the sclk is in quantas of 10kHz */
466 	if (amdgpu_sriov_vf(adev))
467 		return adev->clock.default_sclk / 100;
468 	else if (adev->pm.dpm_enabled)
469 		return amdgpu_dpm_get_sclk(adev, false) / 100;
470 	else
471 		return 100;
472 }
473 
474 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info)
475 {
476 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
477 
478 	memset(cu_info, 0, sizeof(*cu_info));
479 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
480 		return;
481 
482 	cu_info->cu_active_number = acu_info.number;
483 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
484 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
485 	       sizeof(acu_info.bitmap));
486 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
487 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
488 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
489 	cu_info->simd_per_cu = acu_info.simd_per_cu;
490 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
491 	cu_info->wave_front_size = acu_info.wave_front_size;
492 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
493 	cu_info->lds_size = acu_info.lds_size;
494 }
495 
496 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
497 				  struct amdgpu_device **dmabuf_adev,
498 				  uint64_t *bo_size, void *metadata_buffer,
499 				  size_t buffer_size, uint32_t *metadata_size,
500 				  uint32_t *flags)
501 {
502 	struct dma_buf *dma_buf;
503 	struct drm_gem_object *obj;
504 	struct amdgpu_bo *bo;
505 	uint64_t metadata_flags;
506 	int r = -EINVAL;
507 
508 	dma_buf = dma_buf_get(dma_buf_fd);
509 	if (IS_ERR(dma_buf))
510 		return PTR_ERR(dma_buf);
511 
512 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
513 		/* Can't handle non-graphics buffers */
514 		goto out_put;
515 
516 	obj = dma_buf->priv;
517 	if (obj->dev->driver != adev_to_drm(adev)->driver)
518 		/* Can't handle buffers from different drivers */
519 		goto out_put;
520 
521 	adev = drm_to_adev(obj->dev);
522 	bo = gem_to_amdgpu_bo(obj);
523 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
524 				    AMDGPU_GEM_DOMAIN_GTT)))
525 		/* Only VRAM and GTT BOs are supported */
526 		goto out_put;
527 
528 	r = 0;
529 	if (dmabuf_adev)
530 		*dmabuf_adev = adev;
531 	if (bo_size)
532 		*bo_size = amdgpu_bo_size(bo);
533 	if (metadata_buffer)
534 		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
535 					   metadata_size, &metadata_flags);
536 	if (flags) {
537 		*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
538 				KFD_IOC_ALLOC_MEM_FLAGS_VRAM
539 				: KFD_IOC_ALLOC_MEM_FLAGS_GTT;
540 
541 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
542 			*flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
543 	}
544 
545 out_put:
546 	dma_buf_put(dma_buf);
547 	return r;
548 }
549 
550 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
551 					  struct amdgpu_device *src)
552 {
553 	struct amdgpu_device *peer_adev = src;
554 	struct amdgpu_device *adev = dst;
555 	int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
556 
557 	if (ret < 0) {
558 		DRM_ERROR("amdgpu: failed to get  xgmi hops count between node %d and %d. ret = %d\n",
559 			adev->gmc.xgmi.physical_node_id,
560 			peer_adev->gmc.xgmi.physical_node_id, ret);
561 		ret = 0;
562 	}
563 	return  (uint8_t)ret;
564 }
565 
566 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
567 					    struct amdgpu_device *src,
568 					    bool is_min)
569 {
570 	struct amdgpu_device *adev = dst, *peer_adev;
571 	int num_links;
572 
573 	if (adev->asic_type != CHIP_ALDEBARAN)
574 		return 0;
575 
576 	if (src)
577 		peer_adev = src;
578 
579 	/* num links returns 0 for indirect peers since indirect route is unknown. */
580 	num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev);
581 	if (num_links < 0) {
582 		DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n",
583 			adev->gmc.xgmi.physical_node_id,
584 			peer_adev->gmc.xgmi.physical_node_id, num_links);
585 		num_links = 0;
586 	}
587 
588 	/* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */
589 	return (num_links * 16 * 25000)/BITS_PER_BYTE;
590 }
591 
592 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min)
593 {
594 	int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) :
595 							fls(adev->pm.pcie_mlw_mask)) - 1;
596 	int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask &
597 						CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) :
598 					fls(adev->pm.pcie_gen_mask &
599 						CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1;
600 	uint32_t num_lanes_mask = 1 << num_lanes_shift;
601 	uint32_t gen_speed_mask = 1 << gen_speed_shift;
602 	int num_lanes_factor = 0, gen_speed_mbits_factor = 0;
603 
604 	switch (num_lanes_mask) {
605 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1:
606 		num_lanes_factor = 1;
607 		break;
608 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2:
609 		num_lanes_factor = 2;
610 		break;
611 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4:
612 		num_lanes_factor = 4;
613 		break;
614 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8:
615 		num_lanes_factor = 8;
616 		break;
617 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12:
618 		num_lanes_factor = 12;
619 		break;
620 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16:
621 		num_lanes_factor = 16;
622 		break;
623 	case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32:
624 		num_lanes_factor = 32;
625 		break;
626 	}
627 
628 	switch (gen_speed_mask) {
629 	case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1:
630 		gen_speed_mbits_factor = 2500;
631 		break;
632 	case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2:
633 		gen_speed_mbits_factor = 5000;
634 		break;
635 	case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3:
636 		gen_speed_mbits_factor = 8000;
637 		break;
638 	case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4:
639 		gen_speed_mbits_factor = 16000;
640 		break;
641 	case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5:
642 		gen_speed_mbits_factor = 32000;
643 		break;
644 	}
645 
646 	return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE;
647 }
648 
649 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
650 				enum kgd_engine_type engine,
651 				uint32_t vmid, uint64_t gpu_addr,
652 				uint32_t *ib_cmd, uint32_t ib_len)
653 {
654 	struct amdgpu_job *job;
655 	struct amdgpu_ib *ib;
656 	struct amdgpu_ring *ring;
657 	struct dma_fence *f = NULL;
658 	int ret;
659 
660 	switch (engine) {
661 	case KGD_ENGINE_MEC1:
662 		ring = &adev->gfx.compute_ring[0];
663 		break;
664 	case KGD_ENGINE_SDMA1:
665 		ring = &adev->sdma.instance[0].ring;
666 		break;
667 	case KGD_ENGINE_SDMA2:
668 		ring = &adev->sdma.instance[1].ring;
669 		break;
670 	default:
671 		pr_err("Invalid engine in IB submission: %d\n", engine);
672 		ret = -EINVAL;
673 		goto err;
674 	}
675 
676 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
677 	if (ret)
678 		goto err;
679 
680 	ib = &job->ibs[0];
681 	memset(ib, 0, sizeof(struct amdgpu_ib));
682 
683 	ib->gpu_addr = gpu_addr;
684 	ib->ptr = ib_cmd;
685 	ib->length_dw = ib_len;
686 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
687 	job->vmid = vmid;
688 	job->num_ibs = 1;
689 
690 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
691 
692 	if (ret) {
693 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
694 		goto err_ib_sched;
695 	}
696 
697 	/* Drop the initial kref_init count (see drm_sched_main as example) */
698 	dma_fence_put(f);
699 	ret = dma_fence_wait(f, false);
700 
701 err_ib_sched:
702 	amdgpu_job_free(job);
703 err:
704 	return ret;
705 }
706 
707 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle)
708 {
709 	/* Temporary workaround to fix issues observed in some
710 	 * compute applications when GFXOFF is enabled on GFX11.
711 	 */
712 	if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) {
713 		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");
714 		amdgpu_gfx_off_ctrl(adev, idle);
715 	}
716 	amdgpu_dpm_switch_power_profile(adev,
717 					PP_SMC_POWER_PROFILE_COMPUTE,
718 					!idle);
719 }
720 
721 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
722 {
723 	if (adev->kfd.dev)
724 		return vmid >= adev->vm_manager.first_kfd_vmid;
725 
726 	return false;
727 }
728 
729 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev,
730 				     uint16_t vmid)
731 {
732 	if (adev->family == AMDGPU_FAMILY_AI) {
733 		int i;
734 
735 		for (i = 0; i < adev->num_vmhubs; i++)
736 			amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
737 	} else {
738 		amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
739 	}
740 
741 	return 0;
742 }
743 
744 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
745 				      uint16_t pasid, enum TLB_FLUSH_TYPE flush_type)
746 {
747 	bool all_hub = false;
748 
749 	if (adev->family == AMDGPU_FAMILY_AI ||
750 	    adev->family == AMDGPU_FAMILY_RV)
751 		all_hub = true;
752 
753 	return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
754 }
755 
756 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev)
757 {
758 	return adev->have_atomics_support;
759 }
760 
761 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset)
762 {
763 	struct ras_err_data err_data = {0, 0, 0, NULL};
764 
765 	amdgpu_umc_poison_handler(adev, &err_data, reset);
766 }
767 
768 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev)
769 {
770 	if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status)
771 		return adev->gfx.ras->query_utcl2_poison_status(adev);
772 	else
773 		return false;
774 }
775