1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include <linux/module.h>
29 #include <linux/dma-buf.h>
30 
31 static const unsigned int compute_vmid_bitmap = 0xFF00;
32 
33 /* Total memory size in system memory and all GPU VRAM. Used to
34  * estimate worst case amount of memory to reserve for page tables
35  */
36 uint64_t amdgpu_amdkfd_total_mem_size;
37 
38 int amdgpu_amdkfd_init(void)
39 {
40 	struct sysinfo si;
41 	int ret;
42 
43 	si_meminfo(&si);
44 	amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
45 	amdgpu_amdkfd_total_mem_size *= si.mem_unit;
46 
47 #ifdef CONFIG_HSA_AMD
48 	ret = kgd2kfd_init();
49 	amdgpu_amdkfd_gpuvm_init_mem_limits();
50 #else
51 	ret = -ENOENT;
52 #endif
53 
54 	return ret;
55 }
56 
57 void amdgpu_amdkfd_fini(void)
58 {
59 	kgd2kfd_exit();
60 }
61 
62 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
63 {
64 	const struct kfd2kgd_calls *kfd2kgd;
65 
66 	switch (adev->asic_type) {
67 #ifdef CONFIG_DRM_AMDGPU_CIK
68 	case CHIP_KAVERI:
69 	case CHIP_HAWAII:
70 		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
71 		break;
72 #endif
73 	case CHIP_CARRIZO:
74 	case CHIP_TONGA:
75 	case CHIP_FIJI:
76 	case CHIP_POLARIS10:
77 	case CHIP_POLARIS11:
78 	case CHIP_POLARIS12:
79 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
80 		break;
81 	case CHIP_VEGA10:
82 	case CHIP_VEGA12:
83 	case CHIP_VEGA20:
84 	case CHIP_RAVEN:
85 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
86 		break;
87 	default:
88 		dev_info(adev->dev, "kfd not supported on this ASIC\n");
89 		return;
90 	}
91 
92 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
93 				      adev->pdev, kfd2kgd);
94 
95 	if (adev->kfd.dev)
96 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
97 }
98 
99 /**
100  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
101  *                                setup amdkfd
102  *
103  * @adev: amdgpu_device pointer
104  * @aperture_base: output returning doorbell aperture base physical address
105  * @aperture_size: output returning doorbell aperture size in bytes
106  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
107  *
108  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
109  * takes doorbells required for its own rings and reports the setup to amdkfd.
110  * amdgpu reserved doorbells are at the start of the doorbell aperture.
111  */
112 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
113 					 phys_addr_t *aperture_base,
114 					 size_t *aperture_size,
115 					 size_t *start_offset)
116 {
117 	/*
118 	 * The first num_doorbells are used by amdgpu.
119 	 * amdkfd takes whatever's left in the aperture.
120 	 */
121 	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
122 		*aperture_base = adev->doorbell.base;
123 		*aperture_size = adev->doorbell.size;
124 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
125 	} else {
126 		*aperture_base = 0;
127 		*aperture_size = 0;
128 		*start_offset = 0;
129 	}
130 }
131 
132 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
133 {
134 	int i, n;
135 	int last_valid_bit;
136 
137 	if (adev->kfd.dev) {
138 		struct kgd2kfd_shared_resources gpu_resources = {
139 			.compute_vmid_bitmap = compute_vmid_bitmap,
140 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
141 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
142 			.gpuvm_size = min(adev->vm_manager.max_pfn
143 					  << AMDGPU_GPU_PAGE_SHIFT,
144 					  AMDGPU_GMC_HOLE_START),
145 			.drm_render_minor = adev->ddev->render->index
146 		};
147 
148 		/* this is going to have a few of the MSBs set that we need to
149 		 * clear */
150 		bitmap_complement(gpu_resources.queue_bitmap,
151 				  adev->gfx.mec.queue_bitmap,
152 				  KGD_MAX_QUEUES);
153 
154 		/* remove the KIQ bit as well */
155 		if (adev->gfx.kiq.ring.sched.ready)
156 			clear_bit(amdgpu_gfx_queue_to_bit(adev,
157 							  adev->gfx.kiq.ring.me - 1,
158 							  adev->gfx.kiq.ring.pipe,
159 							  adev->gfx.kiq.ring.queue),
160 				  gpu_resources.queue_bitmap);
161 
162 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
163 		 * nbits is not compile time constant */
164 		last_valid_bit = 1 /* only first MEC can have compute queues */
165 				* adev->gfx.mec.num_pipe_per_mec
166 				* adev->gfx.mec.num_queue_per_pipe;
167 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
168 			clear_bit(i, gpu_resources.queue_bitmap);
169 
170 		amdgpu_doorbell_get_kfd_info(adev,
171 				&gpu_resources.doorbell_physical_address,
172 				&gpu_resources.doorbell_aperture_size,
173 				&gpu_resources.doorbell_start_offset);
174 
175 		if (adev->asic_type < CHIP_VEGA10) {
176 			kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
177 			return;
178 		}
179 
180 		n = (adev->asic_type < CHIP_VEGA20) ? 2 : 8;
181 
182 		for (i = 0; i < n; i += 2) {
183 			/* On SOC15 the BIF is involved in routing
184 			 * doorbells using the low 12 bits of the
185 			 * address. Communicate the assignments to
186 			 * KFD. KFD uses two doorbell pages per
187 			 * process in case of 64-bit doorbells so we
188 			 * can use each doorbell assignment twice.
189 			 */
190 			gpu_resources.sdma_doorbell[0][i] =
191 				adev->doorbell_index.sdma_engine[0] + (i >> 1);
192 			gpu_resources.sdma_doorbell[0][i+1] =
193 				adev->doorbell_index.sdma_engine[0] + 0x200 + (i >> 1);
194 			gpu_resources.sdma_doorbell[1][i] =
195 				adev->doorbell_index.sdma_engine[1] + (i >> 1);
196 			gpu_resources.sdma_doorbell[1][i+1] =
197 				adev->doorbell_index.sdma_engine[1] + 0x200 + (i >> 1);
198 		}
199 		/* Doorbells 0x0e0-0ff and 0x2e0-2ff are reserved for
200 		 * SDMA, IH and VCN. So don't use them for the CP.
201 		 */
202 		gpu_resources.reserved_doorbell_mask = 0x1e0;
203 		gpu_resources.reserved_doorbell_val  = 0x0e0;
204 
205 		kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
206 	}
207 }
208 
209 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
210 {
211 	if (adev->kfd.dev) {
212 		kgd2kfd_device_exit(adev->kfd.dev);
213 		adev->kfd.dev = NULL;
214 	}
215 }
216 
217 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
218 		const void *ih_ring_entry)
219 {
220 	if (adev->kfd.dev)
221 		kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
222 }
223 
224 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
225 {
226 	if (adev->kfd.dev)
227 		kgd2kfd_suspend(adev->kfd.dev);
228 }
229 
230 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
231 {
232 	int r = 0;
233 
234 	if (adev->kfd.dev)
235 		r = kgd2kfd_resume(adev->kfd.dev);
236 
237 	return r;
238 }
239 
240 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
241 {
242 	int r = 0;
243 
244 	if (adev->kfd.dev)
245 		r = kgd2kfd_pre_reset(adev->kfd.dev);
246 
247 	return r;
248 }
249 
250 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
251 {
252 	int r = 0;
253 
254 	if (adev->kfd.dev)
255 		r = kgd2kfd_post_reset(adev->kfd.dev);
256 
257 	return r;
258 }
259 
260 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
261 {
262 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
263 
264 	if (amdgpu_device_should_recover_gpu(adev))
265 		amdgpu_device_gpu_recover(adev, NULL);
266 }
267 
268 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
269 				void **mem_obj, uint64_t *gpu_addr,
270 				void **cpu_ptr, bool mqd_gfx9)
271 {
272 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
273 	struct amdgpu_bo *bo = NULL;
274 	struct amdgpu_bo_param bp;
275 	int r;
276 	void *cpu_ptr_tmp = NULL;
277 
278 	memset(&bp, 0, sizeof(bp));
279 	bp.size = size;
280 	bp.byte_align = PAGE_SIZE;
281 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
282 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
283 	bp.type = ttm_bo_type_kernel;
284 	bp.resv = NULL;
285 
286 	if (mqd_gfx9)
287 		bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
288 
289 	r = amdgpu_bo_create(adev, &bp, &bo);
290 	if (r) {
291 		dev_err(adev->dev,
292 			"failed to allocate BO for amdkfd (%d)\n", r);
293 		return r;
294 	}
295 
296 	/* map the buffer */
297 	r = amdgpu_bo_reserve(bo, true);
298 	if (r) {
299 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
300 		goto allocate_mem_reserve_bo_failed;
301 	}
302 
303 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
304 	if (r) {
305 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
306 		goto allocate_mem_pin_bo_failed;
307 	}
308 
309 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
310 	if (r) {
311 		dev_err(adev->dev, "%p bind failed\n", bo);
312 		goto allocate_mem_kmap_bo_failed;
313 	}
314 
315 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
316 	if (r) {
317 		dev_err(adev->dev,
318 			"(%d) failed to map bo to kernel for amdkfd\n", r);
319 		goto allocate_mem_kmap_bo_failed;
320 	}
321 
322 	*mem_obj = bo;
323 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
324 	*cpu_ptr = cpu_ptr_tmp;
325 
326 	amdgpu_bo_unreserve(bo);
327 
328 	return 0;
329 
330 allocate_mem_kmap_bo_failed:
331 	amdgpu_bo_unpin(bo);
332 allocate_mem_pin_bo_failed:
333 	amdgpu_bo_unreserve(bo);
334 allocate_mem_reserve_bo_failed:
335 	amdgpu_bo_unref(&bo);
336 
337 	return r;
338 }
339 
340 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
341 {
342 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
343 
344 	amdgpu_bo_reserve(bo, true);
345 	amdgpu_bo_kunmap(bo);
346 	amdgpu_bo_unpin(bo);
347 	amdgpu_bo_unreserve(bo);
348 	amdgpu_bo_unref(&(bo));
349 }
350 
351 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
352 				      struct kfd_local_mem_info *mem_info)
353 {
354 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
355 	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
356 					     ~((1ULL << 32) - 1);
357 	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
358 
359 	memset(mem_info, 0, sizeof(*mem_info));
360 	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
361 		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
362 		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
363 				adev->gmc.visible_vram_size;
364 	} else {
365 		mem_info->local_mem_size_public = 0;
366 		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
367 	}
368 	mem_info->vram_width = adev->gmc.vram_width;
369 
370 	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
371 			&adev->gmc.aper_base, &aper_limit,
372 			mem_info->local_mem_size_public,
373 			mem_info->local_mem_size_private);
374 
375 	if (amdgpu_sriov_vf(adev))
376 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
377 	else if (adev->powerplay.pp_funcs)
378 		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
379 	else
380 		mem_info->mem_clk_max = 100;
381 }
382 
383 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
384 {
385 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
386 
387 	if (adev->gfx.funcs->get_gpu_clock_counter)
388 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
389 	return 0;
390 }
391 
392 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
393 {
394 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
395 
396 	/* the sclk is in quantas of 10kHz */
397 	if (amdgpu_sriov_vf(adev))
398 		return adev->clock.default_sclk / 100;
399 	else if (adev->powerplay.pp_funcs)
400 		return amdgpu_dpm_get_sclk(adev, false) / 100;
401 	else
402 		return 100;
403 }
404 
405 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
406 {
407 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
408 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
409 
410 	memset(cu_info, 0, sizeof(*cu_info));
411 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
412 		return;
413 
414 	cu_info->cu_active_number = acu_info.number;
415 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
416 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
417 	       sizeof(acu_info.bitmap));
418 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
419 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
420 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
421 	cu_info->simd_per_cu = acu_info.simd_per_cu;
422 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
423 	cu_info->wave_front_size = acu_info.wave_front_size;
424 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
425 	cu_info->lds_size = acu_info.lds_size;
426 }
427 
428 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
429 				  struct kgd_dev **dma_buf_kgd,
430 				  uint64_t *bo_size, void *metadata_buffer,
431 				  size_t buffer_size, uint32_t *metadata_size,
432 				  uint32_t *flags)
433 {
434 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
435 	struct dma_buf *dma_buf;
436 	struct drm_gem_object *obj;
437 	struct amdgpu_bo *bo;
438 	uint64_t metadata_flags;
439 	int r = -EINVAL;
440 
441 	dma_buf = dma_buf_get(dma_buf_fd);
442 	if (IS_ERR(dma_buf))
443 		return PTR_ERR(dma_buf);
444 
445 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
446 		/* Can't handle non-graphics buffers */
447 		goto out_put;
448 
449 	obj = dma_buf->priv;
450 	if (obj->dev->driver != adev->ddev->driver)
451 		/* Can't handle buffers from different drivers */
452 		goto out_put;
453 
454 	adev = obj->dev->dev_private;
455 	bo = gem_to_amdgpu_bo(obj);
456 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
457 				    AMDGPU_GEM_DOMAIN_GTT)))
458 		/* Only VRAM and GTT BOs are supported */
459 		goto out_put;
460 
461 	r = 0;
462 	if (dma_buf_kgd)
463 		*dma_buf_kgd = (struct kgd_dev *)adev;
464 	if (bo_size)
465 		*bo_size = amdgpu_bo_size(bo);
466 	if (metadata_size)
467 		*metadata_size = bo->metadata_size;
468 	if (metadata_buffer)
469 		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
470 					   metadata_size, &metadata_flags);
471 	if (flags) {
472 		*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
473 			ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT;
474 
475 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
476 			*flags |= ALLOC_MEM_FLAGS_PUBLIC;
477 	}
478 
479 out_put:
480 	dma_buf_put(dma_buf);
481 	return r;
482 }
483 
484 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
485 {
486 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
487 
488 	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
489 }
490 
491 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
492 {
493 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
494 
495 	return adev->gmc.xgmi.hive_id;
496 }
497 
498 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
499 				uint32_t vmid, uint64_t gpu_addr,
500 				uint32_t *ib_cmd, uint32_t ib_len)
501 {
502 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
503 	struct amdgpu_job *job;
504 	struct amdgpu_ib *ib;
505 	struct amdgpu_ring *ring;
506 	struct dma_fence *f = NULL;
507 	int ret;
508 
509 	switch (engine) {
510 	case KGD_ENGINE_MEC1:
511 		ring = &adev->gfx.compute_ring[0];
512 		break;
513 	case KGD_ENGINE_SDMA1:
514 		ring = &adev->sdma.instance[0].ring;
515 		break;
516 	case KGD_ENGINE_SDMA2:
517 		ring = &adev->sdma.instance[1].ring;
518 		break;
519 	default:
520 		pr_err("Invalid engine in IB submission: %d\n", engine);
521 		ret = -EINVAL;
522 		goto err;
523 	}
524 
525 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
526 	if (ret)
527 		goto err;
528 
529 	ib = &job->ibs[0];
530 	memset(ib, 0, sizeof(struct amdgpu_ib));
531 
532 	ib->gpu_addr = gpu_addr;
533 	ib->ptr = ib_cmd;
534 	ib->length_dw = ib_len;
535 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
536 	job->vmid = vmid;
537 
538 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
539 	if (ret) {
540 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
541 		goto err_ib_sched;
542 	}
543 
544 	ret = dma_fence_wait(f, false);
545 
546 err_ib_sched:
547 	dma_fence_put(f);
548 	amdgpu_job_free(job);
549 err:
550 	return ret;
551 }
552 
553 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
554 {
555 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
556 
557 	if (adev->powerplay.pp_funcs &&
558 	    adev->powerplay.pp_funcs->switch_power_profile)
559 		amdgpu_dpm_switch_power_profile(adev,
560 						PP_SMC_POWER_PROFILE_COMPUTE,
561 						!idle);
562 }
563 
564 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
565 {
566 	if (adev->kfd.dev) {
567 		if ((1 << vmid) & compute_vmid_bitmap)
568 			return true;
569 	}
570 
571 	return false;
572 }
573 
574 #ifndef CONFIG_HSA_AMD
575 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
576 {
577 	return false;
578 }
579 
580 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
581 {
582 }
583 
584 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
585 					struct amdgpu_vm *vm)
586 {
587 }
588 
589 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
590 {
591 	return NULL;
592 }
593 
594 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
595 {
596 	return 0;
597 }
598 
599 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
600 {
601 	return NULL;
602 }
603 
604 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
605 {
606 	return NULL;
607 }
608 
609 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
610 {
611 	return NULL;
612 }
613 
614 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
615 			      const struct kfd2kgd_calls *f2g)
616 {
617 	return NULL;
618 }
619 
620 bool kgd2kfd_device_init(struct kfd_dev *kfd,
621 			 const struct kgd2kfd_shared_resources *gpu_resources)
622 {
623 	return false;
624 }
625 
626 void kgd2kfd_device_exit(struct kfd_dev *kfd)
627 {
628 }
629 
630 void kgd2kfd_exit(void)
631 {
632 }
633 
634 void kgd2kfd_suspend(struct kfd_dev *kfd)
635 {
636 }
637 
638 int kgd2kfd_resume(struct kfd_dev *kfd)
639 {
640 	return 0;
641 }
642 
643 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
644 {
645 	return 0;
646 }
647 
648 int kgd2kfd_post_reset(struct kfd_dev *kfd)
649 {
650 	return 0;
651 }
652 
653 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
654 {
655 }
656 #endif
657