1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_shared.h" 25 26 #include "amdgpu.h" 27 #include "amdgpu_gfx.h" 28 #include "amdgpu_dma_buf.h" 29 #include <linux/module.h> 30 #include <linux/dma-buf.h> 31 #include "amdgpu_xgmi.h" 32 #include <uapi/linux/kfd_ioctl.h> 33 34 /* Total memory size in system memory and all GPU VRAM. Used to 35 * estimate worst case amount of memory to reserve for page tables 36 */ 37 uint64_t amdgpu_amdkfd_total_mem_size; 38 39 static bool kfd_initialized; 40 41 int amdgpu_amdkfd_init(void) 42 { 43 struct sysinfo si; 44 int ret; 45 46 si_meminfo(&si); 47 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 48 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 49 50 ret = kgd2kfd_init(); 51 amdgpu_amdkfd_gpuvm_init_mem_limits(); 52 kfd_initialized = !ret; 53 54 return ret; 55 } 56 57 void amdgpu_amdkfd_fini(void) 58 { 59 if (kfd_initialized) { 60 kgd2kfd_exit(); 61 kfd_initialized = false; 62 } 63 } 64 65 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 66 { 67 bool vf = amdgpu_sriov_vf(adev); 68 69 if (!kfd_initialized) 70 return; 71 72 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev, 73 adev->pdev, adev->asic_type, vf); 74 75 if (adev->kfd.dev) 76 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 77 } 78 79 /** 80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 81 * setup amdkfd 82 * 83 * @adev: amdgpu_device pointer 84 * @aperture_base: output returning doorbell aperture base physical address 85 * @aperture_size: output returning doorbell aperture size in bytes 86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 87 * 88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 89 * takes doorbells required for its own rings and reports the setup to amdkfd. 90 * amdgpu reserved doorbells are at the start of the doorbell aperture. 91 */ 92 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 93 phys_addr_t *aperture_base, 94 size_t *aperture_size, 95 size_t *start_offset) 96 { 97 /* 98 * The first num_doorbells are used by amdgpu. 99 * amdkfd takes whatever's left in the aperture. 100 */ 101 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) { 102 *aperture_base = adev->doorbell.base; 103 *aperture_size = adev->doorbell.size; 104 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 105 } else { 106 *aperture_base = 0; 107 *aperture_size = 0; 108 *start_offset = 0; 109 } 110 } 111 112 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 113 { 114 int i; 115 int last_valid_bit; 116 117 if (adev->kfd.dev) { 118 struct kgd2kfd_shared_resources gpu_resources = { 119 .compute_vmid_bitmap = 120 ((1 << AMDGPU_NUM_VMID) - 1) - 121 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 122 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 123 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 124 .gpuvm_size = min(adev->vm_manager.max_pfn 125 << AMDGPU_GPU_PAGE_SHIFT, 126 AMDGPU_GMC_HOLE_START), 127 .drm_render_minor = adev_to_drm(adev)->render->index, 128 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 129 130 }; 131 132 /* this is going to have a few of the MSBs set that we need to 133 * clear 134 */ 135 bitmap_complement(gpu_resources.cp_queue_bitmap, 136 adev->gfx.mec.queue_bitmap, 137 KGD_MAX_QUEUES); 138 139 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 140 * nbits is not compile time constant 141 */ 142 last_valid_bit = 1 /* only first MEC can have compute queues */ 143 * adev->gfx.mec.num_pipe_per_mec 144 * adev->gfx.mec.num_queue_per_pipe; 145 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 146 clear_bit(i, gpu_resources.cp_queue_bitmap); 147 148 amdgpu_doorbell_get_kfd_info(adev, 149 &gpu_resources.doorbell_physical_address, 150 &gpu_resources.doorbell_aperture_size, 151 &gpu_resources.doorbell_start_offset); 152 153 /* Since SOC15, BIF starts to statically use the 154 * lower 12 bits of doorbell addresses for routing 155 * based on settings in registers like 156 * SDMA0_DOORBELL_RANGE etc.. 157 * In order to route a doorbell to CP engine, the lower 158 * 12 bits of its address has to be outside the range 159 * set for SDMA, VCN, and IH blocks. 160 */ 161 if (adev->asic_type >= CHIP_VEGA10) { 162 gpu_resources.non_cp_doorbells_start = 163 adev->doorbell_index.first_non_cp; 164 gpu_resources.non_cp_doorbells_end = 165 adev->doorbell_index.last_non_cp; 166 } 167 168 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 169 adev_to_drm(adev), &gpu_resources); 170 } 171 } 172 173 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev) 174 { 175 if (adev->kfd.dev) { 176 kgd2kfd_device_exit(adev->kfd.dev); 177 adev->kfd.dev = NULL; 178 } 179 } 180 181 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 182 const void *ih_ring_entry) 183 { 184 if (adev->kfd.dev) 185 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 186 } 187 188 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 189 { 190 if (adev->kfd.dev) 191 kgd2kfd_suspend(adev->kfd.dev, run_pm); 192 } 193 194 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 195 { 196 int r = 0; 197 198 if (adev->kfd.dev) 199 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 200 201 return r; 202 } 203 204 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 205 { 206 int r = 0; 207 208 if (adev->kfd.dev) 209 r = kgd2kfd_pre_reset(adev->kfd.dev); 210 211 return r; 212 } 213 214 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 215 { 216 int r = 0; 217 218 if (adev->kfd.dev) 219 r = kgd2kfd_post_reset(adev->kfd.dev); 220 221 return r; 222 } 223 224 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd) 225 { 226 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 227 228 if (amdgpu_device_should_recover_gpu(adev)) 229 amdgpu_device_gpu_recover(adev, NULL); 230 } 231 232 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 233 void **mem_obj, uint64_t *gpu_addr, 234 void **cpu_ptr, bool cp_mqd_gfx9) 235 { 236 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 237 struct amdgpu_bo *bo = NULL; 238 struct amdgpu_bo_param bp; 239 int r; 240 void *cpu_ptr_tmp = NULL; 241 242 memset(&bp, 0, sizeof(bp)); 243 bp.size = size; 244 bp.byte_align = PAGE_SIZE; 245 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 246 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 247 bp.type = ttm_bo_type_kernel; 248 bp.resv = NULL; 249 250 if (cp_mqd_gfx9) 251 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 252 253 r = amdgpu_bo_create(adev, &bp, &bo); 254 if (r) { 255 dev_err(adev->dev, 256 "failed to allocate BO for amdkfd (%d)\n", r); 257 return r; 258 } 259 260 /* map the buffer */ 261 r = amdgpu_bo_reserve(bo, true); 262 if (r) { 263 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 264 goto allocate_mem_reserve_bo_failed; 265 } 266 267 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 268 if (r) { 269 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 270 goto allocate_mem_pin_bo_failed; 271 } 272 273 r = amdgpu_ttm_alloc_gart(&bo->tbo); 274 if (r) { 275 dev_err(adev->dev, "%p bind failed\n", bo); 276 goto allocate_mem_kmap_bo_failed; 277 } 278 279 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 280 if (r) { 281 dev_err(adev->dev, 282 "(%d) failed to map bo to kernel for amdkfd\n", r); 283 goto allocate_mem_kmap_bo_failed; 284 } 285 286 *mem_obj = bo; 287 *gpu_addr = amdgpu_bo_gpu_offset(bo); 288 *cpu_ptr = cpu_ptr_tmp; 289 290 amdgpu_bo_unreserve(bo); 291 292 return 0; 293 294 allocate_mem_kmap_bo_failed: 295 amdgpu_bo_unpin(bo); 296 allocate_mem_pin_bo_failed: 297 amdgpu_bo_unreserve(bo); 298 allocate_mem_reserve_bo_failed: 299 amdgpu_bo_unref(&bo); 300 301 return r; 302 } 303 304 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj) 305 { 306 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 307 308 amdgpu_bo_reserve(bo, true); 309 amdgpu_bo_kunmap(bo); 310 amdgpu_bo_unpin(bo); 311 amdgpu_bo_unreserve(bo); 312 amdgpu_bo_unref(&(bo)); 313 } 314 315 int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 316 void **mem_obj) 317 { 318 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 319 struct amdgpu_bo *bo = NULL; 320 struct amdgpu_bo_param bp; 321 int r; 322 323 memset(&bp, 0, sizeof(bp)); 324 bp.size = size; 325 bp.byte_align = 1; 326 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 327 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 328 bp.type = ttm_bo_type_device; 329 bp.resv = NULL; 330 331 r = amdgpu_bo_create(adev, &bp, &bo); 332 if (r) { 333 dev_err(adev->dev, 334 "failed to allocate gws BO for amdkfd (%d)\n", r); 335 return r; 336 } 337 338 *mem_obj = bo; 339 return 0; 340 } 341 342 void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj) 343 { 344 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 345 346 amdgpu_bo_unref(&bo); 347 } 348 349 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd, 350 enum kgd_engine_type type) 351 { 352 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 353 354 switch (type) { 355 case KGD_ENGINE_PFP: 356 return adev->gfx.pfp_fw_version; 357 358 case KGD_ENGINE_ME: 359 return adev->gfx.me_fw_version; 360 361 case KGD_ENGINE_CE: 362 return adev->gfx.ce_fw_version; 363 364 case KGD_ENGINE_MEC1: 365 return adev->gfx.mec_fw_version; 366 367 case KGD_ENGINE_MEC2: 368 return adev->gfx.mec2_fw_version; 369 370 case KGD_ENGINE_RLC: 371 return adev->gfx.rlc_fw_version; 372 373 case KGD_ENGINE_SDMA1: 374 return adev->sdma.instance[0].fw_version; 375 376 case KGD_ENGINE_SDMA2: 377 return adev->sdma.instance[1].fw_version; 378 379 default: 380 return 0; 381 } 382 383 return 0; 384 } 385 386 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd, 387 struct kfd_local_mem_info *mem_info) 388 { 389 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 390 391 memset(mem_info, 0, sizeof(*mem_info)); 392 393 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 394 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 395 adev->gmc.visible_vram_size; 396 397 mem_info->vram_width = adev->gmc.vram_width; 398 399 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 400 &adev->gmc.aper_base, 401 mem_info->local_mem_size_public, 402 mem_info->local_mem_size_private); 403 404 if (amdgpu_sriov_vf(adev)) 405 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 406 else if (adev->pm.dpm_enabled) { 407 if (amdgpu_emu_mode == 1) 408 mem_info->mem_clk_max = 0; 409 else 410 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 411 } else 412 mem_info->mem_clk_max = 100; 413 } 414 415 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd) 416 { 417 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 418 419 if (adev->gfx.funcs->get_gpu_clock_counter) 420 return adev->gfx.funcs->get_gpu_clock_counter(adev); 421 return 0; 422 } 423 424 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd) 425 { 426 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 427 428 /* the sclk is in quantas of 10kHz */ 429 if (amdgpu_sriov_vf(adev)) 430 return adev->clock.default_sclk / 100; 431 else if (adev->pm.dpm_enabled) 432 return amdgpu_dpm_get_sclk(adev, false) / 100; 433 else 434 return 100; 435 } 436 437 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info) 438 { 439 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 440 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 441 442 memset(cu_info, 0, sizeof(*cu_info)); 443 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 444 return; 445 446 cu_info->cu_active_number = acu_info.number; 447 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 448 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 449 sizeof(acu_info.bitmap)); 450 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 451 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 452 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 453 cu_info->simd_per_cu = acu_info.simd_per_cu; 454 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 455 cu_info->wave_front_size = acu_info.wave_front_size; 456 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 457 cu_info->lds_size = acu_info.lds_size; 458 } 459 460 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 461 struct kgd_dev **dma_buf_kgd, 462 uint64_t *bo_size, void *metadata_buffer, 463 size_t buffer_size, uint32_t *metadata_size, 464 uint32_t *flags) 465 { 466 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 467 struct dma_buf *dma_buf; 468 struct drm_gem_object *obj; 469 struct amdgpu_bo *bo; 470 uint64_t metadata_flags; 471 int r = -EINVAL; 472 473 dma_buf = dma_buf_get(dma_buf_fd); 474 if (IS_ERR(dma_buf)) 475 return PTR_ERR(dma_buf); 476 477 if (dma_buf->ops != &amdgpu_dmabuf_ops) 478 /* Can't handle non-graphics buffers */ 479 goto out_put; 480 481 obj = dma_buf->priv; 482 if (obj->dev->driver != adev_to_drm(adev)->driver) 483 /* Can't handle buffers from different drivers */ 484 goto out_put; 485 486 adev = drm_to_adev(obj->dev); 487 bo = gem_to_amdgpu_bo(obj); 488 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 489 AMDGPU_GEM_DOMAIN_GTT))) 490 /* Only VRAM and GTT BOs are supported */ 491 goto out_put; 492 493 r = 0; 494 if (dma_buf_kgd) 495 *dma_buf_kgd = (struct kgd_dev *)adev; 496 if (bo_size) 497 *bo_size = amdgpu_bo_size(bo); 498 if (metadata_size) 499 *metadata_size = bo->metadata_size; 500 if (metadata_buffer) 501 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 502 metadata_size, &metadata_flags); 503 if (flags) { 504 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 505 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 506 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 507 508 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 509 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 510 } 511 512 out_put: 513 dma_buf_put(dma_buf); 514 return r; 515 } 516 517 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd) 518 { 519 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 520 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM); 521 522 return amdgpu_vram_mgr_usage(vram_man); 523 } 524 525 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd) 526 { 527 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 528 529 return adev->gmc.xgmi.hive_id; 530 } 531 532 uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd) 533 { 534 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 535 536 return adev->unique_id; 537 } 538 539 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src) 540 { 541 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src; 542 struct amdgpu_device *adev = (struct amdgpu_device *)dst; 543 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 544 545 if (ret < 0) { 546 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 547 adev->gmc.xgmi.physical_node_id, 548 peer_adev->gmc.xgmi.physical_node_id, ret); 549 ret = 0; 550 } 551 return (uint8_t)ret; 552 } 553 554 uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd) 555 { 556 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 557 558 return adev->rmmio_remap.bus_addr; 559 } 560 561 uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd) 562 { 563 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 564 565 return adev->gds.gws_size; 566 } 567 568 uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd) 569 { 570 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 571 572 return adev->rev_id; 573 } 574 575 int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd) 576 { 577 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 578 579 return adev->gmc.noretry; 580 } 581 582 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine, 583 uint32_t vmid, uint64_t gpu_addr, 584 uint32_t *ib_cmd, uint32_t ib_len) 585 { 586 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 587 struct amdgpu_job *job; 588 struct amdgpu_ib *ib; 589 struct amdgpu_ring *ring; 590 struct dma_fence *f = NULL; 591 int ret; 592 593 switch (engine) { 594 case KGD_ENGINE_MEC1: 595 ring = &adev->gfx.compute_ring[0]; 596 break; 597 case KGD_ENGINE_SDMA1: 598 ring = &adev->sdma.instance[0].ring; 599 break; 600 case KGD_ENGINE_SDMA2: 601 ring = &adev->sdma.instance[1].ring; 602 break; 603 default: 604 pr_err("Invalid engine in IB submission: %d\n", engine); 605 ret = -EINVAL; 606 goto err; 607 } 608 609 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 610 if (ret) 611 goto err; 612 613 ib = &job->ibs[0]; 614 memset(ib, 0, sizeof(struct amdgpu_ib)); 615 616 ib->gpu_addr = gpu_addr; 617 ib->ptr = ib_cmd; 618 ib->length_dw = ib_len; 619 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 620 job->vmid = vmid; 621 622 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 623 624 if (ret) { 625 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 626 goto err_ib_sched; 627 } 628 629 ret = dma_fence_wait(f, false); 630 631 err_ib_sched: 632 dma_fence_put(f); 633 amdgpu_job_free(job); 634 err: 635 return ret; 636 } 637 638 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 639 { 640 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 641 642 amdgpu_dpm_switch_power_profile(adev, 643 PP_SMC_POWER_PROFILE_COMPUTE, 644 !idle); 645 } 646 647 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 648 { 649 if (adev->kfd.dev) 650 return vmid >= adev->vm_manager.first_kfd_vmid; 651 652 return false; 653 } 654 655 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid) 656 { 657 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 658 659 if (adev->family == AMDGPU_FAMILY_AI) { 660 int i; 661 662 for (i = 0; i < adev->num_vmhubs; i++) 663 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 664 } else { 665 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 666 } 667 668 return 0; 669 } 670 671 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid) 672 { 673 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 674 const uint32_t flush_type = 0; 675 bool all_hub = false; 676 677 if (adev->family == AMDGPU_FAMILY_AI) 678 all_hub = true; 679 680 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 681 } 682 683 bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd) 684 { 685 struct amdgpu_device *adev = (struct amdgpu_device *)kgd; 686 687 return adev->have_atomics_support; 688 } 689