1 /* 2 * Copyright 2014 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "amdgpu_amdkfd.h" 24 #include "amd_pcie.h" 25 #include "amd_shared.h" 26 27 #include "amdgpu.h" 28 #include "amdgpu_gfx.h" 29 #include "amdgpu_dma_buf.h" 30 #include <linux/module.h> 31 #include <linux/dma-buf.h> 32 #include "amdgpu_xgmi.h" 33 #include <uapi/linux/kfd_ioctl.h> 34 #include "amdgpu_ras.h" 35 #include "amdgpu_umc.h" 36 #include "amdgpu_reset.h" 37 38 /* Total memory size in system memory and all GPU VRAM. Used to 39 * estimate worst case amount of memory to reserve for page tables 40 */ 41 uint64_t amdgpu_amdkfd_total_mem_size; 42 43 static bool kfd_initialized; 44 45 int amdgpu_amdkfd_init(void) 46 { 47 struct sysinfo si; 48 int ret; 49 50 si_meminfo(&si); 51 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 52 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 53 54 ret = kgd2kfd_init(); 55 amdgpu_amdkfd_gpuvm_init_mem_limits(); 56 kfd_initialized = !ret; 57 58 return ret; 59 } 60 61 void amdgpu_amdkfd_fini(void) 62 { 63 if (kfd_initialized) { 64 kgd2kfd_exit(); 65 kfd_initialized = false; 66 } 67 } 68 69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 70 { 71 bool vf = amdgpu_sriov_vf(adev); 72 73 if (!kfd_initialized) 74 return; 75 76 adev->kfd.dev = kgd2kfd_probe(adev, vf); 77 78 if (adev->kfd.dev) 79 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 80 } 81 82 /** 83 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 84 * setup amdkfd 85 * 86 * @adev: amdgpu_device pointer 87 * @aperture_base: output returning doorbell aperture base physical address 88 * @aperture_size: output returning doorbell aperture size in bytes 89 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 90 * 91 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 92 * takes doorbells required for its own rings and reports the setup to amdkfd. 93 * amdgpu reserved doorbells are at the start of the doorbell aperture. 94 */ 95 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 96 phys_addr_t *aperture_base, 97 size_t *aperture_size, 98 size_t *start_offset) 99 { 100 /* 101 * The first num_doorbells are used by amdgpu. 102 * amdkfd takes whatever's left in the aperture. 103 */ 104 if (adev->enable_mes) { 105 /* 106 * With MES enabled, we only need to initialize 107 * the base address. The size and offset are 108 * not initialized as AMDGPU manages the whole 109 * doorbell space. 110 */ 111 *aperture_base = adev->doorbell.base; 112 *aperture_size = 0; 113 *start_offset = 0; 114 } else if (adev->doorbell.size > adev->doorbell.num_doorbells * 115 sizeof(u32)) { 116 *aperture_base = adev->doorbell.base; 117 *aperture_size = adev->doorbell.size; 118 *start_offset = adev->doorbell.num_doorbells * sizeof(u32); 119 } else { 120 *aperture_base = 0; 121 *aperture_size = 0; 122 *start_offset = 0; 123 } 124 } 125 126 127 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 128 { 129 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 130 kfd.reset_work); 131 132 struct amdgpu_reset_context reset_context; 133 memset(&reset_context, 0, sizeof(reset_context)); 134 135 reset_context.method = AMD_RESET_METHOD_NONE; 136 reset_context.reset_req_dev = adev; 137 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 138 139 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 140 } 141 142 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 143 { 144 int i; 145 int last_valid_bit; 146 147 if (adev->kfd.dev) { 148 struct kgd2kfd_shared_resources gpu_resources = { 149 .compute_vmid_bitmap = 150 ((1 << AMDGPU_NUM_VMID) - 1) - 151 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 152 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 153 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 154 .gpuvm_size = min(adev->vm_manager.max_pfn 155 << AMDGPU_GPU_PAGE_SHIFT, 156 AMDGPU_GMC_HOLE_START), 157 .drm_render_minor = adev_to_drm(adev)->render->index, 158 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 159 .enable_mes = adev->enable_mes, 160 }; 161 162 /* this is going to have a few of the MSBs set that we need to 163 * clear 164 */ 165 bitmap_complement(gpu_resources.cp_queue_bitmap, 166 adev->gfx.mec.queue_bitmap, 167 KGD_MAX_QUEUES); 168 169 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 170 * nbits is not compile time constant 171 */ 172 last_valid_bit = 1 /* only first MEC can have compute queues */ 173 * adev->gfx.mec.num_pipe_per_mec 174 * adev->gfx.mec.num_queue_per_pipe; 175 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 176 clear_bit(i, gpu_resources.cp_queue_bitmap); 177 178 amdgpu_doorbell_get_kfd_info(adev, 179 &gpu_resources.doorbell_physical_address, 180 &gpu_resources.doorbell_aperture_size, 181 &gpu_resources.doorbell_start_offset); 182 183 /* Since SOC15, BIF starts to statically use the 184 * lower 12 bits of doorbell addresses for routing 185 * based on settings in registers like 186 * SDMA0_DOORBELL_RANGE etc.. 187 * In order to route a doorbell to CP engine, the lower 188 * 12 bits of its address has to be outside the range 189 * set for SDMA, VCN, and IH blocks. 190 */ 191 if (adev->asic_type >= CHIP_VEGA10) { 192 gpu_resources.non_cp_doorbells_start = 193 adev->doorbell_index.first_non_cp; 194 gpu_resources.non_cp_doorbells_end = 195 adev->doorbell_index.last_non_cp; 196 } 197 198 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 199 adev_to_drm(adev), &gpu_resources); 200 201 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 202 } 203 } 204 205 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 206 { 207 if (adev->kfd.dev) { 208 kgd2kfd_device_exit(adev->kfd.dev); 209 adev->kfd.dev = NULL; 210 } 211 } 212 213 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 214 const void *ih_ring_entry) 215 { 216 if (adev->kfd.dev) 217 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 218 } 219 220 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 221 { 222 if (adev->kfd.dev) 223 kgd2kfd_suspend(adev->kfd.dev, run_pm); 224 } 225 226 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev) 227 { 228 int r = 0; 229 230 if (adev->kfd.dev) 231 r = kgd2kfd_resume_iommu(adev->kfd.dev); 232 233 return r; 234 } 235 236 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 237 { 238 int r = 0; 239 240 if (adev->kfd.dev) 241 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 242 243 return r; 244 } 245 246 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 247 { 248 int r = 0; 249 250 if (adev->kfd.dev) 251 r = kgd2kfd_pre_reset(adev->kfd.dev); 252 253 return r; 254 } 255 256 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 257 { 258 int r = 0; 259 260 if (adev->kfd.dev) 261 r = kgd2kfd_post_reset(adev->kfd.dev); 262 263 return r; 264 } 265 266 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 267 { 268 if (amdgpu_device_should_recover_gpu(adev)) 269 amdgpu_reset_domain_schedule(adev->reset_domain, 270 &adev->kfd.reset_work); 271 } 272 273 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 274 void **mem_obj, uint64_t *gpu_addr, 275 void **cpu_ptr, bool cp_mqd_gfx9) 276 { 277 struct amdgpu_bo *bo = NULL; 278 struct amdgpu_bo_param bp; 279 int r; 280 void *cpu_ptr_tmp = NULL; 281 282 memset(&bp, 0, sizeof(bp)); 283 bp.size = size; 284 bp.byte_align = PAGE_SIZE; 285 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 286 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 287 bp.type = ttm_bo_type_kernel; 288 bp.resv = NULL; 289 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 290 291 if (cp_mqd_gfx9) 292 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 293 294 r = amdgpu_bo_create(adev, &bp, &bo); 295 if (r) { 296 dev_err(adev->dev, 297 "failed to allocate BO for amdkfd (%d)\n", r); 298 return r; 299 } 300 301 /* map the buffer */ 302 r = amdgpu_bo_reserve(bo, true); 303 if (r) { 304 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 305 goto allocate_mem_reserve_bo_failed; 306 } 307 308 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 309 if (r) { 310 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 311 goto allocate_mem_pin_bo_failed; 312 } 313 314 r = amdgpu_ttm_alloc_gart(&bo->tbo); 315 if (r) { 316 dev_err(adev->dev, "%p bind failed\n", bo); 317 goto allocate_mem_kmap_bo_failed; 318 } 319 320 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 321 if (r) { 322 dev_err(adev->dev, 323 "(%d) failed to map bo to kernel for amdkfd\n", r); 324 goto allocate_mem_kmap_bo_failed; 325 } 326 327 *mem_obj = bo; 328 *gpu_addr = amdgpu_bo_gpu_offset(bo); 329 *cpu_ptr = cpu_ptr_tmp; 330 331 amdgpu_bo_unreserve(bo); 332 333 return 0; 334 335 allocate_mem_kmap_bo_failed: 336 amdgpu_bo_unpin(bo); 337 allocate_mem_pin_bo_failed: 338 amdgpu_bo_unreserve(bo); 339 allocate_mem_reserve_bo_failed: 340 amdgpu_bo_unref(&bo); 341 342 return r; 343 } 344 345 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 346 { 347 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 348 349 amdgpu_bo_reserve(bo, true); 350 amdgpu_bo_kunmap(bo); 351 amdgpu_bo_unpin(bo); 352 amdgpu_bo_unreserve(bo); 353 amdgpu_bo_unref(&(bo)); 354 } 355 356 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 357 void **mem_obj) 358 { 359 struct amdgpu_bo *bo = NULL; 360 struct amdgpu_bo_user *ubo; 361 struct amdgpu_bo_param bp; 362 int r; 363 364 memset(&bp, 0, sizeof(bp)); 365 bp.size = size; 366 bp.byte_align = 1; 367 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 368 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 369 bp.type = ttm_bo_type_device; 370 bp.resv = NULL; 371 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 372 373 r = amdgpu_bo_create_user(adev, &bp, &ubo); 374 if (r) { 375 dev_err(adev->dev, 376 "failed to allocate gws BO for amdkfd (%d)\n", r); 377 return r; 378 } 379 380 bo = &ubo->bo; 381 *mem_obj = bo; 382 return 0; 383 } 384 385 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 386 { 387 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 388 389 amdgpu_bo_unref(&bo); 390 } 391 392 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 393 enum kgd_engine_type type) 394 { 395 switch (type) { 396 case KGD_ENGINE_PFP: 397 return adev->gfx.pfp_fw_version; 398 399 case KGD_ENGINE_ME: 400 return adev->gfx.me_fw_version; 401 402 case KGD_ENGINE_CE: 403 return adev->gfx.ce_fw_version; 404 405 case KGD_ENGINE_MEC1: 406 return adev->gfx.mec_fw_version; 407 408 case KGD_ENGINE_MEC2: 409 return adev->gfx.mec2_fw_version; 410 411 case KGD_ENGINE_RLC: 412 return adev->gfx.rlc_fw_version; 413 414 case KGD_ENGINE_SDMA1: 415 return adev->sdma.instance[0].fw_version; 416 417 case KGD_ENGINE_SDMA2: 418 return adev->sdma.instance[1].fw_version; 419 420 default: 421 return 0; 422 } 423 424 return 0; 425 } 426 427 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 428 struct kfd_local_mem_info *mem_info) 429 { 430 memset(mem_info, 0, sizeof(*mem_info)); 431 432 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 433 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 434 adev->gmc.visible_vram_size; 435 436 mem_info->vram_width = adev->gmc.vram_width; 437 438 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 439 &adev->gmc.aper_base, 440 mem_info->local_mem_size_public, 441 mem_info->local_mem_size_private); 442 443 if (amdgpu_sriov_vf(adev)) 444 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 445 else if (adev->pm.dpm_enabled) { 446 if (amdgpu_emu_mode == 1) 447 mem_info->mem_clk_max = 0; 448 else 449 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 450 } else 451 mem_info->mem_clk_max = 100; 452 } 453 454 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 455 { 456 if (adev->gfx.funcs->get_gpu_clock_counter) 457 return adev->gfx.funcs->get_gpu_clock_counter(adev); 458 return 0; 459 } 460 461 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 462 { 463 /* the sclk is in quantas of 10kHz */ 464 if (amdgpu_sriov_vf(adev)) 465 return adev->clock.default_sclk / 100; 466 else if (adev->pm.dpm_enabled) 467 return amdgpu_dpm_get_sclk(adev, false) / 100; 468 else 469 return 100; 470 } 471 472 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info) 473 { 474 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 475 476 memset(cu_info, 0, sizeof(*cu_info)); 477 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 478 return; 479 480 cu_info->cu_active_number = acu_info.number; 481 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 482 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 483 sizeof(acu_info.bitmap)); 484 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 485 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 486 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 487 cu_info->simd_per_cu = acu_info.simd_per_cu; 488 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 489 cu_info->wave_front_size = acu_info.wave_front_size; 490 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 491 cu_info->lds_size = acu_info.lds_size; 492 } 493 494 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 495 struct amdgpu_device **dmabuf_adev, 496 uint64_t *bo_size, void *metadata_buffer, 497 size_t buffer_size, uint32_t *metadata_size, 498 uint32_t *flags) 499 { 500 struct dma_buf *dma_buf; 501 struct drm_gem_object *obj; 502 struct amdgpu_bo *bo; 503 uint64_t metadata_flags; 504 int r = -EINVAL; 505 506 dma_buf = dma_buf_get(dma_buf_fd); 507 if (IS_ERR(dma_buf)) 508 return PTR_ERR(dma_buf); 509 510 if (dma_buf->ops != &amdgpu_dmabuf_ops) 511 /* Can't handle non-graphics buffers */ 512 goto out_put; 513 514 obj = dma_buf->priv; 515 if (obj->dev->driver != adev_to_drm(adev)->driver) 516 /* Can't handle buffers from different drivers */ 517 goto out_put; 518 519 adev = drm_to_adev(obj->dev); 520 bo = gem_to_amdgpu_bo(obj); 521 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 522 AMDGPU_GEM_DOMAIN_GTT))) 523 /* Only VRAM and GTT BOs are supported */ 524 goto out_put; 525 526 r = 0; 527 if (dmabuf_adev) 528 *dmabuf_adev = adev; 529 if (bo_size) 530 *bo_size = amdgpu_bo_size(bo); 531 if (metadata_buffer) 532 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 533 metadata_size, &metadata_flags); 534 if (flags) { 535 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 536 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 537 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 538 539 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 540 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 541 } 542 543 out_put: 544 dma_buf_put(dma_buf); 545 return r; 546 } 547 548 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 549 struct amdgpu_device *src) 550 { 551 struct amdgpu_device *peer_adev = src; 552 struct amdgpu_device *adev = dst; 553 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 554 555 if (ret < 0) { 556 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 557 adev->gmc.xgmi.physical_node_id, 558 peer_adev->gmc.xgmi.physical_node_id, ret); 559 ret = 0; 560 } 561 return (uint8_t)ret; 562 } 563 564 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 565 struct amdgpu_device *src, 566 bool is_min) 567 { 568 struct amdgpu_device *adev = dst, *peer_adev; 569 int num_links; 570 571 if (adev->asic_type != CHIP_ALDEBARAN) 572 return 0; 573 574 if (src) 575 peer_adev = src; 576 577 /* num links returns 0 for indirect peers since indirect route is unknown. */ 578 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 579 if (num_links < 0) { 580 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 581 adev->gmc.xgmi.physical_node_id, 582 peer_adev->gmc.xgmi.physical_node_id, num_links); 583 num_links = 0; 584 } 585 586 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 587 return (num_links * 16 * 25000)/BITS_PER_BYTE; 588 } 589 590 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 591 { 592 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 593 fls(adev->pm.pcie_mlw_mask)) - 1; 594 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 595 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 596 fls(adev->pm.pcie_gen_mask & 597 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 598 uint32_t num_lanes_mask = 1 << num_lanes_shift; 599 uint32_t gen_speed_mask = 1 << gen_speed_shift; 600 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 601 602 switch (num_lanes_mask) { 603 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 604 num_lanes_factor = 1; 605 break; 606 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 607 num_lanes_factor = 2; 608 break; 609 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 610 num_lanes_factor = 4; 611 break; 612 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 613 num_lanes_factor = 8; 614 break; 615 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 616 num_lanes_factor = 12; 617 break; 618 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 619 num_lanes_factor = 16; 620 break; 621 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 622 num_lanes_factor = 32; 623 break; 624 } 625 626 switch (gen_speed_mask) { 627 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 628 gen_speed_mbits_factor = 2500; 629 break; 630 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 631 gen_speed_mbits_factor = 5000; 632 break; 633 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 634 gen_speed_mbits_factor = 8000; 635 break; 636 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 637 gen_speed_mbits_factor = 16000; 638 break; 639 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 640 gen_speed_mbits_factor = 32000; 641 break; 642 } 643 644 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 645 } 646 647 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 648 enum kgd_engine_type engine, 649 uint32_t vmid, uint64_t gpu_addr, 650 uint32_t *ib_cmd, uint32_t ib_len) 651 { 652 struct amdgpu_job *job; 653 struct amdgpu_ib *ib; 654 struct amdgpu_ring *ring; 655 struct dma_fence *f = NULL; 656 int ret; 657 658 switch (engine) { 659 case KGD_ENGINE_MEC1: 660 ring = &adev->gfx.compute_ring[0]; 661 break; 662 case KGD_ENGINE_SDMA1: 663 ring = &adev->sdma.instance[0].ring; 664 break; 665 case KGD_ENGINE_SDMA2: 666 ring = &adev->sdma.instance[1].ring; 667 break; 668 default: 669 pr_err("Invalid engine in IB submission: %d\n", engine); 670 ret = -EINVAL; 671 goto err; 672 } 673 674 ret = amdgpu_job_alloc(adev, 1, &job, NULL); 675 if (ret) 676 goto err; 677 678 ib = &job->ibs[0]; 679 memset(ib, 0, sizeof(struct amdgpu_ib)); 680 681 ib->gpu_addr = gpu_addr; 682 ib->ptr = ib_cmd; 683 ib->length_dw = ib_len; 684 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 685 job->vmid = vmid; 686 687 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 688 689 if (ret) { 690 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 691 goto err_ib_sched; 692 } 693 694 /* Drop the initial kref_init count (see drm_sched_main as example) */ 695 dma_fence_put(f); 696 ret = dma_fence_wait(f, false); 697 698 err_ib_sched: 699 amdgpu_job_free(job); 700 err: 701 return ret; 702 } 703 704 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 705 { 706 amdgpu_dpm_switch_power_profile(adev, 707 PP_SMC_POWER_PROFILE_COMPUTE, 708 !idle); 709 } 710 711 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 712 { 713 if (adev->kfd.dev) 714 return vmid >= adev->vm_manager.first_kfd_vmid; 715 716 return false; 717 } 718 719 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 720 uint16_t vmid) 721 { 722 if (adev->family == AMDGPU_FAMILY_AI) { 723 int i; 724 725 for (i = 0; i < adev->num_vmhubs; i++) 726 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 727 } else { 728 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0); 729 } 730 731 return 0; 732 } 733 734 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 735 uint16_t pasid, enum TLB_FLUSH_TYPE flush_type) 736 { 737 bool all_hub = false; 738 739 if (adev->family == AMDGPU_FAMILY_AI || 740 adev->family == AMDGPU_FAMILY_RV) 741 all_hub = true; 742 743 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub); 744 } 745 746 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 747 { 748 return adev->have_atomics_support; 749 } 750 751 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 752 { 753 struct ras_err_data err_data = {0, 0, 0, NULL}; 754 755 /* CPU MCA will handle page retirement if connected_to_cpu is 1 */ 756 if (!adev->gmc.xgmi.connected_to_cpu) 757 amdgpu_umc_poison_handler(adev, &err_data, reset); 758 else if (reset) 759 amdgpu_amdkfd_gpu_reset(adev); 760 } 761 762 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 763 { 764 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 765 return adev->gfx.ras->query_utcl2_poison_status(adev); 766 else 767 return false; 768 } 769