1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2014 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "amdgpu_amdkfd.h" 25 #include "amd_pcie.h" 26 #include "amd_shared.h" 27 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_dma_buf.h" 31 #include <linux/module.h> 32 #include <linux/dma-buf.h> 33 #include "amdgpu_xgmi.h" 34 #include <uapi/linux/kfd_ioctl.h> 35 #include "amdgpu_ras.h" 36 #include "amdgpu_umc.h" 37 #include "amdgpu_reset.h" 38 39 /* Total memory size in system memory and all GPU VRAM. Used to 40 * estimate worst case amount of memory to reserve for page tables 41 */ 42 uint64_t amdgpu_amdkfd_total_mem_size; 43 44 static bool kfd_initialized; 45 46 int amdgpu_amdkfd_init(void) 47 { 48 struct sysinfo si; 49 int ret; 50 51 si_meminfo(&si); 52 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh; 53 amdgpu_amdkfd_total_mem_size *= si.mem_unit; 54 55 ret = kgd2kfd_init(); 56 kfd_initialized = !ret; 57 58 return ret; 59 } 60 61 void amdgpu_amdkfd_fini(void) 62 { 63 if (kfd_initialized) { 64 kgd2kfd_exit(); 65 kfd_initialized = false; 66 } 67 } 68 69 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev) 70 { 71 bool vf = amdgpu_sriov_vf(adev); 72 73 if (!kfd_initialized) 74 return; 75 76 adev->kfd.dev = kgd2kfd_probe(adev, vf); 77 } 78 79 /** 80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to 81 * setup amdkfd 82 * 83 * @adev: amdgpu_device pointer 84 * @aperture_base: output returning doorbell aperture base physical address 85 * @aperture_size: output returning doorbell aperture size in bytes 86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu. 87 * 88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up, 89 * takes doorbells required for its own rings and reports the setup to amdkfd. 90 * amdgpu reserved doorbells are at the start of the doorbell aperture. 91 */ 92 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 93 phys_addr_t *aperture_base, 94 size_t *aperture_size, 95 size_t *start_offset) 96 { 97 /* 98 * The first num_kernel_doorbells are used by amdgpu. 99 * amdkfd takes whatever's left in the aperture. 100 */ 101 if (adev->enable_mes) { 102 /* 103 * With MES enabled, we only need to initialize 104 * the base address. The size and offset are 105 * not initialized as AMDGPU manages the whole 106 * doorbell space. 107 */ 108 *aperture_base = adev->doorbell.base; 109 *aperture_size = 0; 110 *start_offset = 0; 111 } else if (adev->doorbell.size > adev->doorbell.num_kernel_doorbells * 112 sizeof(u32)) { 113 *aperture_base = adev->doorbell.base; 114 *aperture_size = adev->doorbell.size; 115 *start_offset = adev->doorbell.num_kernel_doorbells * sizeof(u32); 116 } else { 117 *aperture_base = 0; 118 *aperture_size = 0; 119 *start_offset = 0; 120 } 121 } 122 123 124 static void amdgpu_amdkfd_reset_work(struct work_struct *work) 125 { 126 struct amdgpu_device *adev = container_of(work, struct amdgpu_device, 127 kfd.reset_work); 128 129 struct amdgpu_reset_context reset_context; 130 131 memset(&reset_context, 0, sizeof(reset_context)); 132 133 reset_context.method = AMD_RESET_METHOD_NONE; 134 reset_context.reset_req_dev = adev; 135 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); 136 137 amdgpu_device_gpu_recover(adev, NULL, &reset_context); 138 } 139 140 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 141 { 142 int i; 143 int last_valid_bit; 144 145 amdgpu_amdkfd_gpuvm_init_mem_limits(); 146 147 if (adev->kfd.dev) { 148 struct kgd2kfd_shared_resources gpu_resources = { 149 .compute_vmid_bitmap = 150 ((1 << AMDGPU_NUM_VMID) - 1) - 151 ((1 << adev->vm_manager.first_kfd_vmid) - 1), 152 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, 153 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, 154 .gpuvm_size = min(adev->vm_manager.max_pfn 155 << AMDGPU_GPU_PAGE_SHIFT, 156 AMDGPU_GMC_HOLE_START), 157 .drm_render_minor = adev_to_drm(adev)->render->index, 158 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine, 159 .enable_mes = adev->enable_mes, 160 }; 161 162 /* this is going to have a few of the MSBs set that we need to 163 * clear 164 */ 165 bitmap_complement(gpu_resources.cp_queue_bitmap, 166 adev->gfx.mec_bitmap[0].queue_bitmap, 167 KGD_MAX_QUEUES); 168 169 /* According to linux/bitmap.h we shouldn't use bitmap_clear if 170 * nbits is not compile time constant 171 */ 172 last_valid_bit = 1 /* only first MEC can have compute queues */ 173 * adev->gfx.mec.num_pipe_per_mec 174 * adev->gfx.mec.num_queue_per_pipe; 175 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i) 176 clear_bit(i, gpu_resources.cp_queue_bitmap); 177 178 amdgpu_doorbell_get_kfd_info(adev, 179 &gpu_resources.doorbell_physical_address, 180 &gpu_resources.doorbell_aperture_size, 181 &gpu_resources.doorbell_start_offset); 182 183 /* Since SOC15, BIF starts to statically use the 184 * lower 12 bits of doorbell addresses for routing 185 * based on settings in registers like 186 * SDMA0_DOORBELL_RANGE etc.. 187 * In order to route a doorbell to CP engine, the lower 188 * 12 bits of its address has to be outside the range 189 * set for SDMA, VCN, and IH blocks. 190 */ 191 if (adev->asic_type >= CHIP_VEGA10) { 192 gpu_resources.non_cp_doorbells_start = 193 adev->doorbell_index.first_non_cp; 194 gpu_resources.non_cp_doorbells_end = 195 adev->doorbell_index.last_non_cp; 196 } 197 198 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev, 199 &gpu_resources); 200 201 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size; 202 203 INIT_WORK(&adev->kfd.reset_work, amdgpu_amdkfd_reset_work); 204 } 205 } 206 207 void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev) 208 { 209 if (adev->kfd.dev) { 210 kgd2kfd_device_exit(adev->kfd.dev); 211 adev->kfd.dev = NULL; 212 amdgpu_amdkfd_total_mem_size -= adev->gmc.real_vram_size; 213 } 214 } 215 216 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, 217 const void *ih_ring_entry) 218 { 219 if (adev->kfd.dev) 220 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry); 221 } 222 223 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) 224 { 225 if (adev->kfd.dev) 226 kgd2kfd_suspend(adev->kfd.dev, run_pm); 227 } 228 229 int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev) 230 { 231 int r = 0; 232 233 if (adev->kfd.dev) 234 r = kgd2kfd_resume_iommu(adev->kfd.dev); 235 236 return r; 237 } 238 239 int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) 240 { 241 int r = 0; 242 243 if (adev->kfd.dev) 244 r = kgd2kfd_resume(adev->kfd.dev, run_pm); 245 246 return r; 247 } 248 249 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev) 250 { 251 int r = 0; 252 253 if (adev->kfd.dev) 254 r = kgd2kfd_pre_reset(adev->kfd.dev); 255 256 return r; 257 } 258 259 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev) 260 { 261 int r = 0; 262 263 if (adev->kfd.dev) 264 r = kgd2kfd_post_reset(adev->kfd.dev); 265 266 return r; 267 } 268 269 void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) 270 { 271 if (amdgpu_device_should_recover_gpu(adev)) 272 amdgpu_reset_domain_schedule(adev->reset_domain, 273 &adev->kfd.reset_work); 274 } 275 276 int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, 277 void **mem_obj, uint64_t *gpu_addr, 278 void **cpu_ptr, bool cp_mqd_gfx9) 279 { 280 struct amdgpu_bo *bo = NULL; 281 struct amdgpu_bo_param bp; 282 int r; 283 void *cpu_ptr_tmp = NULL; 284 285 memset(&bp, 0, sizeof(bp)); 286 bp.size = size; 287 bp.byte_align = PAGE_SIZE; 288 bp.domain = AMDGPU_GEM_DOMAIN_GTT; 289 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; 290 bp.type = ttm_bo_type_kernel; 291 bp.resv = NULL; 292 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 293 294 if (cp_mqd_gfx9) 295 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9; 296 297 r = amdgpu_bo_create(adev, &bp, &bo); 298 if (r) { 299 dev_err(adev->dev, 300 "failed to allocate BO for amdkfd (%d)\n", r); 301 return r; 302 } 303 304 /* map the buffer */ 305 r = amdgpu_bo_reserve(bo, true); 306 if (r) { 307 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r); 308 goto allocate_mem_reserve_bo_failed; 309 } 310 311 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); 312 if (r) { 313 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r); 314 goto allocate_mem_pin_bo_failed; 315 } 316 317 r = amdgpu_ttm_alloc_gart(&bo->tbo); 318 if (r) { 319 dev_err(adev->dev, "%p bind failed\n", bo); 320 goto allocate_mem_kmap_bo_failed; 321 } 322 323 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp); 324 if (r) { 325 dev_err(adev->dev, 326 "(%d) failed to map bo to kernel for amdkfd\n", r); 327 goto allocate_mem_kmap_bo_failed; 328 } 329 330 *mem_obj = bo; 331 *gpu_addr = amdgpu_bo_gpu_offset(bo); 332 *cpu_ptr = cpu_ptr_tmp; 333 334 amdgpu_bo_unreserve(bo); 335 336 return 0; 337 338 allocate_mem_kmap_bo_failed: 339 amdgpu_bo_unpin(bo); 340 allocate_mem_pin_bo_failed: 341 amdgpu_bo_unreserve(bo); 342 allocate_mem_reserve_bo_failed: 343 amdgpu_bo_unref(&bo); 344 345 return r; 346 } 347 348 void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj) 349 { 350 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj; 351 352 amdgpu_bo_reserve(bo, true); 353 amdgpu_bo_kunmap(bo); 354 amdgpu_bo_unpin(bo); 355 amdgpu_bo_unreserve(bo); 356 amdgpu_bo_unref(&(bo)); 357 } 358 359 int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, 360 void **mem_obj) 361 { 362 struct amdgpu_bo *bo = NULL; 363 struct amdgpu_bo_user *ubo; 364 struct amdgpu_bo_param bp; 365 int r; 366 367 memset(&bp, 0, sizeof(bp)); 368 bp.size = size; 369 bp.byte_align = 1; 370 bp.domain = AMDGPU_GEM_DOMAIN_GWS; 371 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS; 372 bp.type = ttm_bo_type_device; 373 bp.resv = NULL; 374 bp.bo_ptr_size = sizeof(struct amdgpu_bo); 375 376 r = amdgpu_bo_create_user(adev, &bp, &ubo); 377 if (r) { 378 dev_err(adev->dev, 379 "failed to allocate gws BO for amdkfd (%d)\n", r); 380 return r; 381 } 382 383 bo = &ubo->bo; 384 *mem_obj = bo; 385 return 0; 386 } 387 388 void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj) 389 { 390 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj; 391 392 amdgpu_bo_unref(&bo); 393 } 394 395 uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev, 396 enum kgd_engine_type type) 397 { 398 switch (type) { 399 case KGD_ENGINE_PFP: 400 return adev->gfx.pfp_fw_version; 401 402 case KGD_ENGINE_ME: 403 return adev->gfx.me_fw_version; 404 405 case KGD_ENGINE_CE: 406 return adev->gfx.ce_fw_version; 407 408 case KGD_ENGINE_MEC1: 409 return adev->gfx.mec_fw_version; 410 411 case KGD_ENGINE_MEC2: 412 return adev->gfx.mec2_fw_version; 413 414 case KGD_ENGINE_RLC: 415 return adev->gfx.rlc_fw_version; 416 417 case KGD_ENGINE_SDMA1: 418 return adev->sdma.instance[0].fw_version; 419 420 case KGD_ENGINE_SDMA2: 421 return adev->sdma.instance[1].fw_version; 422 423 default: 424 return 0; 425 } 426 427 return 0; 428 } 429 430 void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev, 431 struct kfd_local_mem_info *mem_info) 432 { 433 memset(mem_info, 0, sizeof(*mem_info)); 434 435 mem_info->local_mem_size_public = adev->gmc.visible_vram_size; 436 mem_info->local_mem_size_private = adev->gmc.real_vram_size - 437 adev->gmc.visible_vram_size; 438 439 mem_info->vram_width = adev->gmc.vram_width; 440 441 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n", 442 &adev->gmc.aper_base, 443 mem_info->local_mem_size_public, 444 mem_info->local_mem_size_private); 445 446 if (amdgpu_sriov_vf(adev)) 447 mem_info->mem_clk_max = adev->clock.default_mclk / 100; 448 else if (adev->pm.dpm_enabled) { 449 if (amdgpu_emu_mode == 1) 450 mem_info->mem_clk_max = 0; 451 else 452 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100; 453 } else 454 mem_info->mem_clk_max = 100; 455 } 456 457 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev) 458 { 459 if (adev->gfx.funcs->get_gpu_clock_counter) 460 return adev->gfx.funcs->get_gpu_clock_counter(adev); 461 return 0; 462 } 463 464 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev) 465 { 466 /* the sclk is in quantas of 10kHz */ 467 if (amdgpu_sriov_vf(adev)) 468 return adev->clock.default_sclk / 100; 469 else if (adev->pm.dpm_enabled) 470 return amdgpu_dpm_get_sclk(adev, false) / 100; 471 else 472 return 100; 473 } 474 475 void amdgpu_amdkfd_get_cu_info(struct amdgpu_device *adev, struct kfd_cu_info *cu_info) 476 { 477 struct amdgpu_cu_info acu_info = adev->gfx.cu_info; 478 479 memset(cu_info, 0, sizeof(*cu_info)); 480 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap)) 481 return; 482 483 cu_info->cu_active_number = acu_info.number; 484 cu_info->cu_ao_mask = acu_info.ao_cu_mask; 485 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0], 486 sizeof(acu_info.bitmap)); 487 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines; 488 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 489 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh; 490 cu_info->simd_per_cu = acu_info.simd_per_cu; 491 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd; 492 cu_info->wave_front_size = acu_info.wave_front_size; 493 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu; 494 cu_info->lds_size = acu_info.lds_size; 495 } 496 497 int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, 498 struct amdgpu_device **dmabuf_adev, 499 uint64_t *bo_size, void *metadata_buffer, 500 size_t buffer_size, uint32_t *metadata_size, 501 uint32_t *flags, int8_t *xcp_id) 502 { 503 struct dma_buf *dma_buf; 504 struct drm_gem_object *obj; 505 struct amdgpu_bo *bo; 506 uint64_t metadata_flags; 507 int r = -EINVAL; 508 509 dma_buf = dma_buf_get(dma_buf_fd); 510 if (IS_ERR(dma_buf)) 511 return PTR_ERR(dma_buf); 512 513 if (dma_buf->ops != &amdgpu_dmabuf_ops) 514 /* Can't handle non-graphics buffers */ 515 goto out_put; 516 517 obj = dma_buf->priv; 518 if (obj->dev->driver != adev_to_drm(adev)->driver) 519 /* Can't handle buffers from different drivers */ 520 goto out_put; 521 522 adev = drm_to_adev(obj->dev); 523 bo = gem_to_amdgpu_bo(obj); 524 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM | 525 AMDGPU_GEM_DOMAIN_GTT))) 526 /* Only VRAM and GTT BOs are supported */ 527 goto out_put; 528 529 r = 0; 530 if (dmabuf_adev) 531 *dmabuf_adev = adev; 532 if (bo_size) 533 *bo_size = amdgpu_bo_size(bo); 534 if (metadata_buffer) 535 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size, 536 metadata_size, &metadata_flags); 537 if (flags) { 538 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? 539 KFD_IOC_ALLOC_MEM_FLAGS_VRAM 540 : KFD_IOC_ALLOC_MEM_FLAGS_GTT; 541 542 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) 543 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC; 544 } 545 if (xcp_id) 546 *xcp_id = bo->xcp_id; 547 548 out_put: 549 dma_buf_put(dma_buf); 550 return r; 551 } 552 553 uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, 554 struct amdgpu_device *src) 555 { 556 struct amdgpu_device *peer_adev = src; 557 struct amdgpu_device *adev = dst; 558 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev); 559 560 if (ret < 0) { 561 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n", 562 adev->gmc.xgmi.physical_node_id, 563 peer_adev->gmc.xgmi.physical_node_id, ret); 564 ret = 0; 565 } 566 return (uint8_t)ret; 567 } 568 569 int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, 570 struct amdgpu_device *src, 571 bool is_min) 572 { 573 struct amdgpu_device *adev = dst, *peer_adev; 574 int num_links; 575 576 if (adev->asic_type != CHIP_ALDEBARAN) 577 return 0; 578 579 if (src) 580 peer_adev = src; 581 582 /* num links returns 0 for indirect peers since indirect route is unknown. */ 583 num_links = is_min ? 1 : amdgpu_xgmi_get_num_links(adev, peer_adev); 584 if (num_links < 0) { 585 DRM_ERROR("amdgpu: failed to get xgmi num links between node %d and %d. ret = %d\n", 586 adev->gmc.xgmi.physical_node_id, 587 peer_adev->gmc.xgmi.physical_node_id, num_links); 588 num_links = 0; 589 } 590 591 /* Aldebaran xGMI DPM is defeatured so assume x16 x 25Gbps for bandwidth. */ 592 return (num_links * 16 * 25000)/BITS_PER_BYTE; 593 } 594 595 int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min) 596 { 597 int num_lanes_shift = (is_min ? ffs(adev->pm.pcie_mlw_mask) : 598 fls(adev->pm.pcie_mlw_mask)) - 1; 599 int gen_speed_shift = (is_min ? ffs(adev->pm.pcie_gen_mask & 600 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) : 601 fls(adev->pm.pcie_gen_mask & 602 CAIL_PCIE_LINK_SPEED_SUPPORT_MASK)) - 1; 603 uint32_t num_lanes_mask = 1 << num_lanes_shift; 604 uint32_t gen_speed_mask = 1 << gen_speed_shift; 605 int num_lanes_factor = 0, gen_speed_mbits_factor = 0; 606 607 switch (num_lanes_mask) { 608 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X1: 609 num_lanes_factor = 1; 610 break; 611 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X2: 612 num_lanes_factor = 2; 613 break; 614 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X4: 615 num_lanes_factor = 4; 616 break; 617 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X8: 618 num_lanes_factor = 8; 619 break; 620 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X12: 621 num_lanes_factor = 12; 622 break; 623 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X16: 624 num_lanes_factor = 16; 625 break; 626 case CAIL_PCIE_LINK_WIDTH_SUPPORT_X32: 627 num_lanes_factor = 32; 628 break; 629 } 630 631 switch (gen_speed_mask) { 632 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1: 633 gen_speed_mbits_factor = 2500; 634 break; 635 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2: 636 gen_speed_mbits_factor = 5000; 637 break; 638 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3: 639 gen_speed_mbits_factor = 8000; 640 break; 641 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4: 642 gen_speed_mbits_factor = 16000; 643 break; 644 case CAIL_PCIE_LINK_SPEED_SUPPORT_GEN5: 645 gen_speed_mbits_factor = 32000; 646 break; 647 } 648 649 return (num_lanes_factor * gen_speed_mbits_factor)/BITS_PER_BYTE; 650 } 651 652 int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, 653 enum kgd_engine_type engine, 654 uint32_t vmid, uint64_t gpu_addr, 655 uint32_t *ib_cmd, uint32_t ib_len) 656 { 657 struct amdgpu_job *job; 658 struct amdgpu_ib *ib; 659 struct amdgpu_ring *ring; 660 struct dma_fence *f = NULL; 661 int ret; 662 663 switch (engine) { 664 case KGD_ENGINE_MEC1: 665 ring = &adev->gfx.compute_ring[0]; 666 break; 667 case KGD_ENGINE_SDMA1: 668 ring = &adev->sdma.instance[0].ring; 669 break; 670 case KGD_ENGINE_SDMA2: 671 ring = &adev->sdma.instance[1].ring; 672 break; 673 default: 674 pr_err("Invalid engine in IB submission: %d\n", engine); 675 ret = -EINVAL; 676 goto err; 677 } 678 679 ret = amdgpu_job_alloc(adev, NULL, NULL, NULL, 1, &job); 680 if (ret) 681 goto err; 682 683 ib = &job->ibs[0]; 684 memset(ib, 0, sizeof(struct amdgpu_ib)); 685 686 ib->gpu_addr = gpu_addr; 687 ib->ptr = ib_cmd; 688 ib->length_dw = ib_len; 689 /* This works for NO_HWS. TODO: need to handle without knowing VMID */ 690 job->vmid = vmid; 691 job->num_ibs = 1; 692 693 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f); 694 695 if (ret) { 696 DRM_ERROR("amdgpu: failed to schedule IB.\n"); 697 goto err_ib_sched; 698 } 699 700 /* Drop the initial kref_init count (see drm_sched_main as example) */ 701 dma_fence_put(f); 702 ret = dma_fence_wait(f, false); 703 704 err_ib_sched: 705 amdgpu_job_free(job); 706 err: 707 return ret; 708 } 709 710 void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle) 711 { 712 /* Temporary workaround to fix issues observed in some 713 * compute applications when GFXOFF is enabled on GFX11. 714 */ 715 if (IP_VERSION_MAJ(adev->ip_versions[GC_HWIP][0]) == 11) { 716 pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled"); 717 amdgpu_gfx_off_ctrl(adev, idle); 718 } 719 amdgpu_dpm_switch_power_profile(adev, 720 PP_SMC_POWER_PROFILE_COMPUTE, 721 !idle); 722 } 723 724 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid) 725 { 726 if (adev->kfd.dev) 727 return vmid >= adev->vm_manager.first_kfd_vmid; 728 729 return false; 730 } 731 732 int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct amdgpu_device *adev, 733 uint16_t vmid) 734 { 735 if (adev->family == AMDGPU_FAMILY_AI) { 736 int i; 737 738 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) 739 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0); 740 } else { 741 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB(0), 0); 742 } 743 744 return 0; 745 } 746 747 int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct amdgpu_device *adev, 748 uint16_t pasid, 749 enum TLB_FLUSH_TYPE flush_type, 750 uint32_t inst) 751 { 752 bool all_hub = false; 753 754 if (adev->family == AMDGPU_FAMILY_AI || 755 adev->family == AMDGPU_FAMILY_RV) 756 all_hub = true; 757 758 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub, inst); 759 } 760 761 bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev) 762 { 763 return adev->have_atomics_support; 764 } 765 766 void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev, bool reset) 767 { 768 amdgpu_umc_poison_handler(adev, reset); 769 } 770 771 bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev) 772 { 773 if (adev->gfx.ras && adev->gfx.ras->query_utcl2_poison_status) 774 return adev->gfx.ras->query_utcl2_poison_status(adev); 775 else 776 return false; 777 } 778 779 int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) 780 { 781 return kgd2kfd_check_and_lock_kfd(); 782 } 783 784 void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev) 785 { 786 kgd2kfd_unlock_kfd(); 787 } 788