1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 
23 #include "amdgpu_amdkfd.h"
24 #include "amd_shared.h"
25 #include <drm/drmP.h>
26 #include "amdgpu.h"
27 #include "amdgpu_gfx.h"
28 #include <linux/module.h>
29 #include <linux/dma-buf.h>
30 
31 static const unsigned int compute_vmid_bitmap = 0xFF00;
32 
33 /* Total memory size in system memory and all GPU VRAM. Used to
34  * estimate worst case amount of memory to reserve for page tables
35  */
36 uint64_t amdgpu_amdkfd_total_mem_size;
37 
38 int amdgpu_amdkfd_init(void)
39 {
40 	struct sysinfo si;
41 	int ret;
42 
43 	si_meminfo(&si);
44 	amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
45 	amdgpu_amdkfd_total_mem_size *= si.mem_unit;
46 
47 #ifdef CONFIG_HSA_AMD
48 	ret = kgd2kfd_init();
49 	amdgpu_amdkfd_gpuvm_init_mem_limits();
50 #else
51 	ret = -ENOENT;
52 #endif
53 
54 	return ret;
55 }
56 
57 void amdgpu_amdkfd_fini(void)
58 {
59 	kgd2kfd_exit();
60 }
61 
62 void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
63 {
64 	const struct kfd2kgd_calls *kfd2kgd;
65 
66 	switch (adev->asic_type) {
67 #ifdef CONFIG_DRM_AMDGPU_CIK
68 	case CHIP_KAVERI:
69 	case CHIP_HAWAII:
70 		kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
71 		break;
72 #endif
73 	case CHIP_CARRIZO:
74 	case CHIP_TONGA:
75 	case CHIP_FIJI:
76 	case CHIP_POLARIS10:
77 	case CHIP_POLARIS11:
78 	case CHIP_POLARIS12:
79 		kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
80 		break;
81 	case CHIP_VEGA10:
82 	case CHIP_VEGA12:
83 	case CHIP_VEGA20:
84 	case CHIP_RAVEN:
85 		kfd2kgd = amdgpu_amdkfd_gfx_9_0_get_functions();
86 		break;
87 	default:
88 		dev_info(adev->dev, "kfd not supported on this ASIC\n");
89 		return;
90 	}
91 
92 	adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
93 				      adev->pdev, kfd2kgd);
94 
95 	if (adev->kfd.dev)
96 		amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
97 }
98 
99 /**
100  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
101  *                                setup amdkfd
102  *
103  * @adev: amdgpu_device pointer
104  * @aperture_base: output returning doorbell aperture base physical address
105  * @aperture_size: output returning doorbell aperture size in bytes
106  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
107  *
108  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
109  * takes doorbells required for its own rings and reports the setup to amdkfd.
110  * amdgpu reserved doorbells are at the start of the doorbell aperture.
111  */
112 static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
113 					 phys_addr_t *aperture_base,
114 					 size_t *aperture_size,
115 					 size_t *start_offset)
116 {
117 	/*
118 	 * The first num_doorbells are used by amdgpu.
119 	 * amdkfd takes whatever's left in the aperture.
120 	 */
121 	if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
122 		*aperture_base = adev->doorbell.base;
123 		*aperture_size = adev->doorbell.size;
124 		*start_offset = adev->doorbell.num_doorbells * sizeof(u32);
125 	} else {
126 		*aperture_base = 0;
127 		*aperture_size = 0;
128 		*start_offset = 0;
129 	}
130 }
131 
132 void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
133 {
134 	int i;
135 	int last_valid_bit;
136 
137 	if (adev->kfd.dev) {
138 		struct kgd2kfd_shared_resources gpu_resources = {
139 			.compute_vmid_bitmap = compute_vmid_bitmap,
140 			.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
141 			.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
142 			.gpuvm_size = min(adev->vm_manager.max_pfn
143 					  << AMDGPU_GPU_PAGE_SHIFT,
144 					  AMDGPU_GMC_HOLE_START),
145 			.drm_render_minor = adev->ddev->render->index,
146 			.sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
147 
148 		};
149 
150 		/* this is going to have a few of the MSBs set that we need to
151 		 * clear */
152 		bitmap_complement(gpu_resources.queue_bitmap,
153 				  adev->gfx.mec.queue_bitmap,
154 				  KGD_MAX_QUEUES);
155 
156 		/* remove the KIQ bit as well */
157 		if (adev->gfx.kiq.ring.sched.ready)
158 			clear_bit(amdgpu_gfx_queue_to_bit(adev,
159 							  adev->gfx.kiq.ring.me - 1,
160 							  adev->gfx.kiq.ring.pipe,
161 							  adev->gfx.kiq.ring.queue),
162 				  gpu_resources.queue_bitmap);
163 
164 		/* According to linux/bitmap.h we shouldn't use bitmap_clear if
165 		 * nbits is not compile time constant */
166 		last_valid_bit = 1 /* only first MEC can have compute queues */
167 				* adev->gfx.mec.num_pipe_per_mec
168 				* adev->gfx.mec.num_queue_per_pipe;
169 		for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
170 			clear_bit(i, gpu_resources.queue_bitmap);
171 
172 		amdgpu_doorbell_get_kfd_info(adev,
173 				&gpu_resources.doorbell_physical_address,
174 				&gpu_resources.doorbell_aperture_size,
175 				&gpu_resources.doorbell_start_offset);
176 
177 		/* Since SOC15, BIF starts to statically use the
178 		 * lower 12 bits of doorbell addresses for routing
179 		 * based on settings in registers like
180 		 * SDMA0_DOORBELL_RANGE etc..
181 		 * In order to route a doorbell to CP engine, the lower
182 		 * 12 bits of its address has to be outside the range
183 		 * set for SDMA, VCN, and IH blocks.
184 		 */
185 		if (adev->asic_type >= CHIP_VEGA10) {
186 			gpu_resources.non_cp_doorbells_start =
187 					adev->doorbell_index.first_non_cp;
188 			gpu_resources.non_cp_doorbells_end =
189 					adev->doorbell_index.last_non_cp;
190 		}
191 
192 		kgd2kfd_device_init(adev->kfd.dev, &gpu_resources);
193 	}
194 }
195 
196 void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
197 {
198 	if (adev->kfd.dev) {
199 		kgd2kfd_device_exit(adev->kfd.dev);
200 		adev->kfd.dev = NULL;
201 	}
202 }
203 
204 void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
205 		const void *ih_ring_entry)
206 {
207 	if (adev->kfd.dev)
208 		kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
209 }
210 
211 void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
212 {
213 	if (adev->kfd.dev)
214 		kgd2kfd_suspend(adev->kfd.dev);
215 }
216 
217 int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
218 {
219 	int r = 0;
220 
221 	if (adev->kfd.dev)
222 		r = kgd2kfd_resume(adev->kfd.dev);
223 
224 	return r;
225 }
226 
227 int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
228 {
229 	int r = 0;
230 
231 	if (adev->kfd.dev)
232 		r = kgd2kfd_pre_reset(adev->kfd.dev);
233 
234 	return r;
235 }
236 
237 int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
238 {
239 	int r = 0;
240 
241 	if (adev->kfd.dev)
242 		r = kgd2kfd_post_reset(adev->kfd.dev);
243 
244 	return r;
245 }
246 
247 void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
248 {
249 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
250 
251 	if (amdgpu_device_should_recover_gpu(adev))
252 		amdgpu_device_gpu_recover(adev, NULL);
253 }
254 
255 int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
256 				void **mem_obj, uint64_t *gpu_addr,
257 				void **cpu_ptr, bool mqd_gfx9)
258 {
259 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
260 	struct amdgpu_bo *bo = NULL;
261 	struct amdgpu_bo_param bp;
262 	int r;
263 	void *cpu_ptr_tmp = NULL;
264 
265 	memset(&bp, 0, sizeof(bp));
266 	bp.size = size;
267 	bp.byte_align = PAGE_SIZE;
268 	bp.domain = AMDGPU_GEM_DOMAIN_GTT;
269 	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
270 	bp.type = ttm_bo_type_kernel;
271 	bp.resv = NULL;
272 
273 	if (mqd_gfx9)
274 		bp.flags |= AMDGPU_GEM_CREATE_MQD_GFX9;
275 
276 	r = amdgpu_bo_create(adev, &bp, &bo);
277 	if (r) {
278 		dev_err(adev->dev,
279 			"failed to allocate BO for amdkfd (%d)\n", r);
280 		return r;
281 	}
282 
283 	/* map the buffer */
284 	r = amdgpu_bo_reserve(bo, true);
285 	if (r) {
286 		dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
287 		goto allocate_mem_reserve_bo_failed;
288 	}
289 
290 	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
291 	if (r) {
292 		dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
293 		goto allocate_mem_pin_bo_failed;
294 	}
295 
296 	r = amdgpu_ttm_alloc_gart(&bo->tbo);
297 	if (r) {
298 		dev_err(adev->dev, "%p bind failed\n", bo);
299 		goto allocate_mem_kmap_bo_failed;
300 	}
301 
302 	r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
303 	if (r) {
304 		dev_err(adev->dev,
305 			"(%d) failed to map bo to kernel for amdkfd\n", r);
306 		goto allocate_mem_kmap_bo_failed;
307 	}
308 
309 	*mem_obj = bo;
310 	*gpu_addr = amdgpu_bo_gpu_offset(bo);
311 	*cpu_ptr = cpu_ptr_tmp;
312 
313 	amdgpu_bo_unreserve(bo);
314 
315 	return 0;
316 
317 allocate_mem_kmap_bo_failed:
318 	amdgpu_bo_unpin(bo);
319 allocate_mem_pin_bo_failed:
320 	amdgpu_bo_unreserve(bo);
321 allocate_mem_reserve_bo_failed:
322 	amdgpu_bo_unref(&bo);
323 
324 	return r;
325 }
326 
327 void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
328 {
329 	struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
330 
331 	amdgpu_bo_reserve(bo, true);
332 	amdgpu_bo_kunmap(bo);
333 	amdgpu_bo_unpin(bo);
334 	amdgpu_bo_unreserve(bo);
335 	amdgpu_bo_unref(&(bo));
336 }
337 
338 uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
339 				      enum kgd_engine_type type)
340 {
341 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
342 
343 	switch (type) {
344 	case KGD_ENGINE_PFP:
345 		return adev->gfx.pfp_fw_version;
346 
347 	case KGD_ENGINE_ME:
348 		return adev->gfx.me_fw_version;
349 
350 	case KGD_ENGINE_CE:
351 		return adev->gfx.ce_fw_version;
352 
353 	case KGD_ENGINE_MEC1:
354 		return adev->gfx.mec_fw_version;
355 
356 	case KGD_ENGINE_MEC2:
357 		return adev->gfx.mec2_fw_version;
358 
359 	case KGD_ENGINE_RLC:
360 		return adev->gfx.rlc_fw_version;
361 
362 	case KGD_ENGINE_SDMA1:
363 		return adev->sdma.instance[0].fw_version;
364 
365 	case KGD_ENGINE_SDMA2:
366 		return adev->sdma.instance[1].fw_version;
367 
368 	default:
369 		return 0;
370 	}
371 
372 	return 0;
373 }
374 
375 void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
376 				      struct kfd_local_mem_info *mem_info)
377 {
378 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
379 	uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
380 					     ~((1ULL << 32) - 1);
381 	resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
382 
383 	memset(mem_info, 0, sizeof(*mem_info));
384 	if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
385 		mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
386 		mem_info->local_mem_size_private = adev->gmc.real_vram_size -
387 				adev->gmc.visible_vram_size;
388 	} else {
389 		mem_info->local_mem_size_public = 0;
390 		mem_info->local_mem_size_private = adev->gmc.real_vram_size;
391 	}
392 	mem_info->vram_width = adev->gmc.vram_width;
393 
394 	pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
395 			&adev->gmc.aper_base, &aper_limit,
396 			mem_info->local_mem_size_public,
397 			mem_info->local_mem_size_private);
398 
399 	if (amdgpu_sriov_vf(adev))
400 		mem_info->mem_clk_max = adev->clock.default_mclk / 100;
401 	else if (adev->powerplay.pp_funcs)
402 		mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
403 	else
404 		mem_info->mem_clk_max = 100;
405 }
406 
407 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
408 {
409 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
410 
411 	if (adev->gfx.funcs->get_gpu_clock_counter)
412 		return adev->gfx.funcs->get_gpu_clock_counter(adev);
413 	return 0;
414 }
415 
416 uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
417 {
418 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
419 
420 	/* the sclk is in quantas of 10kHz */
421 	if (amdgpu_sriov_vf(adev))
422 		return adev->clock.default_sclk / 100;
423 	else if (adev->powerplay.pp_funcs)
424 		return amdgpu_dpm_get_sclk(adev, false) / 100;
425 	else
426 		return 100;
427 }
428 
429 void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
430 {
431 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
432 	struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
433 
434 	memset(cu_info, 0, sizeof(*cu_info));
435 	if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
436 		return;
437 
438 	cu_info->cu_active_number = acu_info.number;
439 	cu_info->cu_ao_mask = acu_info.ao_cu_mask;
440 	memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
441 	       sizeof(acu_info.bitmap));
442 	cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
443 	cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
444 	cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
445 	cu_info->simd_per_cu = acu_info.simd_per_cu;
446 	cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
447 	cu_info->wave_front_size = acu_info.wave_front_size;
448 	cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
449 	cu_info->lds_size = acu_info.lds_size;
450 }
451 
452 int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
453 				  struct kgd_dev **dma_buf_kgd,
454 				  uint64_t *bo_size, void *metadata_buffer,
455 				  size_t buffer_size, uint32_t *metadata_size,
456 				  uint32_t *flags)
457 {
458 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
459 	struct dma_buf *dma_buf;
460 	struct drm_gem_object *obj;
461 	struct amdgpu_bo *bo;
462 	uint64_t metadata_flags;
463 	int r = -EINVAL;
464 
465 	dma_buf = dma_buf_get(dma_buf_fd);
466 	if (IS_ERR(dma_buf))
467 		return PTR_ERR(dma_buf);
468 
469 	if (dma_buf->ops != &amdgpu_dmabuf_ops)
470 		/* Can't handle non-graphics buffers */
471 		goto out_put;
472 
473 	obj = dma_buf->priv;
474 	if (obj->dev->driver != adev->ddev->driver)
475 		/* Can't handle buffers from different drivers */
476 		goto out_put;
477 
478 	adev = obj->dev->dev_private;
479 	bo = gem_to_amdgpu_bo(obj);
480 	if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
481 				    AMDGPU_GEM_DOMAIN_GTT)))
482 		/* Only VRAM and GTT BOs are supported */
483 		goto out_put;
484 
485 	r = 0;
486 	if (dma_buf_kgd)
487 		*dma_buf_kgd = (struct kgd_dev *)adev;
488 	if (bo_size)
489 		*bo_size = amdgpu_bo_size(bo);
490 	if (metadata_size)
491 		*metadata_size = bo->metadata_size;
492 	if (metadata_buffer)
493 		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
494 					   metadata_size, &metadata_flags);
495 	if (flags) {
496 		*flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
497 			ALLOC_MEM_FLAGS_VRAM : ALLOC_MEM_FLAGS_GTT;
498 
499 		if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
500 			*flags |= ALLOC_MEM_FLAGS_PUBLIC;
501 	}
502 
503 out_put:
504 	dma_buf_put(dma_buf);
505 	return r;
506 }
507 
508 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
509 {
510 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
511 
512 	return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
513 }
514 
515 uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
516 {
517 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
518 
519 	return adev->gmc.xgmi.hive_id;
520 }
521 
522 int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
523 				uint32_t vmid, uint64_t gpu_addr,
524 				uint32_t *ib_cmd, uint32_t ib_len)
525 {
526 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
527 	struct amdgpu_job *job;
528 	struct amdgpu_ib *ib;
529 	struct amdgpu_ring *ring;
530 	struct dma_fence *f = NULL;
531 	int ret;
532 
533 	switch (engine) {
534 	case KGD_ENGINE_MEC1:
535 		ring = &adev->gfx.compute_ring[0];
536 		break;
537 	case KGD_ENGINE_SDMA1:
538 		ring = &adev->sdma.instance[0].ring;
539 		break;
540 	case KGD_ENGINE_SDMA2:
541 		ring = &adev->sdma.instance[1].ring;
542 		break;
543 	default:
544 		pr_err("Invalid engine in IB submission: %d\n", engine);
545 		ret = -EINVAL;
546 		goto err;
547 	}
548 
549 	ret = amdgpu_job_alloc(adev, 1, &job, NULL);
550 	if (ret)
551 		goto err;
552 
553 	ib = &job->ibs[0];
554 	memset(ib, 0, sizeof(struct amdgpu_ib));
555 
556 	ib->gpu_addr = gpu_addr;
557 	ib->ptr = ib_cmd;
558 	ib->length_dw = ib_len;
559 	/* This works for NO_HWS. TODO: need to handle without knowing VMID */
560 	job->vmid = vmid;
561 
562 	ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
563 	if (ret) {
564 		DRM_ERROR("amdgpu: failed to schedule IB.\n");
565 		goto err_ib_sched;
566 	}
567 
568 	ret = dma_fence_wait(f, false);
569 
570 err_ib_sched:
571 	dma_fence_put(f);
572 	amdgpu_job_free(job);
573 err:
574 	return ret;
575 }
576 
577 void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
578 {
579 	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
580 
581 	if (adev->powerplay.pp_funcs &&
582 	    adev->powerplay.pp_funcs->switch_power_profile)
583 		amdgpu_dpm_switch_power_profile(adev,
584 						PP_SMC_POWER_PROFILE_COMPUTE,
585 						!idle);
586 }
587 
588 bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
589 {
590 	if (adev->kfd.dev) {
591 		if ((1 << vmid) & compute_vmid_bitmap)
592 			return true;
593 	}
594 
595 	return false;
596 }
597 
598 #ifndef CONFIG_HSA_AMD
599 bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
600 {
601 	return false;
602 }
603 
604 void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
605 {
606 }
607 
608 void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
609 					struct amdgpu_vm *vm)
610 {
611 }
612 
613 struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
614 {
615 	return NULL;
616 }
617 
618 int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
619 {
620 	return 0;
621 }
622 
623 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void)
624 {
625 	return NULL;
626 }
627 
628 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void)
629 {
630 	return NULL;
631 }
632 
633 struct kfd2kgd_calls *amdgpu_amdkfd_gfx_9_0_get_functions(void)
634 {
635 	return NULL;
636 }
637 
638 struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
639 			      const struct kfd2kgd_calls *f2g)
640 {
641 	return NULL;
642 }
643 
644 bool kgd2kfd_device_init(struct kfd_dev *kfd,
645 			 const struct kgd2kfd_shared_resources *gpu_resources)
646 {
647 	return false;
648 }
649 
650 void kgd2kfd_device_exit(struct kfd_dev *kfd)
651 {
652 }
653 
654 void kgd2kfd_exit(void)
655 {
656 }
657 
658 void kgd2kfd_suspend(struct kfd_dev *kfd)
659 {
660 }
661 
662 int kgd2kfd_resume(struct kfd_dev *kfd)
663 {
664 	return 0;
665 }
666 
667 int kgd2kfd_pre_reset(struct kfd_dev *kfd)
668 {
669 	return 0;
670 }
671 
672 int kgd2kfd_post_reset(struct kfd_dev *kfd)
673 {
674 	return 0;
675 }
676 
677 void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
678 {
679 }
680 
681 void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
682 {
683 }
684 #endif
685