1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/irqdomain.h> 27 #include <linux/pci.h> 28 #include <linux/pm_domain.h> 29 #include <linux/platform_device.h> 30 #include <sound/designware_i2s.h> 31 #include <sound/pcm.h> 32 33 #include "amdgpu.h" 34 #include "atom.h" 35 #include "amdgpu_acp.h" 36 37 #include "acp_gfx_if.h" 38 39 #define ACP_TILE_ON_MASK 0x03 40 #define ACP_TILE_OFF_MASK 0x02 41 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 42 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 43 44 #define ACP_TILE_P1_MASK 0x3e 45 #define ACP_TILE_P2_MASK 0x3d 46 #define ACP_TILE_DSP0_MASK 0x3b 47 #define ACP_TILE_DSP1_MASK 0x37 48 49 #define ACP_TILE_DSP2_MASK 0x2f 50 51 #define ACP_DMA_REGS_END 0x146c0 52 #define ACP_I2S_PLAY_REGS_START 0x14840 53 #define ACP_I2S_PLAY_REGS_END 0x148b4 54 #define ACP_I2S_CAP_REGS_START 0x148b8 55 #define ACP_I2S_CAP_REGS_END 0x1496c 56 57 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 58 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 59 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 60 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 61 #define ACP_BT_PLAY_REGS_START 0x14970 62 #define ACP_BT_PLAY_REGS_END 0x14a24 63 #define ACP_BT_COMP1_REG_OFFSET 0xac 64 #define ACP_BT_COMP2_REG_OFFSET 0xa8 65 66 #define mmACP_PGFSM_RETAIN_REG 0x51c9 67 #define mmACP_PGFSM_CONFIG_REG 0x51ca 68 #define mmACP_PGFSM_READ_REG_0 0x51cc 69 70 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 71 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 72 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 73 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 74 75 #define mmACP_CONTROL 0x5131 76 #define mmACP_STATUS 0x5133 77 #define mmACP_SOFT_RESET 0x5134 78 #define ACP_CONTROL__ClkEn_MASK 0x1 79 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 80 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 81 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 82 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 83 84 #define ACP_TIMEOUT_LOOP 0x000000FF 85 #define ACP_DEVS 4 86 #define ACP_SRC_ID 162 87 88 enum { 89 ACP_TILE_P1 = 0, 90 ACP_TILE_P2, 91 ACP_TILE_DSP0, 92 ACP_TILE_DSP1, 93 ACP_TILE_DSP2, 94 }; 95 96 static int acp_sw_init(void *handle) 97 { 98 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99 100 adev->acp.parent = adev->dev; 101 102 adev->acp.cgs_device = 103 amdgpu_cgs_create_device(adev); 104 if (!adev->acp.cgs_device) 105 return -EINVAL; 106 107 return 0; 108 } 109 110 static int acp_sw_fini(void *handle) 111 { 112 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 113 114 if (adev->acp.cgs_device) 115 amdgpu_cgs_destroy_device(adev->acp.cgs_device); 116 117 return 0; 118 } 119 120 struct acp_pm_domain { 121 void *adev; 122 struct generic_pm_domain gpd; 123 }; 124 125 static int acp_poweroff(struct generic_pm_domain *genpd) 126 { 127 struct acp_pm_domain *apd; 128 struct amdgpu_device *adev; 129 130 apd = container_of(genpd, struct acp_pm_domain, gpd); 131 adev = apd->adev; 132 /* call smu to POWER GATE ACP block 133 * smu will 134 * 1. turn off the acp clock 135 * 2. power off the acp tiles 136 * 3. check and enter ulv state 137 */ 138 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 139 return 0; 140 } 141 142 static int acp_poweron(struct generic_pm_domain *genpd) 143 { 144 struct acp_pm_domain *apd; 145 struct amdgpu_device *adev; 146 147 apd = container_of(genpd, struct acp_pm_domain, gpd); 148 adev = apd->adev; 149 /* call smu to UNGATE ACP block 150 * smu will 151 * 1. exit ulv 152 * 2. turn on acp clock 153 * 3. power on acp tiles 154 */ 155 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 156 return 0; 157 } 158 159 static int acp_genpd_add_device(struct device *dev, void *data) 160 { 161 struct generic_pm_domain *gpd = data; 162 int ret; 163 164 ret = pm_genpd_add_device(gpd, dev); 165 if (ret) 166 dev_err(dev, "Failed to add dev to genpd %d\n", ret); 167 168 return ret; 169 } 170 171 static int acp_genpd_remove_device(struct device *dev, void *data) 172 { 173 int ret; 174 175 ret = pm_genpd_remove_device(dev); 176 if (ret) 177 dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 178 179 /* Continue to remove */ 180 return 0; 181 } 182 183 /** 184 * acp_hw_init - start and test ACP block 185 * 186 * @handle: handle used to pass amdgpu_device pointer 187 * 188 */ 189 static int acp_hw_init(void *handle) 190 { 191 int r; 192 u64 acp_base; 193 u32 val = 0; 194 u32 count = 0; 195 struct i2s_platform_data *i2s_pdata = NULL; 196 197 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 198 199 const struct amdgpu_ip_block *ip_block = 200 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 201 202 if (!ip_block) 203 return -EINVAL; 204 205 r = amd_acp_hw_init(adev->acp.cgs_device, 206 ip_block->version->major, ip_block->version->minor); 207 /* -ENODEV means board uses AZ rather than ACP */ 208 if (r == -ENODEV) { 209 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 210 return 0; 211 } else if (r) { 212 return r; 213 } 214 215 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 216 return -EINVAL; 217 218 acp_base = adev->rmmio_base; 219 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); 220 if (!adev->acp.acp_genpd) 221 return -ENOMEM; 222 223 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 224 adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 225 adev->acp.acp_genpd->gpd.power_on = acp_poweron; 226 adev->acp.acp_genpd->adev = adev; 227 228 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 229 230 adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), GFP_KERNEL); 231 232 if (!adev->acp.acp_cell) { 233 r = -ENOMEM; 234 goto failure; 235 } 236 237 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL); 238 if (!adev->acp.acp_res) { 239 r = -ENOMEM; 240 goto failure; 241 } 242 243 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); 244 if (!i2s_pdata) { 245 r = -ENOMEM; 246 goto failure; 247 } 248 249 switch (adev->asic_type) { 250 case CHIP_STONEY: 251 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 252 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 253 break; 254 default: 255 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 256 } 257 i2s_pdata[0].cap = DWC_I2S_PLAY; 258 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 259 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 260 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 261 switch (adev->asic_type) { 262 case CHIP_STONEY: 263 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 264 DW_I2S_QUIRK_COMP_PARAM1 | 265 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 266 break; 267 default: 268 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 269 DW_I2S_QUIRK_COMP_PARAM1; 270 } 271 272 i2s_pdata[1].cap = DWC_I2S_RECORD; 273 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 274 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 275 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 276 277 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 278 switch (adev->asic_type) { 279 case CHIP_STONEY: 280 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 281 break; 282 default: 283 break; 284 } 285 286 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 287 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 288 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 289 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 290 291 adev->acp.acp_res[0].name = "acp2x_dma"; 292 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 293 adev->acp.acp_res[0].start = acp_base; 294 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 295 296 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 297 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 298 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 299 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 300 301 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 302 adev->acp.acp_res[2].flags = IORESOURCE_MEM; 303 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 304 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 305 306 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 307 adev->acp.acp_res[3].flags = IORESOURCE_MEM; 308 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 309 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 310 311 adev->acp.acp_res[4].name = "acp2x_dma_irq"; 312 adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 313 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 314 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 315 316 adev->acp.acp_cell[0].name = "acp_audio_dma"; 317 adev->acp.acp_cell[0].num_resources = 5; 318 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 319 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 320 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 321 322 adev->acp.acp_cell[1].name = "designware-i2s"; 323 adev->acp.acp_cell[1].num_resources = 1; 324 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 325 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 326 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 327 328 adev->acp.acp_cell[2].name = "designware-i2s"; 329 adev->acp.acp_cell[2].num_resources = 1; 330 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 331 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 332 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 333 334 adev->acp.acp_cell[3].name = "designware-i2s"; 335 adev->acp.acp_cell[3].num_resources = 1; 336 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 337 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 338 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 339 340 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS); 341 if (r) 342 goto failure; 343 344 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 345 acp_genpd_add_device); 346 if (r) 347 goto failure; 348 349 /* Assert Soft reset of ACP */ 350 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 351 352 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 353 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 354 355 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 356 while (true) { 357 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 358 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 359 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 360 break; 361 if (--count == 0) { 362 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 363 r = -ETIMEDOUT; 364 goto failure; 365 } 366 udelay(100); 367 } 368 /* Enable clock to ACP and wait until the clock is enabled */ 369 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 370 val = val | ACP_CONTROL__ClkEn_MASK; 371 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 372 373 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 374 375 while (true) { 376 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 377 if (val & (u32) 0x1) 378 break; 379 if (--count == 0) { 380 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 381 r = -ETIMEDOUT; 382 goto failure; 383 } 384 udelay(100); 385 } 386 /* Deassert the SOFT RESET flags */ 387 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 388 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 389 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 390 return 0; 391 392 failure: 393 kfree(i2s_pdata); 394 kfree(adev->acp.acp_res); 395 kfree(adev->acp.acp_cell); 396 kfree(adev->acp.acp_genpd); 397 return r; 398 } 399 400 /** 401 * acp_hw_fini - stop the hardware block 402 * 403 * @handle: handle used to pass amdgpu_device pointer 404 * 405 */ 406 static int acp_hw_fini(void *handle) 407 { 408 u32 val = 0; 409 u32 count = 0; 410 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 411 412 /* return early if no ACP */ 413 if (!adev->acp.acp_genpd) { 414 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 415 return 0; 416 } 417 418 /* Assert Soft reset of ACP */ 419 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 420 421 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 422 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 423 424 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 425 while (true) { 426 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 427 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 428 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 429 break; 430 if (--count == 0) { 431 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 432 return -ETIMEDOUT; 433 } 434 udelay(100); 435 } 436 /* Disable ACP clock */ 437 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 438 val &= ~ACP_CONTROL__ClkEn_MASK; 439 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 440 441 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 442 443 while (true) { 444 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 445 if (val & (u32) 0x1) 446 break; 447 if (--count == 0) { 448 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 449 return -ETIMEDOUT; 450 } 451 udelay(100); 452 } 453 454 device_for_each_child(adev->acp.parent, NULL, 455 acp_genpd_remove_device); 456 457 mfd_remove_devices(adev->acp.parent); 458 kfree(adev->acp.acp_res); 459 kfree(adev->acp.acp_genpd); 460 kfree(adev->acp.acp_cell); 461 462 return 0; 463 } 464 465 static int acp_suspend(void *handle) 466 { 467 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468 469 /* power up on suspend */ 470 if (!adev->acp.acp_cell) 471 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 472 return 0; 473 } 474 475 static int acp_resume(void *handle) 476 { 477 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478 479 /* power down again on resume */ 480 if (!adev->acp.acp_cell) 481 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 482 return 0; 483 } 484 485 static int acp_early_init(void *handle) 486 { 487 return 0; 488 } 489 490 static bool acp_is_idle(void *handle) 491 { 492 return true; 493 } 494 495 static int acp_wait_for_idle(void *handle) 496 { 497 return 0; 498 } 499 500 static int acp_soft_reset(void *handle) 501 { 502 return 0; 503 } 504 505 static int acp_set_clockgating_state(void *handle, 506 enum amd_clockgating_state state) 507 { 508 return 0; 509 } 510 511 static int acp_set_powergating_state(void *handle, 512 enum amd_powergating_state state) 513 { 514 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 515 bool enable = (state == AMD_PG_STATE_GATE); 516 517 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable); 518 519 return 0; 520 } 521 522 static const struct amd_ip_funcs acp_ip_funcs = { 523 .name = "acp_ip", 524 .early_init = acp_early_init, 525 .late_init = NULL, 526 .sw_init = acp_sw_init, 527 .sw_fini = acp_sw_fini, 528 .hw_init = acp_hw_init, 529 .hw_fini = acp_hw_fini, 530 .suspend = acp_suspend, 531 .resume = acp_resume, 532 .is_idle = acp_is_idle, 533 .wait_for_idle = acp_wait_for_idle, 534 .soft_reset = acp_soft_reset, 535 .set_clockgating_state = acp_set_clockgating_state, 536 .set_powergating_state = acp_set_powergating_state, 537 }; 538 539 const struct amdgpu_ip_block_version acp_ip_block = { 540 .type = AMD_IP_BLOCK_TYPE_ACP, 541 .major = 2, 542 .minor = 2, 543 .rev = 0, 544 .funcs = &acp_ip_funcs, 545 }; 546