1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include <linux/irqdomain.h> 27 #include <linux/pci.h> 28 #include <linux/pm_domain.h> 29 #include <linux/platform_device.h> 30 #include <sound/designware_i2s.h> 31 #include <sound/pcm.h> 32 #include <linux/acpi.h> 33 #include <linux/dmi.h> 34 35 #include "amdgpu.h" 36 #include "atom.h" 37 #include "amdgpu_acp.h" 38 39 #include "acp_gfx_if.h" 40 41 #define ST_JADEITE 1 42 #define ACP_TILE_ON_MASK 0x03 43 #define ACP_TILE_OFF_MASK 0x02 44 #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 45 #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 46 47 #define ACP_TILE_P1_MASK 0x3e 48 #define ACP_TILE_P2_MASK 0x3d 49 #define ACP_TILE_DSP0_MASK 0x3b 50 #define ACP_TILE_DSP1_MASK 0x37 51 52 #define ACP_TILE_DSP2_MASK 0x2f 53 54 #define ACP_DMA_REGS_END 0x146c0 55 #define ACP_I2S_PLAY_REGS_START 0x14840 56 #define ACP_I2S_PLAY_REGS_END 0x148b4 57 #define ACP_I2S_CAP_REGS_START 0x148b8 58 #define ACP_I2S_CAP_REGS_END 0x1496c 59 60 #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 61 #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 62 #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 63 #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 64 #define ACP_BT_PLAY_REGS_START 0x14970 65 #define ACP_BT_PLAY_REGS_END 0x14a24 66 #define ACP_BT_COMP1_REG_OFFSET 0xac 67 #define ACP_BT_COMP2_REG_OFFSET 0xa8 68 69 #define mmACP_PGFSM_RETAIN_REG 0x51c9 70 #define mmACP_PGFSM_CONFIG_REG 0x51ca 71 #define mmACP_PGFSM_READ_REG_0 0x51cc 72 73 #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 74 #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 75 #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 76 #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 77 78 #define mmACP_CONTROL 0x5131 79 #define mmACP_STATUS 0x5133 80 #define mmACP_SOFT_RESET 0x5134 81 #define ACP_CONTROL__ClkEn_MASK 0x1 82 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 83 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 84 #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 85 #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 86 87 #define ACP_TIMEOUT_LOOP 0x000000FF 88 #define ACP_DEVS 4 89 #define ACP_SRC_ID 162 90 91 static unsigned long acp_machine_id; 92 93 enum { 94 ACP_TILE_P1 = 0, 95 ACP_TILE_P2, 96 ACP_TILE_DSP0, 97 ACP_TILE_DSP1, 98 ACP_TILE_DSP2, 99 }; 100 101 static int acp_sw_init(void *handle) 102 { 103 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 104 105 adev->acp.parent = adev->dev; 106 107 adev->acp.cgs_device = 108 amdgpu_cgs_create_device(adev); 109 if (!adev->acp.cgs_device) 110 return -EINVAL; 111 112 return 0; 113 } 114 115 static int acp_sw_fini(void *handle) 116 { 117 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 118 119 if (adev->acp.cgs_device) 120 amdgpu_cgs_destroy_device(adev->acp.cgs_device); 121 122 return 0; 123 } 124 125 struct acp_pm_domain { 126 void *adev; 127 struct generic_pm_domain gpd; 128 }; 129 130 static int acp_poweroff(struct generic_pm_domain *genpd) 131 { 132 struct acp_pm_domain *apd; 133 struct amdgpu_device *adev; 134 135 apd = container_of(genpd, struct acp_pm_domain, gpd); 136 adev = apd->adev; 137 /* call smu to POWER GATE ACP block 138 * smu will 139 * 1. turn off the acp clock 140 * 2. power off the acp tiles 141 * 3. check and enter ulv state 142 */ 143 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 144 return 0; 145 } 146 147 static int acp_poweron(struct generic_pm_domain *genpd) 148 { 149 struct acp_pm_domain *apd; 150 struct amdgpu_device *adev; 151 152 apd = container_of(genpd, struct acp_pm_domain, gpd); 153 adev = apd->adev; 154 /* call smu to UNGATE ACP block 155 * smu will 156 * 1. exit ulv 157 * 2. turn on acp clock 158 * 3. power on acp tiles 159 */ 160 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 161 return 0; 162 } 163 164 static int acp_genpd_add_device(struct device *dev, void *data) 165 { 166 struct generic_pm_domain *gpd = data; 167 int ret; 168 169 ret = pm_genpd_add_device(gpd, dev); 170 if (ret) 171 dev_err(dev, "Failed to add dev to genpd %d\n", ret); 172 173 return ret; 174 } 175 176 static int acp_genpd_remove_device(struct device *dev, void *data) 177 { 178 int ret; 179 180 ret = pm_genpd_remove_device(dev); 181 if (ret) 182 dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 183 184 /* Continue to remove */ 185 return 0; 186 } 187 188 static int acp_quirk_cb(const struct dmi_system_id *id) 189 { 190 acp_machine_id = ST_JADEITE; 191 return 1; 192 } 193 194 static const struct dmi_system_id acp_quirk_table[] = { 195 { 196 .callback = acp_quirk_cb, 197 .matches = { 198 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"), 199 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"), 200 } 201 }, 202 { 203 .callback = acp_quirk_cb, 204 .matches = { 205 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."), 206 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"), 207 }, 208 }, 209 { 210 .callback = acp_quirk_cb, 211 .matches = { 212 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"), 213 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"), 214 }, 215 }, 216 {} 217 }; 218 219 /** 220 * acp_hw_init - start and test ACP block 221 * 222 * @handle: handle used to pass amdgpu_device pointer 223 * 224 */ 225 static int acp_hw_init(void *handle) 226 { 227 int r; 228 u64 acp_base; 229 u32 val = 0; 230 u32 count = 0; 231 struct i2s_platform_data *i2s_pdata = NULL; 232 233 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 234 235 const struct amdgpu_ip_block *ip_block = 236 amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 237 238 if (!ip_block) 239 return -EINVAL; 240 241 r = amd_acp_hw_init(adev->acp.cgs_device, 242 ip_block->version->major, ip_block->version->minor); 243 /* -ENODEV means board uses AZ rather than ACP */ 244 if (r == -ENODEV) { 245 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 246 return 0; 247 } else if (r) { 248 return r; 249 } 250 251 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 252 return -EINVAL; 253 254 acp_base = adev->rmmio_base; 255 adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); 256 if (!adev->acp.acp_genpd) 257 return -ENOMEM; 258 259 adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 260 adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 261 adev->acp.acp_genpd->gpd.power_on = acp_poweron; 262 adev->acp.acp_genpd->adev = adev; 263 264 pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 265 266 adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), GFP_KERNEL); 267 268 if (!adev->acp.acp_cell) { 269 r = -ENOMEM; 270 goto failure; 271 } 272 273 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL); 274 if (!adev->acp.acp_res) { 275 r = -ENOMEM; 276 goto failure; 277 } 278 279 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); 280 if (!i2s_pdata) { 281 r = -ENOMEM; 282 goto failure; 283 } 284 285 switch (adev->asic_type) { 286 case CHIP_STONEY: 287 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 288 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 289 break; 290 default: 291 i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 292 } 293 i2s_pdata[0].cap = DWC_I2S_PLAY; 294 i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 295 i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 296 i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 297 switch (adev->asic_type) { 298 case CHIP_STONEY: 299 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 300 DW_I2S_QUIRK_COMP_PARAM1 | 301 DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 302 break; 303 default: 304 i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 305 DW_I2S_QUIRK_COMP_PARAM1; 306 } 307 308 i2s_pdata[1].cap = DWC_I2S_RECORD; 309 i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 310 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 311 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 312 313 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 314 switch (adev->asic_type) { 315 case CHIP_STONEY: 316 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 317 break; 318 default: 319 break; 320 } 321 322 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 323 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 324 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 325 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 326 327 adev->acp.acp_res[0].name = "acp2x_dma"; 328 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 329 adev->acp.acp_res[0].start = acp_base; 330 adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 331 332 adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 333 adev->acp.acp_res[1].flags = IORESOURCE_MEM; 334 adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 335 adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 336 337 adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 338 adev->acp.acp_res[2].flags = IORESOURCE_MEM; 339 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 340 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 341 342 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 343 adev->acp.acp_res[3].flags = IORESOURCE_MEM; 344 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 345 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 346 347 adev->acp.acp_res[4].name = "acp2x_dma_irq"; 348 adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 349 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 350 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 351 352 adev->acp.acp_cell[0].name = "acp_audio_dma"; 353 adev->acp.acp_cell[0].num_resources = 5; 354 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 355 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 356 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 357 358 adev->acp.acp_cell[1].name = "designware-i2s"; 359 adev->acp.acp_cell[1].num_resources = 1; 360 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 361 adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 362 adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 363 364 adev->acp.acp_cell[2].name = "designware-i2s"; 365 adev->acp.acp_cell[2].num_resources = 1; 366 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 367 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 368 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 369 370 adev->acp.acp_cell[3].name = "designware-i2s"; 371 adev->acp.acp_cell[3].num_resources = 1; 372 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 373 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 374 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 375 376 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS); 377 if (r) 378 goto failure; 379 380 r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 381 acp_genpd_add_device); 382 if (r) 383 goto failure; 384 385 /* Assert Soft reset of ACP */ 386 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 387 388 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 389 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 390 391 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 392 while (true) { 393 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 394 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 395 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 396 break; 397 if (--count == 0) { 398 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 399 r = -ETIMEDOUT; 400 goto failure; 401 } 402 udelay(100); 403 } 404 /* Enable clock to ACP and wait until the clock is enabled */ 405 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 406 val = val | ACP_CONTROL__ClkEn_MASK; 407 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 408 409 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 410 411 while (true) { 412 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 413 if (val & (u32) 0x1) 414 break; 415 if (--count == 0) { 416 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 417 r = -ETIMEDOUT; 418 goto failure; 419 } 420 udelay(100); 421 } 422 /* Deassert the SOFT RESET flags */ 423 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 424 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 425 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 426 return 0; 427 428 failure: 429 kfree(i2s_pdata); 430 kfree(adev->acp.acp_res); 431 kfree(adev->acp.acp_cell); 432 kfree(adev->acp.acp_genpd); 433 return r; 434 } 435 436 /** 437 * acp_hw_fini - stop the hardware block 438 * 439 * @handle: handle used to pass amdgpu_device pointer 440 * 441 */ 442 static int acp_hw_fini(void *handle) 443 { 444 u32 val = 0; 445 u32 count = 0; 446 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 447 448 /* return early if no ACP */ 449 if (!adev->acp.acp_genpd) { 450 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 451 return 0; 452 } 453 454 /* Assert Soft reset of ACP */ 455 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 456 457 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 458 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 459 460 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 461 while (true) { 462 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 463 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 464 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 465 break; 466 if (--count == 0) { 467 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 468 return -ETIMEDOUT; 469 } 470 udelay(100); 471 } 472 /* Disable ACP clock */ 473 val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 474 val &= ~ACP_CONTROL__ClkEn_MASK; 475 cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 476 477 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 478 479 while (true) { 480 val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 481 if (val & (u32) 0x1) 482 break; 483 if (--count == 0) { 484 dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 485 return -ETIMEDOUT; 486 } 487 udelay(100); 488 } 489 490 device_for_each_child(adev->acp.parent, NULL, 491 acp_genpd_remove_device); 492 493 mfd_remove_devices(adev->acp.parent); 494 kfree(adev->acp.acp_res); 495 kfree(adev->acp.acp_genpd); 496 kfree(adev->acp.acp_cell); 497 498 return 0; 499 } 500 501 static int acp_suspend(void *handle) 502 { 503 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 504 505 /* power up on suspend */ 506 if (!adev->acp.acp_cell) 507 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 508 return 0; 509 } 510 511 static int acp_resume(void *handle) 512 { 513 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 514 515 /* power down again on resume */ 516 if (!adev->acp.acp_cell) 517 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 518 return 0; 519 } 520 521 static int acp_early_init(void *handle) 522 { 523 return 0; 524 } 525 526 static bool acp_is_idle(void *handle) 527 { 528 return true; 529 } 530 531 static int acp_wait_for_idle(void *handle) 532 { 533 return 0; 534 } 535 536 static int acp_soft_reset(void *handle) 537 { 538 return 0; 539 } 540 541 static int acp_set_clockgating_state(void *handle, 542 enum amd_clockgating_state state) 543 { 544 return 0; 545 } 546 547 static int acp_set_powergating_state(void *handle, 548 enum amd_powergating_state state) 549 { 550 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 551 bool enable = (state == AMD_PG_STATE_GATE); 552 553 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable); 554 555 return 0; 556 } 557 558 static const struct amd_ip_funcs acp_ip_funcs = { 559 .name = "acp_ip", 560 .early_init = acp_early_init, 561 .late_init = NULL, 562 .sw_init = acp_sw_init, 563 .sw_fini = acp_sw_fini, 564 .hw_init = acp_hw_init, 565 .hw_fini = acp_hw_fini, 566 .suspend = acp_suspend, 567 .resume = acp_resume, 568 .is_idle = acp_is_idle, 569 .wait_for_idle = acp_wait_for_idle, 570 .soft_reset = acp_soft_reset, 571 .set_clockgating_state = acp_set_clockgating_state, 572 .set_powergating_state = acp_set_powergating_state, 573 }; 574 575 const struct amdgpu_ip_block_version acp_ip_block = { 576 .type = AMD_IP_BLOCK_TYPE_ACP, 577 .major = 2, 578 .minor = 2, 579 .rev = 0, 580 .funcs = &acp_ip_funcs, 581 }; 582