1a8fe58ceSMaruthi Bayyavarapu /* 2a8fe58ceSMaruthi Bayyavarapu * Copyright 2015 Advanced Micro Devices, Inc. 3a8fe58ceSMaruthi Bayyavarapu * 4a8fe58ceSMaruthi Bayyavarapu * Permission is hereby granted, free of charge, to any person obtaining a 5a8fe58ceSMaruthi Bayyavarapu * copy of this software and associated documentation files (the "Software"), 6a8fe58ceSMaruthi Bayyavarapu * to deal in the Software without restriction, including without limitation 7a8fe58ceSMaruthi Bayyavarapu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a8fe58ceSMaruthi Bayyavarapu * and/or sell copies of the Software, and to permit persons to whom the 9a8fe58ceSMaruthi Bayyavarapu * Software is furnished to do so, subject to the following conditions: 10a8fe58ceSMaruthi Bayyavarapu * 11a8fe58ceSMaruthi Bayyavarapu * The above copyright notice and this permission notice shall be included in 12a8fe58ceSMaruthi Bayyavarapu * all copies or substantial portions of the Software. 13a8fe58ceSMaruthi Bayyavarapu * 14a8fe58ceSMaruthi Bayyavarapu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a8fe58ceSMaruthi Bayyavarapu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a8fe58ceSMaruthi Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a8fe58ceSMaruthi Bayyavarapu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a8fe58ceSMaruthi Bayyavarapu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a8fe58ceSMaruthi Bayyavarapu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a8fe58ceSMaruthi Bayyavarapu * OTHER DEALINGS IN THE SOFTWARE. 21a8fe58ceSMaruthi Bayyavarapu * 22a8fe58ceSMaruthi Bayyavarapu * Authors: AMD 23a8fe58ceSMaruthi Bayyavarapu * 24a8fe58ceSMaruthi Bayyavarapu */ 25a8fe58ceSMaruthi Bayyavarapu 26a8fe58ceSMaruthi Bayyavarapu #include <linux/irqdomain.h> 27841d0023SSam Ravnborg #include <linux/pci.h> 2825030321SMaruthi Srinivas Bayyavarapu #include <linux/pm_domain.h> 29a8fe58ceSMaruthi Bayyavarapu #include <linux/platform_device.h> 30a8fe58ceSMaruthi Bayyavarapu #include <sound/designware_i2s.h> 31a8fe58ceSMaruthi Bayyavarapu #include <sound/pcm.h> 32a8fe58ceSMaruthi Bayyavarapu 33a8fe58ceSMaruthi Bayyavarapu #include "amdgpu.h" 34a8fe58ceSMaruthi Bayyavarapu #include "atom.h" 35a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 36a8fe58ceSMaruthi Bayyavarapu 37a8fe58ceSMaruthi Bayyavarapu #include "acp_gfx_if.h" 38a8fe58ceSMaruthi Bayyavarapu 39a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_MASK 0x03 40a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_MASK 0x02 41a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 42a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 43a8fe58ceSMaruthi Bayyavarapu 44a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P1_MASK 0x3e 45a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P2_MASK 0x3d 46a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP0_MASK 0x3b 47a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP1_MASK 0x37 48a8fe58ceSMaruthi Bayyavarapu 49a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP2_MASK 0x2f 50a8fe58ceSMaruthi Bayyavarapu 51a8fe58ceSMaruthi Bayyavarapu #define ACP_DMA_REGS_END 0x146c0 52a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_START 0x14840 53a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_END 0x148b4 54a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_START 0x148b8 55a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_END 0x1496c 56a8fe58ceSMaruthi Bayyavarapu 57a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 58a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 59a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 60a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 612d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_START 0x14970 622d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_END 0x14a24 632d95ceb4SVijendar Mukunda #define ACP_BT_COMP1_REG_OFFSET 0xac 642d95ceb4SVijendar Mukunda #define ACP_BT_COMP2_REG_OFFSET 0xa8 65a8fe58ceSMaruthi Bayyavarapu 66a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_RETAIN_REG 0x51c9 67a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_CONFIG_REG 0x51ca 68a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_READ_REG_0 0x51cc 69a8fe58ceSMaruthi Bayyavarapu 70a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 71a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 72a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 73a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 74a8fe58ceSMaruthi Bayyavarapu 7537c5f2c9SAkshu Agrawal #define mmACP_CONTROL 0x5131 7637c5f2c9SAkshu Agrawal #define mmACP_STATUS 0x5133 7737c5f2c9SAkshu Agrawal #define mmACP_SOFT_RESET 0x5134 7837c5f2c9SAkshu Agrawal #define ACP_CONTROL__ClkEn_MASK 0x1 7937c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 8037c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 8137c5f2c9SAkshu Agrawal #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 8237c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 8337c5f2c9SAkshu Agrawal 84a8fe58ceSMaruthi Bayyavarapu #define ACP_TIMEOUT_LOOP 0x000000FF 852d95ceb4SVijendar Mukunda #define ACP_DEVS 4 86a8fe58ceSMaruthi Bayyavarapu #define ACP_SRC_ID 162 87a8fe58ceSMaruthi Bayyavarapu 88a8fe58ceSMaruthi Bayyavarapu enum { 89a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P1 = 0, 90a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P2, 91a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP0, 92a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP1, 93a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP2, 94a8fe58ceSMaruthi Bayyavarapu }; 95a8fe58ceSMaruthi Bayyavarapu 96a8fe58ceSMaruthi Bayyavarapu static int acp_sw_init(void *handle) 97a8fe58ceSMaruthi Bayyavarapu { 98a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 99a8fe58ceSMaruthi Bayyavarapu 100a8fe58ceSMaruthi Bayyavarapu adev->acp.parent = adev->dev; 101a8fe58ceSMaruthi Bayyavarapu 102a8fe58ceSMaruthi Bayyavarapu adev->acp.cgs_device = 103a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_create_device(adev); 104a8fe58ceSMaruthi Bayyavarapu if (!adev->acp.cgs_device) 105a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 106a8fe58ceSMaruthi Bayyavarapu 107a8fe58ceSMaruthi Bayyavarapu return 0; 108a8fe58ceSMaruthi Bayyavarapu } 109a8fe58ceSMaruthi Bayyavarapu 110a8fe58ceSMaruthi Bayyavarapu static int acp_sw_fini(void *handle) 111a8fe58ceSMaruthi Bayyavarapu { 112a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 113a8fe58ceSMaruthi Bayyavarapu 114a8fe58ceSMaruthi Bayyavarapu if (adev->acp.cgs_device) 115a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_destroy_device(adev->acp.cgs_device); 116a8fe58ceSMaruthi Bayyavarapu 117a8fe58ceSMaruthi Bayyavarapu return 0; 118a8fe58ceSMaruthi Bayyavarapu } 119a8fe58ceSMaruthi Bayyavarapu 12025030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain { 1213a54d2c8SRex Zhu void *adev; 12225030321SMaruthi Srinivas Bayyavarapu struct generic_pm_domain gpd; 12325030321SMaruthi Srinivas Bayyavarapu }; 12425030321SMaruthi Srinivas Bayyavarapu 12525030321SMaruthi Srinivas Bayyavarapu static int acp_poweroff(struct generic_pm_domain *genpd) 12625030321SMaruthi Srinivas Bayyavarapu { 12725030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1283a54d2c8SRex Zhu struct amdgpu_device *adev; 12925030321SMaruthi Srinivas Bayyavarapu 13025030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 1313a54d2c8SRex Zhu adev = apd->adev; 1323a54d2c8SRex Zhu /* call smu to POWER GATE ACP block 1333a54d2c8SRex Zhu * smu will 1343a54d2c8SRex Zhu * 1. turn off the acp clock 1353a54d2c8SRex Zhu * 2. power off the acp tiles 1363a54d2c8SRex Zhu * 3. check and enter ulv state 13725030321SMaruthi Srinivas Bayyavarapu */ 1383a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 13925030321SMaruthi Srinivas Bayyavarapu return 0; 14025030321SMaruthi Srinivas Bayyavarapu } 14125030321SMaruthi Srinivas Bayyavarapu 14225030321SMaruthi Srinivas Bayyavarapu static int acp_poweron(struct generic_pm_domain *genpd) 14325030321SMaruthi Srinivas Bayyavarapu { 14425030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1453a54d2c8SRex Zhu struct amdgpu_device *adev; 14625030321SMaruthi Srinivas Bayyavarapu 14725030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 1483a54d2c8SRex Zhu adev = apd->adev; 1493a54d2c8SRex Zhu /* call smu to UNGATE ACP block 1503a54d2c8SRex Zhu * smu will 1513a54d2c8SRex Zhu * 1. exit ulv 1523a54d2c8SRex Zhu * 2. turn on acp clock 1533a54d2c8SRex Zhu * 3. power on acp tiles 1543a54d2c8SRex Zhu */ 1553a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 15625030321SMaruthi Srinivas Bayyavarapu return 0; 15725030321SMaruthi Srinivas Bayyavarapu } 15825030321SMaruthi Srinivas Bayyavarapu 159aff89028SKai-Heng Feng static int acp_genpd_add_device(struct device *dev, void *data) 16025030321SMaruthi Srinivas Bayyavarapu { 161aff89028SKai-Heng Feng struct generic_pm_domain *gpd = data; 162aff89028SKai-Heng Feng int ret; 16325030321SMaruthi Srinivas Bayyavarapu 164aff89028SKai-Heng Feng ret = pm_genpd_add_device(gpd, dev); 165aff89028SKai-Heng Feng if (ret) 166aff89028SKai-Heng Feng dev_err(dev, "Failed to add dev to genpd %d\n", ret); 16725030321SMaruthi Srinivas Bayyavarapu 168aff89028SKai-Heng Feng return ret; 169aff89028SKai-Heng Feng } 170aff89028SKai-Heng Feng 171aff89028SKai-Heng Feng static int acp_genpd_remove_device(struct device *dev, void *data) 172aff89028SKai-Heng Feng { 173aff89028SKai-Heng Feng int ret; 174aff89028SKai-Heng Feng 175aff89028SKai-Heng Feng ret = pm_genpd_remove_device(dev); 176aff89028SKai-Heng Feng if (ret) 177aff89028SKai-Heng Feng dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 178aff89028SKai-Heng Feng 179aff89028SKai-Heng Feng /* Continue to remove */ 180aff89028SKai-Heng Feng return 0; 18125030321SMaruthi Srinivas Bayyavarapu } 18225030321SMaruthi Srinivas Bayyavarapu 183a8fe58ceSMaruthi Bayyavarapu /** 184a8fe58ceSMaruthi Bayyavarapu * acp_hw_init - start and test ACP block 185a8fe58ceSMaruthi Bayyavarapu * 186adf0125aSLee Jones * @handle: handle used to pass amdgpu_device pointer 187a8fe58ceSMaruthi Bayyavarapu * 188a8fe58ceSMaruthi Bayyavarapu */ 189a8fe58ceSMaruthi Bayyavarapu static int acp_hw_init(void *handle) 190a8fe58ceSMaruthi Bayyavarapu { 191aff89028SKai-Heng Feng int r; 192*604d3a3fSVijendar Mukunda u64 acp_base; 19337c5f2c9SAkshu Agrawal u32 val = 0; 19437c5f2c9SAkshu Agrawal u32 count = 0; 19557be09c6SNavid Emamdoost struct i2s_platform_data *i2s_pdata = NULL; 196a8fe58ceSMaruthi Bayyavarapu 197a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 198a8fe58ceSMaruthi Bayyavarapu 199a1255107SAlex Deucher const struct amdgpu_ip_block *ip_block = 2002990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 201a8fe58ceSMaruthi Bayyavarapu 202a1255107SAlex Deucher if (!ip_block) 203a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 204a8fe58ceSMaruthi Bayyavarapu 205a8fe58ceSMaruthi Bayyavarapu r = amd_acp_hw_init(adev->acp.cgs_device, 206a1255107SAlex Deucher ip_block->version->major, ip_block->version->minor); 207a8fe58ceSMaruthi Bayyavarapu /* -ENODEV means board uses AZ rather than ACP */ 208be2d6aa5SRex Zhu if (r == -ENODEV) { 209be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 210a8fe58ceSMaruthi Bayyavarapu return 0; 211be2d6aa5SRex Zhu } else if (r) { 212a8fe58ceSMaruthi Bayyavarapu return r; 213be2d6aa5SRex Zhu } 214a8fe58ceSMaruthi Bayyavarapu 215d32d6617SRex Zhu if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 216d32d6617SRex Zhu return -EINVAL; 217d32d6617SRex Zhu 218d32d6617SRex Zhu acp_base = adev->rmmio_base; 21925030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); 220*604d3a3fSVijendar Mukunda if (!adev->acp.acp_genpd) 22125030321SMaruthi Srinivas Bayyavarapu return -ENOMEM; 22225030321SMaruthi Srinivas Bayyavarapu 22325030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 22425030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 22525030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_on = acp_poweron; 2263a54d2c8SRex Zhu adev->acp.acp_genpd->adev = adev; 22725030321SMaruthi Srinivas Bayyavarapu 22825030321SMaruthi Srinivas Bayyavarapu pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 22925030321SMaruthi Srinivas Bayyavarapu 230*604d3a3fSVijendar Mukunda adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), GFP_KERNEL); 231a8fe58ceSMaruthi Bayyavarapu 232*604d3a3fSVijendar Mukunda if (!adev->acp.acp_cell) { 23357be09c6SNavid Emamdoost r = -ENOMEM; 23457be09c6SNavid Emamdoost goto failure; 23557be09c6SNavid Emamdoost } 236a8fe58ceSMaruthi Bayyavarapu 2372d95ceb4SVijendar Mukunda adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL); 238*604d3a3fSVijendar Mukunda if (!adev->acp.acp_res) { 23957be09c6SNavid Emamdoost r = -ENOMEM; 24057be09c6SNavid Emamdoost goto failure; 241a8fe58ceSMaruthi Bayyavarapu } 242a8fe58ceSMaruthi Bayyavarapu 2432d95ceb4SVijendar Mukunda i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); 244*604d3a3fSVijendar Mukunda if (!i2s_pdata) { 24557be09c6SNavid Emamdoost r = -ENOMEM; 24657be09c6SNavid Emamdoost goto failure; 247a8fe58ceSMaruthi Bayyavarapu } 248a8fe58ceSMaruthi Bayyavarapu 24981454cadSVijendar Mukunda switch (adev->asic_type) { 25081454cadSVijendar Mukunda case CHIP_STONEY: 25181454cadSVijendar Mukunda i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 25281454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 25381454cadSVijendar Mukunda break; 25481454cadSVijendar Mukunda default: 255a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 25681454cadSVijendar Mukunda } 257a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].cap = DWC_I2S_PLAY; 258a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 259a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 260a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 26181454cadSVijendar Mukunda switch (adev->asic_type) { 26281454cadSVijendar Mukunda case CHIP_STONEY: 26381454cadSVijendar Mukunda i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 26481454cadSVijendar Mukunda DW_I2S_QUIRK_COMP_PARAM1 | 26581454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 26681454cadSVijendar Mukunda break; 26781454cadSVijendar Mukunda default: 268a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 269a8fe58ceSMaruthi Bayyavarapu DW_I2S_QUIRK_COMP_PARAM1; 27081454cadSVijendar Mukunda } 27181454cadSVijendar Mukunda 272a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].cap = DWC_I2S_RECORD; 273a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 274a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 275a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 276a8fe58ceSMaruthi Bayyavarapu 2772d95ceb4SVijendar Mukunda i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 2782d95ceb4SVijendar Mukunda switch (adev->asic_type) { 2792d95ceb4SVijendar Mukunda case CHIP_STONEY: 2802d95ceb4SVijendar Mukunda i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 2812d95ceb4SVijendar Mukunda break; 2822d95ceb4SVijendar Mukunda default: 2832d95ceb4SVijendar Mukunda break; 2842d95ceb4SVijendar Mukunda } 2852d95ceb4SVijendar Mukunda 2862d95ceb4SVijendar Mukunda i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 2872d95ceb4SVijendar Mukunda i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 2882d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 2892d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 2902d95ceb4SVijendar Mukunda 291a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].name = "acp2x_dma"; 292a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].flags = IORESOURCE_MEM; 293a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].start = acp_base; 294a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 295a8fe58ceSMaruthi Bayyavarapu 296a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 297a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].flags = IORESOURCE_MEM; 298a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 299a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 300a8fe58ceSMaruthi Bayyavarapu 301a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 302a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].flags = IORESOURCE_MEM; 303a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 304a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 305a8fe58ceSMaruthi Bayyavarapu 3062d95ceb4SVijendar Mukunda adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 3072d95ceb4SVijendar Mukunda adev->acp.acp_res[3].flags = IORESOURCE_MEM; 3082d95ceb4SVijendar Mukunda adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 3092d95ceb4SVijendar Mukunda adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 3102d95ceb4SVijendar Mukunda 3112d95ceb4SVijendar Mukunda adev->acp.acp_res[4].name = "acp2x_dma_irq"; 3122d95ceb4SVijendar Mukunda adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 3132d95ceb4SVijendar Mukunda adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 3142d95ceb4SVijendar Mukunda adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 315a8fe58ceSMaruthi Bayyavarapu 316a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].name = "acp_audio_dma"; 3172d95ceb4SVijendar Mukunda adev->acp.acp_cell[0].num_resources = 5; 318a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 3191fd16f36SVijendar Mukunda adev->acp.acp_cell[0].platform_data = &adev->asic_type; 3201fd16f36SVijendar Mukunda adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 321a8fe58ceSMaruthi Bayyavarapu 322a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].name = "designware-i2s"; 323a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].num_resources = 1; 324a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 325a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 326a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 327a8fe58ceSMaruthi Bayyavarapu 328a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].name = "designware-i2s"; 329a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].num_resources = 1; 330a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 331a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 332a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 333a8fe58ceSMaruthi Bayyavarapu 3342d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].name = "designware-i2s"; 3352d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].num_resources = 1; 3362d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 3372d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 3382d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 3392d95ceb4SVijendar Mukunda 340*604d3a3fSVijendar Mukunda r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS); 341a8fe58ceSMaruthi Bayyavarapu if (r) 34257be09c6SNavid Emamdoost goto failure; 343a8fe58ceSMaruthi Bayyavarapu 344aff89028SKai-Heng Feng r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 345aff89028SKai-Heng Feng acp_genpd_add_device); 346aff89028SKai-Heng Feng if (r) 34757be09c6SNavid Emamdoost goto failure; 34825030321SMaruthi Srinivas Bayyavarapu 34937c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 35037c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 35137c5f2c9SAkshu Agrawal 35237c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 35337c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 35437c5f2c9SAkshu Agrawal 35537c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 35637c5f2c9SAkshu Agrawal while (true) { 35737c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 35837c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 35937c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 36037c5f2c9SAkshu Agrawal break; 36137c5f2c9SAkshu Agrawal if (--count == 0) { 36237c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 36357be09c6SNavid Emamdoost r = -ETIMEDOUT; 36457be09c6SNavid Emamdoost goto failure; 36537c5f2c9SAkshu Agrawal } 36637c5f2c9SAkshu Agrawal udelay(100); 36737c5f2c9SAkshu Agrawal } 36837c5f2c9SAkshu Agrawal /* Enable clock to ACP and wait until the clock is enabled */ 36937c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 37037c5f2c9SAkshu Agrawal val = val | ACP_CONTROL__ClkEn_MASK; 37137c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 37237c5f2c9SAkshu Agrawal 37337c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 37437c5f2c9SAkshu Agrawal 37537c5f2c9SAkshu Agrawal while (true) { 37637c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 37737c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 37837c5f2c9SAkshu Agrawal break; 37937c5f2c9SAkshu Agrawal if (--count == 0) { 38037c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 38157be09c6SNavid Emamdoost r = -ETIMEDOUT; 38257be09c6SNavid Emamdoost goto failure; 38337c5f2c9SAkshu Agrawal } 38437c5f2c9SAkshu Agrawal udelay(100); 38537c5f2c9SAkshu Agrawal } 38637c5f2c9SAkshu Agrawal /* Deassert the SOFT RESET flags */ 38737c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 38837c5f2c9SAkshu Agrawal val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 38937c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 390a8fe58ceSMaruthi Bayyavarapu return 0; 39157be09c6SNavid Emamdoost 39257be09c6SNavid Emamdoost failure: 39357be09c6SNavid Emamdoost kfree(i2s_pdata); 39457be09c6SNavid Emamdoost kfree(adev->acp.acp_res); 39557be09c6SNavid Emamdoost kfree(adev->acp.acp_cell); 39657be09c6SNavid Emamdoost kfree(adev->acp.acp_genpd); 39757be09c6SNavid Emamdoost return r; 398a8fe58ceSMaruthi Bayyavarapu } 399a8fe58ceSMaruthi Bayyavarapu 400a8fe58ceSMaruthi Bayyavarapu /** 401a8fe58ceSMaruthi Bayyavarapu * acp_hw_fini - stop the hardware block 402a8fe58ceSMaruthi Bayyavarapu * 403adf0125aSLee Jones * @handle: handle used to pass amdgpu_device pointer 404a8fe58ceSMaruthi Bayyavarapu * 405a8fe58ceSMaruthi Bayyavarapu */ 406a8fe58ceSMaruthi Bayyavarapu static int acp_hw_fini(void *handle) 407a8fe58ceSMaruthi Bayyavarapu { 40837c5f2c9SAkshu Agrawal u32 val = 0; 40937c5f2c9SAkshu Agrawal u32 count = 0; 410a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 411a8fe58ceSMaruthi Bayyavarapu 412757124d9SAlex Deucher /* return early if no ACP */ 4131062ddb6SVijendar Mukunda if (!adev->acp.acp_genpd) { 414be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 415757124d9SAlex Deucher return 0; 416be2d6aa5SRex Zhu } 417757124d9SAlex Deucher 41837c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 41937c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 42037c5f2c9SAkshu Agrawal 42137c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 42237c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 42337c5f2c9SAkshu Agrawal 42437c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 42537c5f2c9SAkshu Agrawal while (true) { 42637c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 42737c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 42837c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 42937c5f2c9SAkshu Agrawal break; 43037c5f2c9SAkshu Agrawal if (--count == 0) { 43137c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 43237c5f2c9SAkshu Agrawal return -ETIMEDOUT; 43337c5f2c9SAkshu Agrawal } 43437c5f2c9SAkshu Agrawal udelay(100); 43537c5f2c9SAkshu Agrawal } 43637c5f2c9SAkshu Agrawal /* Disable ACP clock */ 43737c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 43837c5f2c9SAkshu Agrawal val &= ~ACP_CONTROL__ClkEn_MASK; 43937c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 44037c5f2c9SAkshu Agrawal 44137c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 44237c5f2c9SAkshu Agrawal 44337c5f2c9SAkshu Agrawal while (true) { 44437c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 44537c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 44637c5f2c9SAkshu Agrawal break; 44737c5f2c9SAkshu Agrawal if (--count == 0) { 44837c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 44937c5f2c9SAkshu Agrawal return -ETIMEDOUT; 45037c5f2c9SAkshu Agrawal } 45137c5f2c9SAkshu Agrawal udelay(100); 45237c5f2c9SAkshu Agrawal } 45337c5f2c9SAkshu Agrawal 454aff89028SKai-Heng Feng device_for_each_child(adev->acp.parent, NULL, 455aff89028SKai-Heng Feng acp_genpd_remove_device); 45625030321SMaruthi Srinivas Bayyavarapu 457a8fe58ceSMaruthi Bayyavarapu mfd_remove_devices(adev->acp.parent); 458a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_res); 4591062ddb6SVijendar Mukunda kfree(adev->acp.acp_genpd); 460a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_cell); 461a8fe58ceSMaruthi Bayyavarapu 462a8fe58ceSMaruthi Bayyavarapu return 0; 463a8fe58ceSMaruthi Bayyavarapu } 464a8fe58ceSMaruthi Bayyavarapu 465a8fe58ceSMaruthi Bayyavarapu static int acp_suspend(void *handle) 466a8fe58ceSMaruthi Bayyavarapu { 467be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 468be2d6aa5SRex Zhu 469be2d6aa5SRex Zhu /* power up on suspend */ 470be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 471be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 472a8fe58ceSMaruthi Bayyavarapu return 0; 473a8fe58ceSMaruthi Bayyavarapu } 474a8fe58ceSMaruthi Bayyavarapu 475a8fe58ceSMaruthi Bayyavarapu static int acp_resume(void *handle) 476a8fe58ceSMaruthi Bayyavarapu { 477be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 478be2d6aa5SRex Zhu 479be2d6aa5SRex Zhu /* power down again on resume */ 480be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 481be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 482a8fe58ceSMaruthi Bayyavarapu return 0; 483a8fe58ceSMaruthi Bayyavarapu } 484a8fe58ceSMaruthi Bayyavarapu 485a8fe58ceSMaruthi Bayyavarapu static int acp_early_init(void *handle) 486a8fe58ceSMaruthi Bayyavarapu { 487a8fe58ceSMaruthi Bayyavarapu return 0; 488a8fe58ceSMaruthi Bayyavarapu } 489a8fe58ceSMaruthi Bayyavarapu 490a8fe58ceSMaruthi Bayyavarapu static bool acp_is_idle(void *handle) 491a8fe58ceSMaruthi Bayyavarapu { 492a8fe58ceSMaruthi Bayyavarapu return true; 493a8fe58ceSMaruthi Bayyavarapu } 494a8fe58ceSMaruthi Bayyavarapu 495a8fe58ceSMaruthi Bayyavarapu static int acp_wait_for_idle(void *handle) 496a8fe58ceSMaruthi Bayyavarapu { 497a8fe58ceSMaruthi Bayyavarapu return 0; 498a8fe58ceSMaruthi Bayyavarapu } 499a8fe58ceSMaruthi Bayyavarapu 500a8fe58ceSMaruthi Bayyavarapu static int acp_soft_reset(void *handle) 501a8fe58ceSMaruthi Bayyavarapu { 502a8fe58ceSMaruthi Bayyavarapu return 0; 503a8fe58ceSMaruthi Bayyavarapu } 504a8fe58ceSMaruthi Bayyavarapu 505a8fe58ceSMaruthi Bayyavarapu static int acp_set_clockgating_state(void *handle, 506a8fe58ceSMaruthi Bayyavarapu enum amd_clockgating_state state) 507a8fe58ceSMaruthi Bayyavarapu { 508a8fe58ceSMaruthi Bayyavarapu return 0; 509a8fe58ceSMaruthi Bayyavarapu } 510a8fe58ceSMaruthi Bayyavarapu 511a8fe58ceSMaruthi Bayyavarapu static int acp_set_powergating_state(void *handle, 512a8fe58ceSMaruthi Bayyavarapu enum amd_powergating_state state) 513a8fe58ceSMaruthi Bayyavarapu { 514c36628d8SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 515a9d4fe2fSNirmoy Das bool enable = (state == AMD_PG_STATE_GATE); 516c36628d8SRex Zhu 517c36628d8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable); 518c36628d8SRex Zhu 519a8fe58ceSMaruthi Bayyavarapu return 0; 520a8fe58ceSMaruthi Bayyavarapu } 521a8fe58ceSMaruthi Bayyavarapu 522a1255107SAlex Deucher static const struct amd_ip_funcs acp_ip_funcs = { 52388a907d6STom St Denis .name = "acp_ip", 524a8fe58ceSMaruthi Bayyavarapu .early_init = acp_early_init, 525a8fe58ceSMaruthi Bayyavarapu .late_init = NULL, 526a8fe58ceSMaruthi Bayyavarapu .sw_init = acp_sw_init, 527a8fe58ceSMaruthi Bayyavarapu .sw_fini = acp_sw_fini, 528a8fe58ceSMaruthi Bayyavarapu .hw_init = acp_hw_init, 529a8fe58ceSMaruthi Bayyavarapu .hw_fini = acp_hw_fini, 530a8fe58ceSMaruthi Bayyavarapu .suspend = acp_suspend, 531a8fe58ceSMaruthi Bayyavarapu .resume = acp_resume, 532a8fe58ceSMaruthi Bayyavarapu .is_idle = acp_is_idle, 533a8fe58ceSMaruthi Bayyavarapu .wait_for_idle = acp_wait_for_idle, 534a8fe58ceSMaruthi Bayyavarapu .soft_reset = acp_soft_reset, 535a8fe58ceSMaruthi Bayyavarapu .set_clockgating_state = acp_set_clockgating_state, 536a8fe58ceSMaruthi Bayyavarapu .set_powergating_state = acp_set_powergating_state, 537a8fe58ceSMaruthi Bayyavarapu }; 538a1255107SAlex Deucher 539*604d3a3fSVijendar Mukunda const struct amdgpu_ip_block_version acp_ip_block = { 540a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_ACP, 541a1255107SAlex Deucher .major = 2, 542a1255107SAlex Deucher .minor = 2, 543a1255107SAlex Deucher .rev = 0, 544a1255107SAlex Deucher .funcs = &acp_ip_funcs, 545a1255107SAlex Deucher }; 546