1a8fe58ceSMaruthi Bayyavarapu /* 2a8fe58ceSMaruthi Bayyavarapu * Copyright 2015 Advanced Micro Devices, Inc. 3a8fe58ceSMaruthi Bayyavarapu * 4a8fe58ceSMaruthi Bayyavarapu * Permission is hereby granted, free of charge, to any person obtaining a 5a8fe58ceSMaruthi Bayyavarapu * copy of this software and associated documentation files (the "Software"), 6a8fe58ceSMaruthi Bayyavarapu * to deal in the Software without restriction, including without limitation 7a8fe58ceSMaruthi Bayyavarapu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a8fe58ceSMaruthi Bayyavarapu * and/or sell copies of the Software, and to permit persons to whom the 9a8fe58ceSMaruthi Bayyavarapu * Software is furnished to do so, subject to the following conditions: 10a8fe58ceSMaruthi Bayyavarapu * 11a8fe58ceSMaruthi Bayyavarapu * The above copyright notice and this permission notice shall be included in 12a8fe58ceSMaruthi Bayyavarapu * all copies or substantial portions of the Software. 13a8fe58ceSMaruthi Bayyavarapu * 14a8fe58ceSMaruthi Bayyavarapu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a8fe58ceSMaruthi Bayyavarapu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a8fe58ceSMaruthi Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a8fe58ceSMaruthi Bayyavarapu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a8fe58ceSMaruthi Bayyavarapu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a8fe58ceSMaruthi Bayyavarapu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a8fe58ceSMaruthi Bayyavarapu * OTHER DEALINGS IN THE SOFTWARE. 21a8fe58ceSMaruthi Bayyavarapu * 22a8fe58ceSMaruthi Bayyavarapu * Authors: AMD 23a8fe58ceSMaruthi Bayyavarapu * 24a8fe58ceSMaruthi Bayyavarapu */ 25a8fe58ceSMaruthi Bayyavarapu 26a8fe58ceSMaruthi Bayyavarapu #include <linux/irqdomain.h> 27841d0023SSam Ravnborg #include <linux/pci.h> 2825030321SMaruthi Srinivas Bayyavarapu #include <linux/pm_domain.h> 29a8fe58ceSMaruthi Bayyavarapu #include <linux/platform_device.h> 30a8fe58ceSMaruthi Bayyavarapu #include <sound/designware_i2s.h> 31a8fe58ceSMaruthi Bayyavarapu #include <sound/pcm.h> 32*49062ee3SVijendar Mukunda #include <linux/acpi.h> 33*49062ee3SVijendar Mukunda #include <linux/dmi.h> 34a8fe58ceSMaruthi Bayyavarapu 35a8fe58ceSMaruthi Bayyavarapu #include "amdgpu.h" 36a8fe58ceSMaruthi Bayyavarapu #include "atom.h" 37a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 38a8fe58ceSMaruthi Bayyavarapu 39a8fe58ceSMaruthi Bayyavarapu #include "acp_gfx_if.h" 40a8fe58ceSMaruthi Bayyavarapu 41*49062ee3SVijendar Mukunda #define ST_JADEITE 1 42a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_MASK 0x03 43a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_MASK 0x02 44a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 45a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 46a8fe58ceSMaruthi Bayyavarapu 47a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P1_MASK 0x3e 48a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P2_MASK 0x3d 49a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP0_MASK 0x3b 50a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP1_MASK 0x37 51a8fe58ceSMaruthi Bayyavarapu 52a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP2_MASK 0x2f 53a8fe58ceSMaruthi Bayyavarapu 54a8fe58ceSMaruthi Bayyavarapu #define ACP_DMA_REGS_END 0x146c0 55a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_START 0x14840 56a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_END 0x148b4 57a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_START 0x148b8 58a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_END 0x1496c 59a8fe58ceSMaruthi Bayyavarapu 60a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 61a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 62a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 63a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 642d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_START 0x14970 652d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_END 0x14a24 662d95ceb4SVijendar Mukunda #define ACP_BT_COMP1_REG_OFFSET 0xac 672d95ceb4SVijendar Mukunda #define ACP_BT_COMP2_REG_OFFSET 0xa8 68a8fe58ceSMaruthi Bayyavarapu 69a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_RETAIN_REG 0x51c9 70a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_CONFIG_REG 0x51ca 71a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_READ_REG_0 0x51cc 72a8fe58ceSMaruthi Bayyavarapu 73a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 74a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 75a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 76a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 77a8fe58ceSMaruthi Bayyavarapu 7837c5f2c9SAkshu Agrawal #define mmACP_CONTROL 0x5131 7937c5f2c9SAkshu Agrawal #define mmACP_STATUS 0x5133 8037c5f2c9SAkshu Agrawal #define mmACP_SOFT_RESET 0x5134 8137c5f2c9SAkshu Agrawal #define ACP_CONTROL__ClkEn_MASK 0x1 8237c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 8337c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 8437c5f2c9SAkshu Agrawal #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 8537c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 8637c5f2c9SAkshu Agrawal 87a8fe58ceSMaruthi Bayyavarapu #define ACP_TIMEOUT_LOOP 0x000000FF 882d95ceb4SVijendar Mukunda #define ACP_DEVS 4 89a8fe58ceSMaruthi Bayyavarapu #define ACP_SRC_ID 162 90a8fe58ceSMaruthi Bayyavarapu 91*49062ee3SVijendar Mukunda static unsigned long acp_machine_id; 92*49062ee3SVijendar Mukunda 93a8fe58ceSMaruthi Bayyavarapu enum { 94a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P1 = 0, 95a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P2, 96a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP0, 97a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP1, 98a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP2, 99a8fe58ceSMaruthi Bayyavarapu }; 100a8fe58ceSMaruthi Bayyavarapu 101a8fe58ceSMaruthi Bayyavarapu static int acp_sw_init(void *handle) 102a8fe58ceSMaruthi Bayyavarapu { 103a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 104a8fe58ceSMaruthi Bayyavarapu 105a8fe58ceSMaruthi Bayyavarapu adev->acp.parent = adev->dev; 106a8fe58ceSMaruthi Bayyavarapu 107a8fe58ceSMaruthi Bayyavarapu adev->acp.cgs_device = 108a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_create_device(adev); 109a8fe58ceSMaruthi Bayyavarapu if (!adev->acp.cgs_device) 110a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 111a8fe58ceSMaruthi Bayyavarapu 112a8fe58ceSMaruthi Bayyavarapu return 0; 113a8fe58ceSMaruthi Bayyavarapu } 114a8fe58ceSMaruthi Bayyavarapu 115a8fe58ceSMaruthi Bayyavarapu static int acp_sw_fini(void *handle) 116a8fe58ceSMaruthi Bayyavarapu { 117a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 118a8fe58ceSMaruthi Bayyavarapu 119a8fe58ceSMaruthi Bayyavarapu if (adev->acp.cgs_device) 120a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_destroy_device(adev->acp.cgs_device); 121a8fe58ceSMaruthi Bayyavarapu 122a8fe58ceSMaruthi Bayyavarapu return 0; 123a8fe58ceSMaruthi Bayyavarapu } 124a8fe58ceSMaruthi Bayyavarapu 12525030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain { 1263a54d2c8SRex Zhu void *adev; 12725030321SMaruthi Srinivas Bayyavarapu struct generic_pm_domain gpd; 12825030321SMaruthi Srinivas Bayyavarapu }; 12925030321SMaruthi Srinivas Bayyavarapu 13025030321SMaruthi Srinivas Bayyavarapu static int acp_poweroff(struct generic_pm_domain *genpd) 13125030321SMaruthi Srinivas Bayyavarapu { 13225030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1333a54d2c8SRex Zhu struct amdgpu_device *adev; 13425030321SMaruthi Srinivas Bayyavarapu 13525030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 1363a54d2c8SRex Zhu adev = apd->adev; 1373a54d2c8SRex Zhu /* call smu to POWER GATE ACP block 1383a54d2c8SRex Zhu * smu will 1393a54d2c8SRex Zhu * 1. turn off the acp clock 1403a54d2c8SRex Zhu * 2. power off the acp tiles 1413a54d2c8SRex Zhu * 3. check and enter ulv state 14225030321SMaruthi Srinivas Bayyavarapu */ 1433a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 14425030321SMaruthi Srinivas Bayyavarapu return 0; 14525030321SMaruthi Srinivas Bayyavarapu } 14625030321SMaruthi Srinivas Bayyavarapu 14725030321SMaruthi Srinivas Bayyavarapu static int acp_poweron(struct generic_pm_domain *genpd) 14825030321SMaruthi Srinivas Bayyavarapu { 14925030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1503a54d2c8SRex Zhu struct amdgpu_device *adev; 15125030321SMaruthi Srinivas Bayyavarapu 15225030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 1533a54d2c8SRex Zhu adev = apd->adev; 1543a54d2c8SRex Zhu /* call smu to UNGATE ACP block 1553a54d2c8SRex Zhu * smu will 1563a54d2c8SRex Zhu * 1. exit ulv 1573a54d2c8SRex Zhu * 2. turn on acp clock 1583a54d2c8SRex Zhu * 3. power on acp tiles 1593a54d2c8SRex Zhu */ 1603a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 16125030321SMaruthi Srinivas Bayyavarapu return 0; 16225030321SMaruthi Srinivas Bayyavarapu } 16325030321SMaruthi Srinivas Bayyavarapu 164aff89028SKai-Heng Feng static int acp_genpd_add_device(struct device *dev, void *data) 16525030321SMaruthi Srinivas Bayyavarapu { 166aff89028SKai-Heng Feng struct generic_pm_domain *gpd = data; 167aff89028SKai-Heng Feng int ret; 16825030321SMaruthi Srinivas Bayyavarapu 169aff89028SKai-Heng Feng ret = pm_genpd_add_device(gpd, dev); 170aff89028SKai-Heng Feng if (ret) 171aff89028SKai-Heng Feng dev_err(dev, "Failed to add dev to genpd %d\n", ret); 17225030321SMaruthi Srinivas Bayyavarapu 173aff89028SKai-Heng Feng return ret; 174aff89028SKai-Heng Feng } 175aff89028SKai-Heng Feng 176aff89028SKai-Heng Feng static int acp_genpd_remove_device(struct device *dev, void *data) 177aff89028SKai-Heng Feng { 178aff89028SKai-Heng Feng int ret; 179aff89028SKai-Heng Feng 180aff89028SKai-Heng Feng ret = pm_genpd_remove_device(dev); 181aff89028SKai-Heng Feng if (ret) 182aff89028SKai-Heng Feng dev_err(dev, "Failed to remove dev from genpd %d\n", ret); 183aff89028SKai-Heng Feng 184aff89028SKai-Heng Feng /* Continue to remove */ 185aff89028SKai-Heng Feng return 0; 18625030321SMaruthi Srinivas Bayyavarapu } 18725030321SMaruthi Srinivas Bayyavarapu 188*49062ee3SVijendar Mukunda static int acp_quirk_cb(const struct dmi_system_id *id) 189*49062ee3SVijendar Mukunda { 190*49062ee3SVijendar Mukunda acp_machine_id = ST_JADEITE; 191*49062ee3SVijendar Mukunda return 1; 192*49062ee3SVijendar Mukunda } 193*49062ee3SVijendar Mukunda 194*49062ee3SVijendar Mukunda static const struct dmi_system_id acp_quirk_table[] = { 195*49062ee3SVijendar Mukunda { 196*49062ee3SVijendar Mukunda .callback = acp_quirk_cb, 197*49062ee3SVijendar Mukunda .matches = { 198*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMD"), 199*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "Jadeite"), 200*49062ee3SVijendar Mukunda } 201*49062ee3SVijendar Mukunda }, 202*49062ee3SVijendar Mukunda { 203*49062ee3SVijendar Mukunda .callback = acp_quirk_cb, 204*49062ee3SVijendar Mukunda .matches = { 205*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "IP3 Technology CO.,Ltd."), 206*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN1D"), 207*49062ee3SVijendar Mukunda }, 208*49062ee3SVijendar Mukunda }, 209*49062ee3SVijendar Mukunda { 210*49062ee3SVijendar Mukunda .callback = acp_quirk_cb, 211*49062ee3SVijendar Mukunda .matches = { 212*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Standard"), 213*49062ee3SVijendar Mukunda DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ASN10"), 214*49062ee3SVijendar Mukunda }, 215*49062ee3SVijendar Mukunda }, 216*49062ee3SVijendar Mukunda {} 217*49062ee3SVijendar Mukunda }; 218*49062ee3SVijendar Mukunda 219a8fe58ceSMaruthi Bayyavarapu /** 220a8fe58ceSMaruthi Bayyavarapu * acp_hw_init - start and test ACP block 221a8fe58ceSMaruthi Bayyavarapu * 222adf0125aSLee Jones * @handle: handle used to pass amdgpu_device pointer 223a8fe58ceSMaruthi Bayyavarapu * 224a8fe58ceSMaruthi Bayyavarapu */ 225a8fe58ceSMaruthi Bayyavarapu static int acp_hw_init(void *handle) 226a8fe58ceSMaruthi Bayyavarapu { 227aff89028SKai-Heng Feng int r; 228604d3a3fSVijendar Mukunda u64 acp_base; 22937c5f2c9SAkshu Agrawal u32 val = 0; 23037c5f2c9SAkshu Agrawal u32 count = 0; 23157be09c6SNavid Emamdoost struct i2s_platform_data *i2s_pdata = NULL; 232a8fe58ceSMaruthi Bayyavarapu 233a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 234a8fe58ceSMaruthi Bayyavarapu 235a1255107SAlex Deucher const struct amdgpu_ip_block *ip_block = 2362990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 237a8fe58ceSMaruthi Bayyavarapu 238a1255107SAlex Deucher if (!ip_block) 239a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 240a8fe58ceSMaruthi Bayyavarapu 241a8fe58ceSMaruthi Bayyavarapu r = amd_acp_hw_init(adev->acp.cgs_device, 242a1255107SAlex Deucher ip_block->version->major, ip_block->version->minor); 243a8fe58ceSMaruthi Bayyavarapu /* -ENODEV means board uses AZ rather than ACP */ 244be2d6aa5SRex Zhu if (r == -ENODEV) { 245be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 246a8fe58ceSMaruthi Bayyavarapu return 0; 247be2d6aa5SRex Zhu } else if (r) { 248a8fe58ceSMaruthi Bayyavarapu return r; 249be2d6aa5SRex Zhu } 250a8fe58ceSMaruthi Bayyavarapu 251d32d6617SRex Zhu if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 252d32d6617SRex Zhu return -EINVAL; 253d32d6617SRex Zhu 254d32d6617SRex Zhu acp_base = adev->rmmio_base; 25525030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); 256604d3a3fSVijendar Mukunda if (!adev->acp.acp_genpd) 25725030321SMaruthi Srinivas Bayyavarapu return -ENOMEM; 25825030321SMaruthi Srinivas Bayyavarapu 25925030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 26025030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 26125030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_on = acp_poweron; 2623a54d2c8SRex Zhu adev->acp.acp_genpd->adev = adev; 26325030321SMaruthi Srinivas Bayyavarapu 26425030321SMaruthi Srinivas Bayyavarapu pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 26525030321SMaruthi Srinivas Bayyavarapu 266604d3a3fSVijendar Mukunda adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), GFP_KERNEL); 267a8fe58ceSMaruthi Bayyavarapu 268604d3a3fSVijendar Mukunda if (!adev->acp.acp_cell) { 26957be09c6SNavid Emamdoost r = -ENOMEM; 27057be09c6SNavid Emamdoost goto failure; 27157be09c6SNavid Emamdoost } 272a8fe58ceSMaruthi Bayyavarapu 2732d95ceb4SVijendar Mukunda adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL); 274604d3a3fSVijendar Mukunda if (!adev->acp.acp_res) { 27557be09c6SNavid Emamdoost r = -ENOMEM; 27657be09c6SNavid Emamdoost goto failure; 277a8fe58ceSMaruthi Bayyavarapu } 278a8fe58ceSMaruthi Bayyavarapu 2792d95ceb4SVijendar Mukunda i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); 280604d3a3fSVijendar Mukunda if (!i2s_pdata) { 28157be09c6SNavid Emamdoost r = -ENOMEM; 28257be09c6SNavid Emamdoost goto failure; 283a8fe58ceSMaruthi Bayyavarapu } 284a8fe58ceSMaruthi Bayyavarapu 28581454cadSVijendar Mukunda switch (adev->asic_type) { 28681454cadSVijendar Mukunda case CHIP_STONEY: 28781454cadSVijendar Mukunda i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 28881454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 28981454cadSVijendar Mukunda break; 29081454cadSVijendar Mukunda default: 291a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 29281454cadSVijendar Mukunda } 293a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].cap = DWC_I2S_PLAY; 294a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 295a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 296a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 29781454cadSVijendar Mukunda switch (adev->asic_type) { 29881454cadSVijendar Mukunda case CHIP_STONEY: 29981454cadSVijendar Mukunda i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 30081454cadSVijendar Mukunda DW_I2S_QUIRK_COMP_PARAM1 | 30181454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 30281454cadSVijendar Mukunda break; 30381454cadSVijendar Mukunda default: 304a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 305a8fe58ceSMaruthi Bayyavarapu DW_I2S_QUIRK_COMP_PARAM1; 30681454cadSVijendar Mukunda } 30781454cadSVijendar Mukunda 308a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].cap = DWC_I2S_RECORD; 309a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 310a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 311a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 312a8fe58ceSMaruthi Bayyavarapu 3132d95ceb4SVijendar Mukunda i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 3142d95ceb4SVijendar Mukunda switch (adev->asic_type) { 3152d95ceb4SVijendar Mukunda case CHIP_STONEY: 3162d95ceb4SVijendar Mukunda i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 3172d95ceb4SVijendar Mukunda break; 3182d95ceb4SVijendar Mukunda default: 3192d95ceb4SVijendar Mukunda break; 3202d95ceb4SVijendar Mukunda } 3212d95ceb4SVijendar Mukunda 3222d95ceb4SVijendar Mukunda i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 3232d95ceb4SVijendar Mukunda i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 3242d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 3252d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 3262d95ceb4SVijendar Mukunda 327a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].name = "acp2x_dma"; 328a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].flags = IORESOURCE_MEM; 329a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].start = acp_base; 330a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 331a8fe58ceSMaruthi Bayyavarapu 332a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 333a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].flags = IORESOURCE_MEM; 334a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 335a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 336a8fe58ceSMaruthi Bayyavarapu 337a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 338a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].flags = IORESOURCE_MEM; 339a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 340a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 341a8fe58ceSMaruthi Bayyavarapu 3422d95ceb4SVijendar Mukunda adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 3432d95ceb4SVijendar Mukunda adev->acp.acp_res[3].flags = IORESOURCE_MEM; 3442d95ceb4SVijendar Mukunda adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 3452d95ceb4SVijendar Mukunda adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 3462d95ceb4SVijendar Mukunda 3472d95ceb4SVijendar Mukunda adev->acp.acp_res[4].name = "acp2x_dma_irq"; 3482d95ceb4SVijendar Mukunda adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 3492d95ceb4SVijendar Mukunda adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 3502d95ceb4SVijendar Mukunda adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 351a8fe58ceSMaruthi Bayyavarapu 352a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].name = "acp_audio_dma"; 3532d95ceb4SVijendar Mukunda adev->acp.acp_cell[0].num_resources = 5; 354a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 3551fd16f36SVijendar Mukunda adev->acp.acp_cell[0].platform_data = &adev->asic_type; 3561fd16f36SVijendar Mukunda adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 357a8fe58ceSMaruthi Bayyavarapu 358a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].name = "designware-i2s"; 359a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].num_resources = 1; 360a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 361a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 362a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 363a8fe58ceSMaruthi Bayyavarapu 364a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].name = "designware-i2s"; 365a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].num_resources = 1; 366a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 367a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 368a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 369a8fe58ceSMaruthi Bayyavarapu 3702d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].name = "designware-i2s"; 3712d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].num_resources = 1; 3722d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 3732d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 3742d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 3752d95ceb4SVijendar Mukunda 376604d3a3fSVijendar Mukunda r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, ACP_DEVS); 377a8fe58ceSMaruthi Bayyavarapu if (r) 37857be09c6SNavid Emamdoost goto failure; 379a8fe58ceSMaruthi Bayyavarapu 380aff89028SKai-Heng Feng r = device_for_each_child(adev->acp.parent, &adev->acp.acp_genpd->gpd, 381aff89028SKai-Heng Feng acp_genpd_add_device); 382aff89028SKai-Heng Feng if (r) 38357be09c6SNavid Emamdoost goto failure; 38425030321SMaruthi Srinivas Bayyavarapu 38537c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 38637c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 38737c5f2c9SAkshu Agrawal 38837c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 38937c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 39037c5f2c9SAkshu Agrawal 39137c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 39237c5f2c9SAkshu Agrawal while (true) { 39337c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 39437c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 39537c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 39637c5f2c9SAkshu Agrawal break; 39737c5f2c9SAkshu Agrawal if (--count == 0) { 39837c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 39957be09c6SNavid Emamdoost r = -ETIMEDOUT; 40057be09c6SNavid Emamdoost goto failure; 40137c5f2c9SAkshu Agrawal } 40237c5f2c9SAkshu Agrawal udelay(100); 40337c5f2c9SAkshu Agrawal } 40437c5f2c9SAkshu Agrawal /* Enable clock to ACP and wait until the clock is enabled */ 40537c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 40637c5f2c9SAkshu Agrawal val = val | ACP_CONTROL__ClkEn_MASK; 40737c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 40837c5f2c9SAkshu Agrawal 40937c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 41037c5f2c9SAkshu Agrawal 41137c5f2c9SAkshu Agrawal while (true) { 41237c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 41337c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 41437c5f2c9SAkshu Agrawal break; 41537c5f2c9SAkshu Agrawal if (--count == 0) { 41637c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 41757be09c6SNavid Emamdoost r = -ETIMEDOUT; 41857be09c6SNavid Emamdoost goto failure; 41937c5f2c9SAkshu Agrawal } 42037c5f2c9SAkshu Agrawal udelay(100); 42137c5f2c9SAkshu Agrawal } 42237c5f2c9SAkshu Agrawal /* Deassert the SOFT RESET flags */ 42337c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 42437c5f2c9SAkshu Agrawal val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 42537c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 426a8fe58ceSMaruthi Bayyavarapu return 0; 42757be09c6SNavid Emamdoost 42857be09c6SNavid Emamdoost failure: 42957be09c6SNavid Emamdoost kfree(i2s_pdata); 43057be09c6SNavid Emamdoost kfree(adev->acp.acp_res); 43157be09c6SNavid Emamdoost kfree(adev->acp.acp_cell); 43257be09c6SNavid Emamdoost kfree(adev->acp.acp_genpd); 43357be09c6SNavid Emamdoost return r; 434a8fe58ceSMaruthi Bayyavarapu } 435a8fe58ceSMaruthi Bayyavarapu 436a8fe58ceSMaruthi Bayyavarapu /** 437a8fe58ceSMaruthi Bayyavarapu * acp_hw_fini - stop the hardware block 438a8fe58ceSMaruthi Bayyavarapu * 439adf0125aSLee Jones * @handle: handle used to pass amdgpu_device pointer 440a8fe58ceSMaruthi Bayyavarapu * 441a8fe58ceSMaruthi Bayyavarapu */ 442a8fe58ceSMaruthi Bayyavarapu static int acp_hw_fini(void *handle) 443a8fe58ceSMaruthi Bayyavarapu { 44437c5f2c9SAkshu Agrawal u32 val = 0; 44537c5f2c9SAkshu Agrawal u32 count = 0; 446a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 447a8fe58ceSMaruthi Bayyavarapu 448757124d9SAlex Deucher /* return early if no ACP */ 4491062ddb6SVijendar Mukunda if (!adev->acp.acp_genpd) { 450be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 451757124d9SAlex Deucher return 0; 452be2d6aa5SRex Zhu } 453757124d9SAlex Deucher 45437c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 45537c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 45637c5f2c9SAkshu Agrawal 45737c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 45837c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 45937c5f2c9SAkshu Agrawal 46037c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 46137c5f2c9SAkshu Agrawal while (true) { 46237c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 46337c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 46437c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 46537c5f2c9SAkshu Agrawal break; 46637c5f2c9SAkshu Agrawal if (--count == 0) { 46737c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 46837c5f2c9SAkshu Agrawal return -ETIMEDOUT; 46937c5f2c9SAkshu Agrawal } 47037c5f2c9SAkshu Agrawal udelay(100); 47137c5f2c9SAkshu Agrawal } 47237c5f2c9SAkshu Agrawal /* Disable ACP clock */ 47337c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 47437c5f2c9SAkshu Agrawal val &= ~ACP_CONTROL__ClkEn_MASK; 47537c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 47637c5f2c9SAkshu Agrawal 47737c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 47837c5f2c9SAkshu Agrawal 47937c5f2c9SAkshu Agrawal while (true) { 48037c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 48137c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 48237c5f2c9SAkshu Agrawal break; 48337c5f2c9SAkshu Agrawal if (--count == 0) { 48437c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 48537c5f2c9SAkshu Agrawal return -ETIMEDOUT; 48637c5f2c9SAkshu Agrawal } 48737c5f2c9SAkshu Agrawal udelay(100); 48837c5f2c9SAkshu Agrawal } 48937c5f2c9SAkshu Agrawal 490aff89028SKai-Heng Feng device_for_each_child(adev->acp.parent, NULL, 491aff89028SKai-Heng Feng acp_genpd_remove_device); 49225030321SMaruthi Srinivas Bayyavarapu 493a8fe58ceSMaruthi Bayyavarapu mfd_remove_devices(adev->acp.parent); 494a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_res); 4951062ddb6SVijendar Mukunda kfree(adev->acp.acp_genpd); 496a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_cell); 497a8fe58ceSMaruthi Bayyavarapu 498a8fe58ceSMaruthi Bayyavarapu return 0; 499a8fe58ceSMaruthi Bayyavarapu } 500a8fe58ceSMaruthi Bayyavarapu 501a8fe58ceSMaruthi Bayyavarapu static int acp_suspend(void *handle) 502a8fe58ceSMaruthi Bayyavarapu { 503be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 504be2d6aa5SRex Zhu 505be2d6aa5SRex Zhu /* power up on suspend */ 506be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 507be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 508a8fe58ceSMaruthi Bayyavarapu return 0; 509a8fe58ceSMaruthi Bayyavarapu } 510a8fe58ceSMaruthi Bayyavarapu 511a8fe58ceSMaruthi Bayyavarapu static int acp_resume(void *handle) 512a8fe58ceSMaruthi Bayyavarapu { 513be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 514be2d6aa5SRex Zhu 515be2d6aa5SRex Zhu /* power down again on resume */ 516be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 517be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 518a8fe58ceSMaruthi Bayyavarapu return 0; 519a8fe58ceSMaruthi Bayyavarapu } 520a8fe58ceSMaruthi Bayyavarapu 521a8fe58ceSMaruthi Bayyavarapu static int acp_early_init(void *handle) 522a8fe58ceSMaruthi Bayyavarapu { 523a8fe58ceSMaruthi Bayyavarapu return 0; 524a8fe58ceSMaruthi Bayyavarapu } 525a8fe58ceSMaruthi Bayyavarapu 526a8fe58ceSMaruthi Bayyavarapu static bool acp_is_idle(void *handle) 527a8fe58ceSMaruthi Bayyavarapu { 528a8fe58ceSMaruthi Bayyavarapu return true; 529a8fe58ceSMaruthi Bayyavarapu } 530a8fe58ceSMaruthi Bayyavarapu 531a8fe58ceSMaruthi Bayyavarapu static int acp_wait_for_idle(void *handle) 532a8fe58ceSMaruthi Bayyavarapu { 533a8fe58ceSMaruthi Bayyavarapu return 0; 534a8fe58ceSMaruthi Bayyavarapu } 535a8fe58ceSMaruthi Bayyavarapu 536a8fe58ceSMaruthi Bayyavarapu static int acp_soft_reset(void *handle) 537a8fe58ceSMaruthi Bayyavarapu { 538a8fe58ceSMaruthi Bayyavarapu return 0; 539a8fe58ceSMaruthi Bayyavarapu } 540a8fe58ceSMaruthi Bayyavarapu 541a8fe58ceSMaruthi Bayyavarapu static int acp_set_clockgating_state(void *handle, 542a8fe58ceSMaruthi Bayyavarapu enum amd_clockgating_state state) 543a8fe58ceSMaruthi Bayyavarapu { 544a8fe58ceSMaruthi Bayyavarapu return 0; 545a8fe58ceSMaruthi Bayyavarapu } 546a8fe58ceSMaruthi Bayyavarapu 547a8fe58ceSMaruthi Bayyavarapu static int acp_set_powergating_state(void *handle, 548a8fe58ceSMaruthi Bayyavarapu enum amd_powergating_state state) 549a8fe58ceSMaruthi Bayyavarapu { 550c36628d8SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 551a9d4fe2fSNirmoy Das bool enable = (state == AMD_PG_STATE_GATE); 552c36628d8SRex Zhu 553c36628d8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, enable); 554c36628d8SRex Zhu 555a8fe58ceSMaruthi Bayyavarapu return 0; 556a8fe58ceSMaruthi Bayyavarapu } 557a8fe58ceSMaruthi Bayyavarapu 558a1255107SAlex Deucher static const struct amd_ip_funcs acp_ip_funcs = { 55988a907d6STom St Denis .name = "acp_ip", 560a8fe58ceSMaruthi Bayyavarapu .early_init = acp_early_init, 561a8fe58ceSMaruthi Bayyavarapu .late_init = NULL, 562a8fe58ceSMaruthi Bayyavarapu .sw_init = acp_sw_init, 563a8fe58ceSMaruthi Bayyavarapu .sw_fini = acp_sw_fini, 564a8fe58ceSMaruthi Bayyavarapu .hw_init = acp_hw_init, 565a8fe58ceSMaruthi Bayyavarapu .hw_fini = acp_hw_fini, 566a8fe58ceSMaruthi Bayyavarapu .suspend = acp_suspend, 567a8fe58ceSMaruthi Bayyavarapu .resume = acp_resume, 568a8fe58ceSMaruthi Bayyavarapu .is_idle = acp_is_idle, 569a8fe58ceSMaruthi Bayyavarapu .wait_for_idle = acp_wait_for_idle, 570a8fe58ceSMaruthi Bayyavarapu .soft_reset = acp_soft_reset, 571a8fe58ceSMaruthi Bayyavarapu .set_clockgating_state = acp_set_clockgating_state, 572a8fe58ceSMaruthi Bayyavarapu .set_powergating_state = acp_set_powergating_state, 573a8fe58ceSMaruthi Bayyavarapu }; 574a1255107SAlex Deucher 575604d3a3fSVijendar Mukunda const struct amdgpu_ip_block_version acp_ip_block = { 576a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_ACP, 577a1255107SAlex Deucher .major = 2, 578a1255107SAlex Deucher .minor = 2, 579a1255107SAlex Deucher .rev = 0, 580a1255107SAlex Deucher .funcs = &acp_ip_funcs, 581a1255107SAlex Deucher }; 582