1a8fe58ceSMaruthi Bayyavarapu /* 2a8fe58ceSMaruthi Bayyavarapu * Copyright 2015 Advanced Micro Devices, Inc. 3a8fe58ceSMaruthi Bayyavarapu * 4a8fe58ceSMaruthi Bayyavarapu * Permission is hereby granted, free of charge, to any person obtaining a 5a8fe58ceSMaruthi Bayyavarapu * copy of this software and associated documentation files (the "Software"), 6a8fe58ceSMaruthi Bayyavarapu * to deal in the Software without restriction, including without limitation 7a8fe58ceSMaruthi Bayyavarapu * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8a8fe58ceSMaruthi Bayyavarapu * and/or sell copies of the Software, and to permit persons to whom the 9a8fe58ceSMaruthi Bayyavarapu * Software is furnished to do so, subject to the following conditions: 10a8fe58ceSMaruthi Bayyavarapu * 11a8fe58ceSMaruthi Bayyavarapu * The above copyright notice and this permission notice shall be included in 12a8fe58ceSMaruthi Bayyavarapu * all copies or substantial portions of the Software. 13a8fe58ceSMaruthi Bayyavarapu * 14a8fe58ceSMaruthi Bayyavarapu * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15a8fe58ceSMaruthi Bayyavarapu * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16a8fe58ceSMaruthi Bayyavarapu * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17a8fe58ceSMaruthi Bayyavarapu * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18a8fe58ceSMaruthi Bayyavarapu * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19a8fe58ceSMaruthi Bayyavarapu * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20a8fe58ceSMaruthi Bayyavarapu * OTHER DEALINGS IN THE SOFTWARE. 21a8fe58ceSMaruthi Bayyavarapu * 22a8fe58ceSMaruthi Bayyavarapu * Authors: AMD 23a8fe58ceSMaruthi Bayyavarapu * 24a8fe58ceSMaruthi Bayyavarapu */ 25a8fe58ceSMaruthi Bayyavarapu 26a8fe58ceSMaruthi Bayyavarapu #include <linux/irqdomain.h> 2725030321SMaruthi Srinivas Bayyavarapu #include <linux/pm_domain.h> 28a8fe58ceSMaruthi Bayyavarapu #include <linux/platform_device.h> 29a8fe58ceSMaruthi Bayyavarapu #include <sound/designware_i2s.h> 30a8fe58ceSMaruthi Bayyavarapu #include <sound/pcm.h> 31a8fe58ceSMaruthi Bayyavarapu 32a8fe58ceSMaruthi Bayyavarapu #include "amdgpu.h" 33a8fe58ceSMaruthi Bayyavarapu #include "atom.h" 34a8fe58ceSMaruthi Bayyavarapu #include "amdgpu_acp.h" 35a8fe58ceSMaruthi Bayyavarapu 36a8fe58ceSMaruthi Bayyavarapu #include "acp_gfx_if.h" 37a8fe58ceSMaruthi Bayyavarapu 38a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_MASK 0x03 39a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_MASK 0x02 40a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_ON_RETAIN_REG_MASK 0x1f 41a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_OFF_RETAIN_REG_MASK 0x20 42a8fe58ceSMaruthi Bayyavarapu 43a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P1_MASK 0x3e 44a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_P2_MASK 0x3d 45a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP0_MASK 0x3b 46a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP1_MASK 0x37 47a8fe58ceSMaruthi Bayyavarapu 48a8fe58ceSMaruthi Bayyavarapu #define ACP_TILE_DSP2_MASK 0x2f 49a8fe58ceSMaruthi Bayyavarapu 50a8fe58ceSMaruthi Bayyavarapu #define ACP_DMA_REGS_END 0x146c0 51a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_START 0x14840 52a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_PLAY_REGS_END 0x148b4 53a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_START 0x148b8 54a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_CAP_REGS_END 0x1496c 55a8fe58ceSMaruthi Bayyavarapu 56a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac 57a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 58a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 59a8fe58ceSMaruthi Bayyavarapu #define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 602d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_START 0x14970 612d95ceb4SVijendar Mukunda #define ACP_BT_PLAY_REGS_END 0x14a24 622d95ceb4SVijendar Mukunda #define ACP_BT_COMP1_REG_OFFSET 0xac 632d95ceb4SVijendar Mukunda #define ACP_BT_COMP2_REG_OFFSET 0xa8 64a8fe58ceSMaruthi Bayyavarapu 65a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_RETAIN_REG 0x51c9 66a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_CONFIG_REG 0x51ca 67a8fe58ceSMaruthi Bayyavarapu #define mmACP_PGFSM_READ_REG_0 0x51cc 68a8fe58ceSMaruthi Bayyavarapu 69a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8 70a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9 71a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa 72a8fe58ceSMaruthi Bayyavarapu #define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb 73a8fe58ceSMaruthi Bayyavarapu 7437c5f2c9SAkshu Agrawal #define mmACP_CONTROL 0x5131 7537c5f2c9SAkshu Agrawal #define mmACP_STATUS 0x5133 7637c5f2c9SAkshu Agrawal #define mmACP_SOFT_RESET 0x5134 7737c5f2c9SAkshu Agrawal #define ACP_CONTROL__ClkEn_MASK 0x1 7837c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100 7937c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000 8037c5f2c9SAkshu Agrawal #define ACP_CLOCK_EN_TIME_OUT_VALUE 0x000000FF 8137c5f2c9SAkshu Agrawal #define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 8237c5f2c9SAkshu Agrawal 83a8fe58ceSMaruthi Bayyavarapu #define ACP_TIMEOUT_LOOP 0x000000FF 842d95ceb4SVijendar Mukunda #define ACP_DEVS 4 85a8fe58ceSMaruthi Bayyavarapu #define ACP_SRC_ID 162 86a8fe58ceSMaruthi Bayyavarapu 87a8fe58ceSMaruthi Bayyavarapu enum { 88a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P1 = 0, 89a8fe58ceSMaruthi Bayyavarapu ACP_TILE_P2, 90a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP0, 91a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP1, 92a8fe58ceSMaruthi Bayyavarapu ACP_TILE_DSP2, 93a8fe58ceSMaruthi Bayyavarapu }; 94a8fe58ceSMaruthi Bayyavarapu 95a8fe58ceSMaruthi Bayyavarapu static int acp_sw_init(void *handle) 96a8fe58ceSMaruthi Bayyavarapu { 97a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 98a8fe58ceSMaruthi Bayyavarapu 99a8fe58ceSMaruthi Bayyavarapu adev->acp.parent = adev->dev; 100a8fe58ceSMaruthi Bayyavarapu 101a8fe58ceSMaruthi Bayyavarapu adev->acp.cgs_device = 102a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_create_device(adev); 103a8fe58ceSMaruthi Bayyavarapu if (!adev->acp.cgs_device) 104a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 105a8fe58ceSMaruthi Bayyavarapu 106a8fe58ceSMaruthi Bayyavarapu return 0; 107a8fe58ceSMaruthi Bayyavarapu } 108a8fe58ceSMaruthi Bayyavarapu 109a8fe58ceSMaruthi Bayyavarapu static int acp_sw_fini(void *handle) 110a8fe58ceSMaruthi Bayyavarapu { 111a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 112a8fe58ceSMaruthi Bayyavarapu 113a8fe58ceSMaruthi Bayyavarapu if (adev->acp.cgs_device) 114a8fe58ceSMaruthi Bayyavarapu amdgpu_cgs_destroy_device(adev->acp.cgs_device); 115a8fe58ceSMaruthi Bayyavarapu 116a8fe58ceSMaruthi Bayyavarapu return 0; 117a8fe58ceSMaruthi Bayyavarapu } 118a8fe58ceSMaruthi Bayyavarapu 11925030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain { 1203a54d2c8SRex Zhu void *adev; 12125030321SMaruthi Srinivas Bayyavarapu struct generic_pm_domain gpd; 12225030321SMaruthi Srinivas Bayyavarapu }; 12325030321SMaruthi Srinivas Bayyavarapu 12425030321SMaruthi Srinivas Bayyavarapu static int acp_poweroff(struct generic_pm_domain *genpd) 12525030321SMaruthi Srinivas Bayyavarapu { 12625030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1273a54d2c8SRex Zhu struct amdgpu_device *adev; 12825030321SMaruthi Srinivas Bayyavarapu 12925030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 13025030321SMaruthi Srinivas Bayyavarapu if (apd != NULL) { 1313a54d2c8SRex Zhu adev = apd->adev; 1323a54d2c8SRex Zhu /* call smu to POWER GATE ACP block 1333a54d2c8SRex Zhu * smu will 1343a54d2c8SRex Zhu * 1. turn off the acp clock 1353a54d2c8SRex Zhu * 2. power off the acp tiles 1363a54d2c8SRex Zhu * 3. check and enter ulv state 13725030321SMaruthi Srinivas Bayyavarapu */ 1383a54d2c8SRex Zhu if (adev->powerplay.pp_funcs->set_powergating_by_smu) 1393a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 14025030321SMaruthi Srinivas Bayyavarapu } 14125030321SMaruthi Srinivas Bayyavarapu return 0; 14225030321SMaruthi Srinivas Bayyavarapu } 14325030321SMaruthi Srinivas Bayyavarapu 14425030321SMaruthi Srinivas Bayyavarapu static int acp_poweron(struct generic_pm_domain *genpd) 14525030321SMaruthi Srinivas Bayyavarapu { 14625030321SMaruthi Srinivas Bayyavarapu struct acp_pm_domain *apd; 1473a54d2c8SRex Zhu struct amdgpu_device *adev; 14825030321SMaruthi Srinivas Bayyavarapu 14925030321SMaruthi Srinivas Bayyavarapu apd = container_of(genpd, struct acp_pm_domain, gpd); 15025030321SMaruthi Srinivas Bayyavarapu if (apd != NULL) { 1513a54d2c8SRex Zhu adev = apd->adev; 1523a54d2c8SRex Zhu /* call smu to UNGATE ACP block 1533a54d2c8SRex Zhu * smu will 1543a54d2c8SRex Zhu * 1. exit ulv 1553a54d2c8SRex Zhu * 2. turn on acp clock 1563a54d2c8SRex Zhu * 3. power on acp tiles 1573a54d2c8SRex Zhu */ 1583a54d2c8SRex Zhu if (adev->powerplay.pp_funcs->set_powergating_by_smu) 1593a54d2c8SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 16025030321SMaruthi Srinivas Bayyavarapu } 16125030321SMaruthi Srinivas Bayyavarapu return 0; 16225030321SMaruthi Srinivas Bayyavarapu } 16325030321SMaruthi Srinivas Bayyavarapu 16425030321SMaruthi Srinivas Bayyavarapu static struct device *get_mfd_cell_dev(const char *device_name, int r) 16525030321SMaruthi Srinivas Bayyavarapu { 16625030321SMaruthi Srinivas Bayyavarapu char auto_dev_name[25]; 16725030321SMaruthi Srinivas Bayyavarapu struct device *dev; 16825030321SMaruthi Srinivas Bayyavarapu 169a65ecc40SDan Carpenter snprintf(auto_dev_name, sizeof(auto_dev_name), 170a65ecc40SDan Carpenter "%s.%d.auto", device_name, r); 17125030321SMaruthi Srinivas Bayyavarapu dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name); 17225030321SMaruthi Srinivas Bayyavarapu dev_info(dev, "device %s added to pm domain\n", auto_dev_name); 17325030321SMaruthi Srinivas Bayyavarapu 17425030321SMaruthi Srinivas Bayyavarapu return dev; 17525030321SMaruthi Srinivas Bayyavarapu } 17625030321SMaruthi Srinivas Bayyavarapu 177a8fe58ceSMaruthi Bayyavarapu /** 178a8fe58ceSMaruthi Bayyavarapu * acp_hw_init - start and test ACP block 179a8fe58ceSMaruthi Bayyavarapu * 180a8fe58ceSMaruthi Bayyavarapu * @adev: amdgpu_device pointer 181a8fe58ceSMaruthi Bayyavarapu * 182a8fe58ceSMaruthi Bayyavarapu */ 183a8fe58ceSMaruthi Bayyavarapu static int acp_hw_init(void *handle) 184a8fe58ceSMaruthi Bayyavarapu { 18525030321SMaruthi Srinivas Bayyavarapu int r, i; 186a8fe58ceSMaruthi Bayyavarapu uint64_t acp_base; 18737c5f2c9SAkshu Agrawal u32 val = 0; 18837c5f2c9SAkshu Agrawal u32 count = 0; 18925030321SMaruthi Srinivas Bayyavarapu struct device *dev; 190a8fe58ceSMaruthi Bayyavarapu struct i2s_platform_data *i2s_pdata; 191a8fe58ceSMaruthi Bayyavarapu 192a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 193a8fe58ceSMaruthi Bayyavarapu 194a1255107SAlex Deucher const struct amdgpu_ip_block *ip_block = 1952990a1fcSAlex Deucher amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); 196a8fe58ceSMaruthi Bayyavarapu 197a1255107SAlex Deucher if (!ip_block) 198a8fe58ceSMaruthi Bayyavarapu return -EINVAL; 199a8fe58ceSMaruthi Bayyavarapu 200a8fe58ceSMaruthi Bayyavarapu r = amd_acp_hw_init(adev->acp.cgs_device, 201a1255107SAlex Deucher ip_block->version->major, ip_block->version->minor); 202a8fe58ceSMaruthi Bayyavarapu /* -ENODEV means board uses AZ rather than ACP */ 203be2d6aa5SRex Zhu if (r == -ENODEV) { 204be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 205a8fe58ceSMaruthi Bayyavarapu return 0; 206be2d6aa5SRex Zhu } else if (r) { 207a8fe58ceSMaruthi Bayyavarapu return r; 208be2d6aa5SRex Zhu } 209a8fe58ceSMaruthi Bayyavarapu 210d32d6617SRex Zhu if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) 211d32d6617SRex Zhu return -EINVAL; 212d32d6617SRex Zhu 213d32d6617SRex Zhu acp_base = adev->rmmio_base; 214d32d6617SRex Zhu 2151062ddb6SVijendar Mukunda 21625030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL); 21725030321SMaruthi Srinivas Bayyavarapu if (adev->acp.acp_genpd == NULL) 21825030321SMaruthi Srinivas Bayyavarapu return -ENOMEM; 21925030321SMaruthi Srinivas Bayyavarapu 22025030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.name = "ACP_AUDIO"; 22125030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_off = acp_poweroff; 22225030321SMaruthi Srinivas Bayyavarapu adev->acp.acp_genpd->gpd.power_on = acp_poweron; 22325030321SMaruthi Srinivas Bayyavarapu 22425030321SMaruthi Srinivas Bayyavarapu 2253a54d2c8SRex Zhu adev->acp.acp_genpd->adev = adev; 22625030321SMaruthi Srinivas Bayyavarapu 22725030321SMaruthi Srinivas Bayyavarapu pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false); 22825030321SMaruthi Srinivas Bayyavarapu 2296396bb22SKees Cook adev->acp.acp_cell = kcalloc(ACP_DEVS, sizeof(struct mfd_cell), 230a8fe58ceSMaruthi Bayyavarapu GFP_KERNEL); 231a8fe58ceSMaruthi Bayyavarapu 232a8fe58ceSMaruthi Bayyavarapu if (adev->acp.acp_cell == NULL) 233a8fe58ceSMaruthi Bayyavarapu return -ENOMEM; 234a8fe58ceSMaruthi Bayyavarapu 2352d95ceb4SVijendar Mukunda adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL); 236a8fe58ceSMaruthi Bayyavarapu if (adev->acp.acp_res == NULL) { 237a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_cell); 238a8fe58ceSMaruthi Bayyavarapu return -ENOMEM; 239a8fe58ceSMaruthi Bayyavarapu } 240a8fe58ceSMaruthi Bayyavarapu 2412d95ceb4SVijendar Mukunda i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL); 242a8fe58ceSMaruthi Bayyavarapu if (i2s_pdata == NULL) { 243a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_res); 244a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_cell); 245a8fe58ceSMaruthi Bayyavarapu return -ENOMEM; 246a8fe58ceSMaruthi Bayyavarapu } 247a8fe58ceSMaruthi Bayyavarapu 24881454cadSVijendar Mukunda switch (adev->asic_type) { 24981454cadSVijendar Mukunda case CHIP_STONEY: 25081454cadSVijendar Mukunda i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 25181454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 25281454cadSVijendar Mukunda break; 25381454cadSVijendar Mukunda default: 254a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 25581454cadSVijendar Mukunda } 256a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].cap = DWC_I2S_PLAY; 257a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000; 258a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET; 259a8fe58ceSMaruthi Bayyavarapu i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET; 26081454cadSVijendar Mukunda switch (adev->asic_type) { 26181454cadSVijendar Mukunda case CHIP_STONEY: 26281454cadSVijendar Mukunda i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 26381454cadSVijendar Mukunda DW_I2S_QUIRK_COMP_PARAM1 | 26481454cadSVijendar Mukunda DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 26581454cadSVijendar Mukunda break; 26681454cadSVijendar Mukunda default: 267a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET | 268a8fe58ceSMaruthi Bayyavarapu DW_I2S_QUIRK_COMP_PARAM1; 26981454cadSVijendar Mukunda } 27081454cadSVijendar Mukunda 271a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].cap = DWC_I2S_RECORD; 272a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000; 273a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 274a8fe58ceSMaruthi Bayyavarapu i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 275a8fe58ceSMaruthi Bayyavarapu 2762d95ceb4SVijendar Mukunda i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET; 2772d95ceb4SVijendar Mukunda switch (adev->asic_type) { 2782d95ceb4SVijendar Mukunda case CHIP_STONEY: 2792d95ceb4SVijendar Mukunda i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE; 2802d95ceb4SVijendar Mukunda break; 2812d95ceb4SVijendar Mukunda default: 2822d95ceb4SVijendar Mukunda break; 2832d95ceb4SVijendar Mukunda } 2842d95ceb4SVijendar Mukunda 2852d95ceb4SVijendar Mukunda i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD; 2862d95ceb4SVijendar Mukunda i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000; 2872d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET; 2882d95ceb4SVijendar Mukunda i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET; 2892d95ceb4SVijendar Mukunda 290a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].name = "acp2x_dma"; 291a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].flags = IORESOURCE_MEM; 292a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].start = acp_base; 293a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END; 294a8fe58ceSMaruthi Bayyavarapu 295a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].name = "acp2x_dw_i2s_play"; 296a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].flags = IORESOURCE_MEM; 297a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START; 298a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END; 299a8fe58ceSMaruthi Bayyavarapu 300a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap"; 301a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].flags = IORESOURCE_MEM; 302a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 303a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 304a8fe58ceSMaruthi Bayyavarapu 3052d95ceb4SVijendar Mukunda adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap"; 3062d95ceb4SVijendar Mukunda adev->acp.acp_res[3].flags = IORESOURCE_MEM; 3072d95ceb4SVijendar Mukunda adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START; 3082d95ceb4SVijendar Mukunda adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END; 3092d95ceb4SVijendar Mukunda 3102d95ceb4SVijendar Mukunda adev->acp.acp_res[4].name = "acp2x_dma_irq"; 3112d95ceb4SVijendar Mukunda adev->acp.acp_res[4].flags = IORESOURCE_IRQ; 3122d95ceb4SVijendar Mukunda adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162); 3132d95ceb4SVijendar Mukunda adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; 314a8fe58ceSMaruthi Bayyavarapu 315a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].name = "acp_audio_dma"; 3162d95ceb4SVijendar Mukunda adev->acp.acp_cell[0].num_resources = 5; 317a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 3181fd16f36SVijendar Mukunda adev->acp.acp_cell[0].platform_data = &adev->asic_type; 3191fd16f36SVijendar Mukunda adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 320a8fe58ceSMaruthi Bayyavarapu 321a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].name = "designware-i2s"; 322a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].num_resources = 1; 323a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; 324a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].platform_data = &i2s_pdata[0]; 325a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data); 326a8fe58ceSMaruthi Bayyavarapu 327a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].name = "designware-i2s"; 328a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].num_resources = 1; 329a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; 330a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 331a8fe58ceSMaruthi Bayyavarapu adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 332a8fe58ceSMaruthi Bayyavarapu 3332d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].name = "designware-i2s"; 3342d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].num_resources = 1; 3352d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; 3362d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].platform_data = &i2s_pdata[2]; 3372d95ceb4SVijendar Mukunda adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data); 3382d95ceb4SVijendar Mukunda 339a8fe58ceSMaruthi Bayyavarapu r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, 340a8fe58ceSMaruthi Bayyavarapu ACP_DEVS); 341a8fe58ceSMaruthi Bayyavarapu if (r) 342a8fe58ceSMaruthi Bayyavarapu return r; 343a8fe58ceSMaruthi Bayyavarapu 34425030321SMaruthi Srinivas Bayyavarapu for (i = 0; i < ACP_DEVS ; i++) { 34525030321SMaruthi Srinivas Bayyavarapu dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); 34625030321SMaruthi Srinivas Bayyavarapu r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev); 34725030321SMaruthi Srinivas Bayyavarapu if (r) { 34825030321SMaruthi Srinivas Bayyavarapu dev_err(dev, "Failed to add dev to genpd\n"); 34925030321SMaruthi Srinivas Bayyavarapu return r; 35025030321SMaruthi Srinivas Bayyavarapu } 35125030321SMaruthi Srinivas Bayyavarapu } 3521062ddb6SVijendar Mukunda 35325030321SMaruthi Srinivas Bayyavarapu 35437c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 35537c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 35637c5f2c9SAkshu Agrawal 35737c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 35837c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 35937c5f2c9SAkshu Agrawal 36037c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 36137c5f2c9SAkshu Agrawal while (true) { 36237c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 36337c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 36437c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 36537c5f2c9SAkshu Agrawal break; 36637c5f2c9SAkshu Agrawal if (--count == 0) { 36737c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 36837c5f2c9SAkshu Agrawal return -ETIMEDOUT; 36937c5f2c9SAkshu Agrawal } 37037c5f2c9SAkshu Agrawal udelay(100); 37137c5f2c9SAkshu Agrawal } 37237c5f2c9SAkshu Agrawal /* Enable clock to ACP and wait until the clock is enabled */ 37337c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 37437c5f2c9SAkshu Agrawal val = val | ACP_CONTROL__ClkEn_MASK; 37537c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 37637c5f2c9SAkshu Agrawal 37737c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 37837c5f2c9SAkshu Agrawal 37937c5f2c9SAkshu Agrawal while (true) { 38037c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 38137c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 38237c5f2c9SAkshu Agrawal break; 38337c5f2c9SAkshu Agrawal if (--count == 0) { 38437c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 38537c5f2c9SAkshu Agrawal return -ETIMEDOUT; 38637c5f2c9SAkshu Agrawal } 38737c5f2c9SAkshu Agrawal udelay(100); 38837c5f2c9SAkshu Agrawal } 38937c5f2c9SAkshu Agrawal /* Deassert the SOFT RESET flags */ 39037c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 39137c5f2c9SAkshu Agrawal val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 39237c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 393a8fe58ceSMaruthi Bayyavarapu return 0; 394a8fe58ceSMaruthi Bayyavarapu } 395a8fe58ceSMaruthi Bayyavarapu 396a8fe58ceSMaruthi Bayyavarapu /** 397a8fe58ceSMaruthi Bayyavarapu * acp_hw_fini - stop the hardware block 398a8fe58ceSMaruthi Bayyavarapu * 399a8fe58ceSMaruthi Bayyavarapu * @adev: amdgpu_device pointer 400a8fe58ceSMaruthi Bayyavarapu * 401a8fe58ceSMaruthi Bayyavarapu */ 402a8fe58ceSMaruthi Bayyavarapu static int acp_hw_fini(void *handle) 403a8fe58ceSMaruthi Bayyavarapu { 40425030321SMaruthi Srinivas Bayyavarapu int i, ret; 40537c5f2c9SAkshu Agrawal u32 val = 0; 40637c5f2c9SAkshu Agrawal u32 count = 0; 40725030321SMaruthi Srinivas Bayyavarapu struct device *dev; 408a8fe58ceSMaruthi Bayyavarapu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 409a8fe58ceSMaruthi Bayyavarapu 410757124d9SAlex Deucher /* return early if no ACP */ 4111062ddb6SVijendar Mukunda if (!adev->acp.acp_genpd) { 412be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 413757124d9SAlex Deucher return 0; 414be2d6aa5SRex Zhu } 415757124d9SAlex Deucher 41637c5f2c9SAkshu Agrawal /* Assert Soft reset of ACP */ 41737c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 41837c5f2c9SAkshu Agrawal 41937c5f2c9SAkshu Agrawal val |= ACP_SOFT_RESET__SoftResetAud_MASK; 42037c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 42137c5f2c9SAkshu Agrawal 42237c5f2c9SAkshu Agrawal count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 42337c5f2c9SAkshu Agrawal while (true) { 42437c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 42537c5f2c9SAkshu Agrawal if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 42637c5f2c9SAkshu Agrawal (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 42737c5f2c9SAkshu Agrawal break; 42837c5f2c9SAkshu Agrawal if (--count == 0) { 42937c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 43037c5f2c9SAkshu Agrawal return -ETIMEDOUT; 43137c5f2c9SAkshu Agrawal } 43237c5f2c9SAkshu Agrawal udelay(100); 43337c5f2c9SAkshu Agrawal } 43437c5f2c9SAkshu Agrawal /* Disable ACP clock */ 43537c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_CONTROL); 43637c5f2c9SAkshu Agrawal val &= ~ACP_CONTROL__ClkEn_MASK; 43737c5f2c9SAkshu Agrawal cgs_write_register(adev->acp.cgs_device, mmACP_CONTROL, val); 43837c5f2c9SAkshu Agrawal 43937c5f2c9SAkshu Agrawal count = ACP_CLOCK_EN_TIME_OUT_VALUE; 44037c5f2c9SAkshu Agrawal 44137c5f2c9SAkshu Agrawal while (true) { 44237c5f2c9SAkshu Agrawal val = cgs_read_register(adev->acp.cgs_device, mmACP_STATUS); 44337c5f2c9SAkshu Agrawal if (val & (u32) 0x1) 44437c5f2c9SAkshu Agrawal break; 44537c5f2c9SAkshu Agrawal if (--count == 0) { 44637c5f2c9SAkshu Agrawal dev_err(&adev->pdev->dev, "Failed to reset ACP\n"); 44737c5f2c9SAkshu Agrawal return -ETIMEDOUT; 44837c5f2c9SAkshu Agrawal } 44937c5f2c9SAkshu Agrawal udelay(100); 45037c5f2c9SAkshu Agrawal } 45137c5f2c9SAkshu Agrawal 45225030321SMaruthi Srinivas Bayyavarapu for (i = 0; i < ACP_DEVS ; i++) { 45325030321SMaruthi Srinivas Bayyavarapu dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i); 454924f4486SUlf Hansson ret = pm_genpd_remove_device(dev); 45525030321SMaruthi Srinivas Bayyavarapu /* If removal fails, dont giveup and try rest */ 45625030321SMaruthi Srinivas Bayyavarapu if (ret) 45725030321SMaruthi Srinivas Bayyavarapu dev_err(dev, "remove dev from genpd failed\n"); 45825030321SMaruthi Srinivas Bayyavarapu } 45925030321SMaruthi Srinivas Bayyavarapu 460a8fe58ceSMaruthi Bayyavarapu mfd_remove_devices(adev->acp.parent); 461a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_res); 4621062ddb6SVijendar Mukunda kfree(adev->acp.acp_genpd); 463a8fe58ceSMaruthi Bayyavarapu kfree(adev->acp.acp_cell); 464a8fe58ceSMaruthi Bayyavarapu 465a8fe58ceSMaruthi Bayyavarapu return 0; 466a8fe58ceSMaruthi Bayyavarapu } 467a8fe58ceSMaruthi Bayyavarapu 468a8fe58ceSMaruthi Bayyavarapu static int acp_suspend(void *handle) 469a8fe58ceSMaruthi Bayyavarapu { 470be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 471be2d6aa5SRex Zhu 472be2d6aa5SRex Zhu /* power up on suspend */ 473be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 474be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, false); 475a8fe58ceSMaruthi Bayyavarapu return 0; 476a8fe58ceSMaruthi Bayyavarapu } 477a8fe58ceSMaruthi Bayyavarapu 478a8fe58ceSMaruthi Bayyavarapu static int acp_resume(void *handle) 479a8fe58ceSMaruthi Bayyavarapu { 480be2d6aa5SRex Zhu struct amdgpu_device *adev = (struct amdgpu_device *)handle; 481be2d6aa5SRex Zhu 482be2d6aa5SRex Zhu /* power down again on resume */ 483be2d6aa5SRex Zhu if (!adev->acp.acp_cell) 484be2d6aa5SRex Zhu amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_ACP, true); 485a8fe58ceSMaruthi Bayyavarapu return 0; 486a8fe58ceSMaruthi Bayyavarapu } 487a8fe58ceSMaruthi Bayyavarapu 488a8fe58ceSMaruthi Bayyavarapu static int acp_early_init(void *handle) 489a8fe58ceSMaruthi Bayyavarapu { 490a8fe58ceSMaruthi Bayyavarapu return 0; 491a8fe58ceSMaruthi Bayyavarapu } 492a8fe58ceSMaruthi Bayyavarapu 493a8fe58ceSMaruthi Bayyavarapu static bool acp_is_idle(void *handle) 494a8fe58ceSMaruthi Bayyavarapu { 495a8fe58ceSMaruthi Bayyavarapu return true; 496a8fe58ceSMaruthi Bayyavarapu } 497a8fe58ceSMaruthi Bayyavarapu 498a8fe58ceSMaruthi Bayyavarapu static int acp_wait_for_idle(void *handle) 499a8fe58ceSMaruthi Bayyavarapu { 500a8fe58ceSMaruthi Bayyavarapu return 0; 501a8fe58ceSMaruthi Bayyavarapu } 502a8fe58ceSMaruthi Bayyavarapu 503a8fe58ceSMaruthi Bayyavarapu static int acp_soft_reset(void *handle) 504a8fe58ceSMaruthi Bayyavarapu { 505a8fe58ceSMaruthi Bayyavarapu return 0; 506a8fe58ceSMaruthi Bayyavarapu } 507a8fe58ceSMaruthi Bayyavarapu 508a8fe58ceSMaruthi Bayyavarapu static int acp_set_clockgating_state(void *handle, 509a8fe58ceSMaruthi Bayyavarapu enum amd_clockgating_state state) 510a8fe58ceSMaruthi Bayyavarapu { 511a8fe58ceSMaruthi Bayyavarapu return 0; 512a8fe58ceSMaruthi Bayyavarapu } 513a8fe58ceSMaruthi Bayyavarapu 514a8fe58ceSMaruthi Bayyavarapu static int acp_set_powergating_state(void *handle, 515a8fe58ceSMaruthi Bayyavarapu enum amd_powergating_state state) 516a8fe58ceSMaruthi Bayyavarapu { 517a8fe58ceSMaruthi Bayyavarapu return 0; 518a8fe58ceSMaruthi Bayyavarapu } 519a8fe58ceSMaruthi Bayyavarapu 520a1255107SAlex Deucher static const struct amd_ip_funcs acp_ip_funcs = { 52188a907d6STom St Denis .name = "acp_ip", 522a8fe58ceSMaruthi Bayyavarapu .early_init = acp_early_init, 523a8fe58ceSMaruthi Bayyavarapu .late_init = NULL, 524a8fe58ceSMaruthi Bayyavarapu .sw_init = acp_sw_init, 525a8fe58ceSMaruthi Bayyavarapu .sw_fini = acp_sw_fini, 526a8fe58ceSMaruthi Bayyavarapu .hw_init = acp_hw_init, 527a8fe58ceSMaruthi Bayyavarapu .hw_fini = acp_hw_fini, 528a8fe58ceSMaruthi Bayyavarapu .suspend = acp_suspend, 529a8fe58ceSMaruthi Bayyavarapu .resume = acp_resume, 530a8fe58ceSMaruthi Bayyavarapu .is_idle = acp_is_idle, 531a8fe58ceSMaruthi Bayyavarapu .wait_for_idle = acp_wait_for_idle, 532a8fe58ceSMaruthi Bayyavarapu .soft_reset = acp_soft_reset, 533a8fe58ceSMaruthi Bayyavarapu .set_clockgating_state = acp_set_clockgating_state, 534a8fe58ceSMaruthi Bayyavarapu .set_powergating_state = acp_set_powergating_state, 535a8fe58ceSMaruthi Bayyavarapu }; 536a1255107SAlex Deucher 537a1255107SAlex Deucher const struct amdgpu_ip_block_version acp_ip_block = 538a1255107SAlex Deucher { 539a1255107SAlex Deucher .type = AMD_IP_BLOCK_TYPE_ACP, 540a1255107SAlex Deucher .major = 2, 541a1255107SAlex Deucher .minor = 2, 542a1255107SAlex Deucher .rev = 0, 543a1255107SAlex Deucher .funcs = &acp_ip_funcs, 544a1255107SAlex Deucher }; 545