1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_gart.h" 79 #include "amdgpu_debugfs.h" 80 #include "amdgpu_job.h" 81 #include "amdgpu_bo_list.h" 82 #include "amdgpu_gem.h" 83 84 /* 85 * Modules parameters. 86 */ 87 extern int amdgpu_modeset; 88 extern int amdgpu_vram_limit; 89 extern int amdgpu_vis_vram_limit; 90 extern int amdgpu_gart_size; 91 extern int amdgpu_gtt_size; 92 extern int amdgpu_moverate; 93 extern int amdgpu_benchmarking; 94 extern int amdgpu_testing; 95 extern int amdgpu_audio; 96 extern int amdgpu_disp_priority; 97 extern int amdgpu_hw_i2c; 98 extern int amdgpu_pcie_gen2; 99 extern int amdgpu_msi; 100 extern int amdgpu_lockup_timeout; 101 extern int amdgpu_dpm; 102 extern int amdgpu_fw_load_type; 103 extern int amdgpu_aspm; 104 extern int amdgpu_runtime_pm; 105 extern uint amdgpu_ip_block_mask; 106 extern int amdgpu_bapm; 107 extern int amdgpu_deep_color; 108 extern int amdgpu_vm_size; 109 extern int amdgpu_vm_block_size; 110 extern int amdgpu_vm_fragment_size; 111 extern int amdgpu_vm_fault_stop; 112 extern int amdgpu_vm_debug; 113 extern int amdgpu_vm_update_mode; 114 extern int amdgpu_dc; 115 extern int amdgpu_sched_jobs; 116 extern int amdgpu_sched_hw_submission; 117 extern uint amdgpu_pcie_gen_cap; 118 extern uint amdgpu_pcie_lane_cap; 119 extern uint amdgpu_cg_mask; 120 extern uint amdgpu_pg_mask; 121 extern uint amdgpu_sdma_phase_quantum; 122 extern char *amdgpu_disable_cu; 123 extern char *amdgpu_virtual_display; 124 extern uint amdgpu_pp_feature_mask; 125 extern int amdgpu_vram_page_split; 126 extern int amdgpu_ngg; 127 extern int amdgpu_prim_buf_per_se; 128 extern int amdgpu_pos_buf_per_se; 129 extern int amdgpu_cntl_sb_buf_per_se; 130 extern int amdgpu_param_buf_per_se; 131 extern int amdgpu_job_hang_limit; 132 extern int amdgpu_lbpw; 133 extern int amdgpu_compute_multipipe; 134 extern int amdgpu_gpu_recovery; 135 extern int amdgpu_emu_mode; 136 extern uint amdgpu_smu_memory_pool_size; 137 138 #ifdef CONFIG_DRM_AMDGPU_SI 139 extern int amdgpu_si_support; 140 #endif 141 #ifdef CONFIG_DRM_AMDGPU_CIK 142 extern int amdgpu_cik_support; 143 #endif 144 145 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 146 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 147 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 148 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 149 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 150 #define AMDGPU_IB_POOL_SIZE 16 151 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 152 #define AMDGPUFB_CONN_LIMIT 4 153 #define AMDGPU_BIOS_NUM_SCRATCH 16 154 155 /* hard reset data */ 156 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 157 158 /* reset flags */ 159 #define AMDGPU_RESET_GFX (1 << 0) 160 #define AMDGPU_RESET_COMPUTE (1 << 1) 161 #define AMDGPU_RESET_DMA (1 << 2) 162 #define AMDGPU_RESET_CP (1 << 3) 163 #define AMDGPU_RESET_GRBM (1 << 4) 164 #define AMDGPU_RESET_DMA1 (1 << 5) 165 #define AMDGPU_RESET_RLC (1 << 6) 166 #define AMDGPU_RESET_SEM (1 << 7) 167 #define AMDGPU_RESET_IH (1 << 8) 168 #define AMDGPU_RESET_VMC (1 << 9) 169 #define AMDGPU_RESET_MC (1 << 10) 170 #define AMDGPU_RESET_DISPLAY (1 << 11) 171 #define AMDGPU_RESET_UVD (1 << 12) 172 #define AMDGPU_RESET_VCE (1 << 13) 173 #define AMDGPU_RESET_VCE1 (1 << 14) 174 175 /* max cursor sizes (in pixels) */ 176 #define CIK_CURSOR_WIDTH 128 177 #define CIK_CURSOR_HEIGHT 128 178 179 struct amdgpu_device; 180 struct amdgpu_ib; 181 struct amdgpu_cs_parser; 182 struct amdgpu_job; 183 struct amdgpu_irq_src; 184 struct amdgpu_fpriv; 185 struct amdgpu_bo_va_mapping; 186 struct amdgpu_atif; 187 188 enum amdgpu_cp_irq { 189 AMDGPU_CP_IRQ_GFX_EOP = 0, 190 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 191 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 194 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 195 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 198 199 AMDGPU_CP_IRQ_LAST 200 }; 201 202 enum amdgpu_thermal_irq { 203 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 204 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 205 206 AMDGPU_THERMAL_IRQ_LAST 207 }; 208 209 enum amdgpu_kiq_irq { 210 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 211 AMDGPU_CP_KIQ_IRQ_LAST 212 }; 213 214 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 215 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 216 #define MAX_KIQ_REG_TRY 20 217 218 int amdgpu_device_ip_set_clockgating_state(void *dev, 219 enum amd_ip_block_type block_type, 220 enum amd_clockgating_state state); 221 int amdgpu_device_ip_set_powergating_state(void *dev, 222 enum amd_ip_block_type block_type, 223 enum amd_powergating_state state); 224 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 225 u32 *flags); 226 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 227 enum amd_ip_block_type block_type); 228 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 229 enum amd_ip_block_type block_type); 230 231 #define AMDGPU_MAX_IP_NUM 16 232 233 struct amdgpu_ip_block_status { 234 bool valid; 235 bool sw; 236 bool hw; 237 bool late_initialized; 238 bool hang; 239 }; 240 241 struct amdgpu_ip_block_version { 242 const enum amd_ip_block_type type; 243 const u32 major; 244 const u32 minor; 245 const u32 rev; 246 const struct amd_ip_funcs *funcs; 247 }; 248 249 struct amdgpu_ip_block { 250 struct amdgpu_ip_block_status status; 251 const struct amdgpu_ip_block_version *version; 252 }; 253 254 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 255 enum amd_ip_block_type type, 256 u32 major, u32 minor); 257 258 struct amdgpu_ip_block * 259 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 260 enum amd_ip_block_type type); 261 262 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 263 const struct amdgpu_ip_block_version *ip_block_version); 264 265 /* 266 * BIOS. 267 */ 268 bool amdgpu_get_bios(struct amdgpu_device *adev); 269 bool amdgpu_read_bios(struct amdgpu_device *adev); 270 271 /* 272 * Clocks 273 */ 274 275 #define AMDGPU_MAX_PPLL 3 276 277 struct amdgpu_clock { 278 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 279 struct amdgpu_pll spll; 280 struct amdgpu_pll mpll; 281 /* 10 Khz units */ 282 uint32_t default_mclk; 283 uint32_t default_sclk; 284 uint32_t default_dispclk; 285 uint32_t current_dispclk; 286 uint32_t dp_extclk; 287 uint32_t max_pixel_clock; 288 }; 289 290 /* sub-allocation manager, it has to be protected by another lock. 291 * By conception this is an helper for other part of the driver 292 * like the indirect buffer or semaphore, which both have their 293 * locking. 294 * 295 * Principe is simple, we keep a list of sub allocation in offset 296 * order (first entry has offset == 0, last entry has the highest 297 * offset). 298 * 299 * When allocating new object we first check if there is room at 300 * the end total_size - (last_object_offset + last_object_size) >= 301 * alloc_size. If so we allocate new object there. 302 * 303 * When there is not enough room at the end, we start waiting for 304 * each sub object until we reach object_offset+object_size >= 305 * alloc_size, this object then become the sub object we return. 306 * 307 * Alignment can't be bigger than page size. 308 * 309 * Hole are not considered for allocation to keep things simple. 310 * Assumption is that there won't be hole (all object on same 311 * alignment). 312 */ 313 314 #define AMDGPU_SA_NUM_FENCE_LISTS 32 315 316 struct amdgpu_sa_manager { 317 wait_queue_head_t wq; 318 struct amdgpu_bo *bo; 319 struct list_head *hole; 320 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 321 struct list_head olist; 322 unsigned size; 323 uint64_t gpu_addr; 324 void *cpu_ptr; 325 uint32_t domain; 326 uint32_t align; 327 }; 328 329 /* sub-allocation buffer */ 330 struct amdgpu_sa_bo { 331 struct list_head olist; 332 struct list_head flist; 333 struct amdgpu_sa_manager *manager; 334 unsigned soffset; 335 unsigned eoffset; 336 struct dma_fence *fence; 337 }; 338 339 int amdgpu_fence_slab_init(void); 340 void amdgpu_fence_slab_fini(void); 341 342 /* 343 * GPU doorbell structures, functions & helpers 344 */ 345 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 346 { 347 AMDGPU_DOORBELL_KIQ = 0x000, 348 AMDGPU_DOORBELL_HIQ = 0x001, 349 AMDGPU_DOORBELL_DIQ = 0x002, 350 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 351 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 352 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 353 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 354 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 355 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 356 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 357 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 358 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 359 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 360 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 361 AMDGPU_DOORBELL_IH = 0x1E8, 362 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 363 AMDGPU_DOORBELL_INVALID = 0xFFFF 364 } AMDGPU_DOORBELL_ASSIGNMENT; 365 366 struct amdgpu_doorbell { 367 /* doorbell mmio */ 368 resource_size_t base; 369 resource_size_t size; 370 u32 __iomem *ptr; 371 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 372 }; 373 374 /* 375 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 376 */ 377 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 378 { 379 /* 380 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 381 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 382 * Compute related doorbells are allocated from 0x00 to 0x8a 383 */ 384 385 386 /* kernel scheduling */ 387 AMDGPU_DOORBELL64_KIQ = 0x00, 388 389 /* HSA interface queue and debug queue */ 390 AMDGPU_DOORBELL64_HIQ = 0x01, 391 AMDGPU_DOORBELL64_DIQ = 0x02, 392 393 /* Compute engines */ 394 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 395 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 396 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 397 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 398 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 399 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 400 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 401 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 402 403 /* User queue doorbell range (128 doorbells) */ 404 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 405 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 406 407 /* Graphics engine */ 408 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 409 410 /* 411 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 412 * Graphics voltage island aperture 1 413 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 414 */ 415 416 /* sDMA engines */ 417 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 418 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 419 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 420 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 421 422 /* Interrupt handler */ 423 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 424 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 425 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 426 427 /* VCN engine use 32 bits doorbell */ 428 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 429 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 430 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 431 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 432 433 /* overlap the doorbell assignment with VCN as they are mutually exclusive 434 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 435 */ 436 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8, 437 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9, 438 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA, 439 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB, 440 441 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC, 442 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD, 443 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE, 444 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF, 445 446 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 447 AMDGPU_DOORBELL64_INVALID = 0xFFFF 448 } AMDGPU_DOORBELL64_ASSIGNMENT; 449 450 /* 451 * IRQS. 452 */ 453 454 struct amdgpu_flip_work { 455 struct delayed_work flip_work; 456 struct work_struct unpin_work; 457 struct amdgpu_device *adev; 458 int crtc_id; 459 u32 target_vblank; 460 uint64_t base; 461 struct drm_pending_vblank_event *event; 462 struct amdgpu_bo *old_abo; 463 struct dma_fence *excl; 464 unsigned shared_count; 465 struct dma_fence **shared; 466 struct dma_fence_cb cb; 467 bool async; 468 }; 469 470 471 /* 472 * CP & rings. 473 */ 474 475 struct amdgpu_ib { 476 struct amdgpu_sa_bo *sa_bo; 477 uint32_t length_dw; 478 uint64_t gpu_addr; 479 uint32_t *ptr; 480 uint32_t flags; 481 }; 482 483 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 484 485 /* 486 * file private structure 487 */ 488 489 struct amdgpu_fpriv { 490 struct amdgpu_vm vm; 491 struct amdgpu_bo_va *prt_va; 492 struct amdgpu_bo_va *csa_va; 493 struct mutex bo_list_lock; 494 struct idr bo_list_handles; 495 struct amdgpu_ctx_mgr ctx_mgr; 496 }; 497 498 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 499 unsigned size, struct amdgpu_ib *ib); 500 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 501 struct dma_fence *f); 502 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 503 struct amdgpu_ib *ibs, struct amdgpu_job *job, 504 struct dma_fence **f); 505 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 506 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 507 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 508 509 /* 510 * CS. 511 */ 512 struct amdgpu_cs_chunk { 513 uint32_t chunk_id; 514 uint32_t length_dw; 515 void *kdata; 516 }; 517 518 struct amdgpu_cs_parser { 519 struct amdgpu_device *adev; 520 struct drm_file *filp; 521 struct amdgpu_ctx *ctx; 522 523 /* chunks */ 524 unsigned nchunks; 525 struct amdgpu_cs_chunk *chunks; 526 527 /* scheduler job object */ 528 struct amdgpu_job *job; 529 struct drm_sched_entity *entity; 530 531 /* buffer objects */ 532 struct ww_acquire_ctx ticket; 533 struct amdgpu_bo_list *bo_list; 534 struct amdgpu_mn *mn; 535 struct amdgpu_bo_list_entry vm_pd; 536 struct list_head validated; 537 struct dma_fence *fence; 538 uint64_t bytes_moved_threshold; 539 uint64_t bytes_moved_vis_threshold; 540 uint64_t bytes_moved; 541 uint64_t bytes_moved_vis; 542 struct amdgpu_bo_list_entry *evictable; 543 544 /* user fence */ 545 struct amdgpu_bo_list_entry uf_entry; 546 547 unsigned num_post_dep_syncobjs; 548 struct drm_syncobj **post_dep_syncobjs; 549 }; 550 551 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 552 uint32_t ib_idx, int idx) 553 { 554 return p->job->ibs[ib_idx].ptr[idx]; 555 } 556 557 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 558 uint32_t ib_idx, int idx, 559 uint32_t value) 560 { 561 p->job->ibs[ib_idx].ptr[idx] = value; 562 } 563 564 /* 565 * Writeback 566 */ 567 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 568 569 struct amdgpu_wb { 570 struct amdgpu_bo *wb_obj; 571 volatile uint32_t *wb; 572 uint64_t gpu_addr; 573 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 574 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 575 }; 576 577 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 578 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 579 580 /* 581 * Benchmarking 582 */ 583 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 584 585 586 /* 587 * Testing 588 */ 589 void amdgpu_test_moves(struct amdgpu_device *adev); 590 591 592 /* 593 * amdgpu smumgr functions 594 */ 595 struct amdgpu_smumgr_funcs { 596 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 597 int (*request_smu_load_fw)(struct amdgpu_device *adev); 598 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 599 }; 600 601 /* 602 * amdgpu smumgr 603 */ 604 struct amdgpu_smumgr { 605 struct amdgpu_bo *toc_buf; 606 struct amdgpu_bo *smu_buf; 607 /* asic priv smu data */ 608 void *priv; 609 spinlock_t smu_lock; 610 /* smumgr functions */ 611 const struct amdgpu_smumgr_funcs *smumgr_funcs; 612 /* ucode loading complete flag */ 613 uint32_t fw_flags; 614 }; 615 616 /* 617 * ASIC specific register table accessible by UMD 618 */ 619 struct amdgpu_allowed_register_entry { 620 uint32_t reg_offset; 621 bool grbm_indexed; 622 }; 623 624 /* 625 * ASIC specific functions. 626 */ 627 struct amdgpu_asic_funcs { 628 bool (*read_disabled_bios)(struct amdgpu_device *adev); 629 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 630 u8 *bios, u32 length_bytes); 631 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 632 u32 sh_num, u32 reg_offset, u32 *value); 633 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 634 int (*reset)(struct amdgpu_device *adev); 635 /* get the reference clock */ 636 u32 (*get_xclk)(struct amdgpu_device *adev); 637 /* MM block clocks */ 638 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 639 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 640 /* static power management */ 641 int (*get_pcie_lanes)(struct amdgpu_device *adev); 642 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 643 /* get config memsize register */ 644 u32 (*get_config_memsize)(struct amdgpu_device *adev); 645 /* flush hdp write queue */ 646 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 647 /* invalidate hdp read cache */ 648 void (*invalidate_hdp)(struct amdgpu_device *adev, 649 struct amdgpu_ring *ring); 650 /* check if the asic needs a full reset of if soft reset will work */ 651 bool (*need_full_reset)(struct amdgpu_device *adev); 652 }; 653 654 /* 655 * IOCTL. 656 */ 657 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 658 struct drm_file *filp); 659 660 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 661 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *filp); 663 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 664 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 665 struct drm_file *filp); 666 667 /* VRAM scratch page for HDP bug, default vram page */ 668 struct amdgpu_vram_scratch { 669 struct amdgpu_bo *robj; 670 volatile uint32_t *ptr; 671 u64 gpu_addr; 672 }; 673 674 /* 675 * ACPI 676 */ 677 struct amdgpu_atcs_functions { 678 bool get_ext_state; 679 bool pcie_perf_req; 680 bool pcie_dev_rdy; 681 bool pcie_bus_width; 682 }; 683 684 struct amdgpu_atcs { 685 struct amdgpu_atcs_functions functions; 686 }; 687 688 /* 689 * Firmware VRAM reservation 690 */ 691 struct amdgpu_fw_vram_usage { 692 u64 start_offset; 693 u64 size; 694 struct amdgpu_bo *reserved_bo; 695 void *va; 696 }; 697 698 /* 699 * CGS 700 */ 701 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 702 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 703 704 /* 705 * Core structure, functions and helpers. 706 */ 707 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 708 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 709 710 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 711 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 712 713 714 /* 715 * amdgpu nbio functions 716 * 717 */ 718 struct nbio_hdp_flush_reg { 719 u32 ref_and_mask_cp0; 720 u32 ref_and_mask_cp1; 721 u32 ref_and_mask_cp2; 722 u32 ref_and_mask_cp3; 723 u32 ref_and_mask_cp4; 724 u32 ref_and_mask_cp5; 725 u32 ref_and_mask_cp6; 726 u32 ref_and_mask_cp7; 727 u32 ref_and_mask_cp8; 728 u32 ref_and_mask_cp9; 729 u32 ref_and_mask_sdma0; 730 u32 ref_and_mask_sdma1; 731 }; 732 733 struct amdgpu_nbio_funcs { 734 const struct nbio_hdp_flush_reg *hdp_flush_reg; 735 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 736 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 737 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 738 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 739 u32 (*get_rev_id)(struct amdgpu_device *adev); 740 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 741 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 742 u32 (*get_memsize)(struct amdgpu_device *adev); 743 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 744 bool use_doorbell, int doorbell_index); 745 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 746 bool enable); 747 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 748 bool enable); 749 void (*ih_doorbell_range)(struct amdgpu_device *adev, 750 bool use_doorbell, int doorbell_index); 751 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 752 bool enable); 753 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 754 bool enable); 755 void (*get_clockgating_state)(struct amdgpu_device *adev, 756 u32 *flags); 757 void (*ih_control)(struct amdgpu_device *adev); 758 void (*init_registers)(struct amdgpu_device *adev); 759 void (*detect_hw_virt)(struct amdgpu_device *adev); 760 }; 761 762 struct amdgpu_df_funcs { 763 void (*init)(struct amdgpu_device *adev); 764 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 765 bool enable); 766 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 767 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 768 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 769 bool enable); 770 void (*get_clockgating_state)(struct amdgpu_device *adev, 771 u32 *flags); 772 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 773 bool enable); 774 }; 775 /* Define the HW IP blocks will be used in driver , add more if necessary */ 776 enum amd_hw_ip_block_type { 777 GC_HWIP = 1, 778 HDP_HWIP, 779 SDMA0_HWIP, 780 SDMA1_HWIP, 781 MMHUB_HWIP, 782 ATHUB_HWIP, 783 NBIO_HWIP, 784 MP0_HWIP, 785 MP1_HWIP, 786 UVD_HWIP, 787 VCN_HWIP = UVD_HWIP, 788 VCE_HWIP, 789 DF_HWIP, 790 DCE_HWIP, 791 OSSSYS_HWIP, 792 SMUIO_HWIP, 793 PWR_HWIP, 794 NBIF_HWIP, 795 THM_HWIP, 796 CLK_HWIP, 797 MAX_HWIP 798 }; 799 800 #define HWIP_MAX_INSTANCE 6 801 802 struct amd_powerplay { 803 void *pp_handle; 804 const struct amd_pm_funcs *pp_funcs; 805 uint32_t pp_feature; 806 }; 807 808 #define AMDGPU_RESET_MAGIC_NUM 64 809 struct amdgpu_device { 810 struct device *dev; 811 struct drm_device *ddev; 812 struct pci_dev *pdev; 813 814 #ifdef CONFIG_DRM_AMD_ACP 815 struct amdgpu_acp acp; 816 #endif 817 818 /* ASIC */ 819 enum amd_asic_type asic_type; 820 uint32_t family; 821 uint32_t rev_id; 822 uint32_t external_rev_id; 823 unsigned long flags; 824 int usec_timeout; 825 const struct amdgpu_asic_funcs *asic_funcs; 826 bool shutdown; 827 bool need_dma32; 828 bool need_swiotlb; 829 bool accel_working; 830 struct work_struct reset_work; 831 struct notifier_block acpi_nb; 832 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 833 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 834 unsigned debugfs_count; 835 #if defined(CONFIG_DEBUG_FS) 836 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 837 #endif 838 struct amdgpu_atif *atif; 839 struct amdgpu_atcs atcs; 840 struct mutex srbm_mutex; 841 /* GRBM index mutex. Protects concurrent access to GRBM index */ 842 struct mutex grbm_idx_mutex; 843 struct dev_pm_domain vga_pm_domain; 844 bool have_disp_power_ref; 845 846 /* BIOS */ 847 bool is_atom_fw; 848 uint8_t *bios; 849 uint32_t bios_size; 850 struct amdgpu_bo *stolen_vga_memory; 851 uint32_t bios_scratch_reg_offset; 852 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 853 854 /* Register/doorbell mmio */ 855 resource_size_t rmmio_base; 856 resource_size_t rmmio_size; 857 void __iomem *rmmio; 858 /* protects concurrent MM_INDEX/DATA based register access */ 859 spinlock_t mmio_idx_lock; 860 /* protects concurrent SMC based register access */ 861 spinlock_t smc_idx_lock; 862 amdgpu_rreg_t smc_rreg; 863 amdgpu_wreg_t smc_wreg; 864 /* protects concurrent PCIE register access */ 865 spinlock_t pcie_idx_lock; 866 amdgpu_rreg_t pcie_rreg; 867 amdgpu_wreg_t pcie_wreg; 868 amdgpu_rreg_t pciep_rreg; 869 amdgpu_wreg_t pciep_wreg; 870 /* protects concurrent UVD register access */ 871 spinlock_t uvd_ctx_idx_lock; 872 amdgpu_rreg_t uvd_ctx_rreg; 873 amdgpu_wreg_t uvd_ctx_wreg; 874 /* protects concurrent DIDT register access */ 875 spinlock_t didt_idx_lock; 876 amdgpu_rreg_t didt_rreg; 877 amdgpu_wreg_t didt_wreg; 878 /* protects concurrent gc_cac register access */ 879 spinlock_t gc_cac_idx_lock; 880 amdgpu_rreg_t gc_cac_rreg; 881 amdgpu_wreg_t gc_cac_wreg; 882 /* protects concurrent se_cac register access */ 883 spinlock_t se_cac_idx_lock; 884 amdgpu_rreg_t se_cac_rreg; 885 amdgpu_wreg_t se_cac_wreg; 886 /* protects concurrent ENDPOINT (audio) register access */ 887 spinlock_t audio_endpt_idx_lock; 888 amdgpu_block_rreg_t audio_endpt_rreg; 889 amdgpu_block_wreg_t audio_endpt_wreg; 890 void __iomem *rio_mem; 891 resource_size_t rio_mem_size; 892 struct amdgpu_doorbell doorbell; 893 894 /* clock/pll info */ 895 struct amdgpu_clock clock; 896 897 /* MC */ 898 struct amdgpu_gmc gmc; 899 struct amdgpu_gart gart; 900 dma_addr_t dummy_page_addr; 901 struct amdgpu_vm_manager vm_manager; 902 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 903 904 /* memory management */ 905 struct amdgpu_mman mman; 906 struct amdgpu_vram_scratch vram_scratch; 907 struct amdgpu_wb wb; 908 atomic64_t num_bytes_moved; 909 atomic64_t num_evictions; 910 atomic64_t num_vram_cpu_page_faults; 911 atomic_t gpu_reset_counter; 912 atomic_t vram_lost_counter; 913 914 /* data for buffer migration throttling */ 915 struct { 916 spinlock_t lock; 917 s64 last_update_us; 918 s64 accum_us; /* accumulated microseconds */ 919 s64 accum_us_vis; /* for visible VRAM */ 920 u32 log2_max_MBps; 921 } mm_stats; 922 923 /* display */ 924 bool enable_virtual_display; 925 struct amdgpu_mode_info mode_info; 926 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 927 struct work_struct hotplug_work; 928 struct amdgpu_irq_src crtc_irq; 929 struct amdgpu_irq_src pageflip_irq; 930 struct amdgpu_irq_src hpd_irq; 931 932 /* rings */ 933 u64 fence_context; 934 unsigned num_rings; 935 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 936 bool ib_pool_ready; 937 struct amdgpu_sa_manager ring_tmp_bo; 938 939 /* interrupts */ 940 struct amdgpu_irq irq; 941 942 /* powerplay */ 943 struct amd_powerplay powerplay; 944 bool pp_force_state_enabled; 945 946 /* dpm */ 947 struct amdgpu_pm pm; 948 u32 cg_flags; 949 u32 pg_flags; 950 951 /* amdgpu smumgr */ 952 struct amdgpu_smumgr smu; 953 954 /* gfx */ 955 struct amdgpu_gfx gfx; 956 957 /* sdma */ 958 struct amdgpu_sdma sdma; 959 960 /* uvd */ 961 struct amdgpu_uvd uvd; 962 963 /* vce */ 964 struct amdgpu_vce vce; 965 966 /* vcn */ 967 struct amdgpu_vcn vcn; 968 969 /* firmwares */ 970 struct amdgpu_firmware firmware; 971 972 /* PSP */ 973 struct psp_context psp; 974 975 /* GDS */ 976 struct amdgpu_gds gds; 977 978 /* display related functionality */ 979 struct amdgpu_display_manager dm; 980 981 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 982 int num_ip_blocks; 983 struct mutex mn_lock; 984 DECLARE_HASHTABLE(mn_hash, 7); 985 986 /* tracking pinned memory */ 987 atomic64_t vram_pin_size; 988 atomic64_t visible_pin_size; 989 atomic64_t gart_pin_size; 990 991 /* amdkfd interface */ 992 struct kfd_dev *kfd; 993 994 /* soc15 register offset based on ip, instance and segment */ 995 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 996 997 const struct amdgpu_nbio_funcs *nbio_funcs; 998 const struct amdgpu_df_funcs *df_funcs; 999 1000 /* delayed work_func for deferring clockgating during resume */ 1001 struct delayed_work late_init_work; 1002 1003 struct amdgpu_virt virt; 1004 /* firmware VRAM reservation */ 1005 struct amdgpu_fw_vram_usage fw_vram_usage; 1006 1007 /* link all shadow bo */ 1008 struct list_head shadow_list; 1009 struct mutex shadow_list_lock; 1010 /* keep an lru list of rings by HW IP */ 1011 struct list_head ring_lru_list; 1012 spinlock_t ring_lru_list_lock; 1013 1014 /* record hw reset is performed */ 1015 bool has_hw_reset; 1016 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1017 1018 /* record last mm index being written through WREG32*/ 1019 unsigned long last_mm_index; 1020 bool in_gpu_reset; 1021 struct mutex lock_reset; 1022 }; 1023 1024 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1025 { 1026 return container_of(bdev, struct amdgpu_device, mman.bdev); 1027 } 1028 1029 int amdgpu_device_init(struct amdgpu_device *adev, 1030 struct drm_device *ddev, 1031 struct pci_dev *pdev, 1032 uint32_t flags); 1033 void amdgpu_device_fini(struct amdgpu_device *adev); 1034 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1035 1036 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1037 uint32_t acc_flags); 1038 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1039 uint32_t acc_flags); 1040 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1041 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1042 1043 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1044 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1045 1046 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1047 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1048 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1049 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1050 1051 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1052 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1053 1054 int emu_soc_asic_init(struct amdgpu_device *adev); 1055 1056 /* 1057 * Registers read & write functions. 1058 */ 1059 1060 #define AMDGPU_REGS_IDX (1<<0) 1061 #define AMDGPU_REGS_NO_KIQ (1<<1) 1062 1063 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1064 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1065 1066 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1067 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1068 1069 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1070 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1071 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1072 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1073 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1074 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1075 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1076 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1077 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1078 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1079 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1080 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1081 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1082 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1084 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1085 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1086 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1087 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1088 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1089 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1090 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1091 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1092 #define WREG32_P(reg, val, mask) \ 1093 do { \ 1094 uint32_t tmp_ = RREG32(reg); \ 1095 tmp_ &= (mask); \ 1096 tmp_ |= ((val) & ~(mask)); \ 1097 WREG32(reg, tmp_); \ 1098 } while (0) 1099 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1100 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1101 #define WREG32_PLL_P(reg, val, mask) \ 1102 do { \ 1103 uint32_t tmp_ = RREG32_PLL(reg); \ 1104 tmp_ &= (mask); \ 1105 tmp_ |= ((val) & ~(mask)); \ 1106 WREG32_PLL(reg, tmp_); \ 1107 } while (0) 1108 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1109 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1110 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1111 1112 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1113 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1114 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1115 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1116 1117 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1118 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1119 1120 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1121 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1122 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1123 1124 #define REG_GET_FIELD(value, reg, field) \ 1125 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1126 1127 #define WREG32_FIELD(reg, field, val) \ 1128 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1129 1130 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1131 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1132 1133 /* 1134 * BIOS helpers. 1135 */ 1136 #define RBIOS8(i) (adev->bios[i]) 1137 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1138 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1139 1140 /* 1141 * ASICs macro. 1142 */ 1143 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1144 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1145 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1146 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1147 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1148 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1149 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1150 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1151 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1152 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1153 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1154 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1155 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1156 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1157 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1158 1159 /* Common functions */ 1160 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1161 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1162 struct amdgpu_job* job); 1163 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1164 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1165 1166 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1167 u64 num_vis_bytes); 1168 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1169 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1170 const u32 *registers, 1171 const u32 array_size); 1172 1173 bool amdgpu_device_is_px(struct drm_device *dev); 1174 /* atpx handler */ 1175 #if defined(CONFIG_VGA_SWITCHEROO) 1176 void amdgpu_register_atpx_handler(void); 1177 void amdgpu_unregister_atpx_handler(void); 1178 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1179 bool amdgpu_is_atpx_hybrid(void); 1180 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1181 bool amdgpu_has_atpx(void); 1182 #else 1183 static inline void amdgpu_register_atpx_handler(void) {} 1184 static inline void amdgpu_unregister_atpx_handler(void) {} 1185 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1186 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1187 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1188 static inline bool amdgpu_has_atpx(void) { return false; } 1189 #endif 1190 1191 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1192 void *amdgpu_atpx_get_dhandle(void); 1193 #else 1194 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1195 #endif 1196 1197 /* 1198 * KMS 1199 */ 1200 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1201 extern const int amdgpu_max_kms_ioctl; 1202 1203 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1204 void amdgpu_driver_unload_kms(struct drm_device *dev); 1205 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1206 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1207 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1208 struct drm_file *file_priv); 1209 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1210 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1211 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1212 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1213 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1214 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1215 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1216 unsigned long arg); 1217 1218 1219 /* 1220 * functions used by amdgpu_xgmi.c 1221 */ 1222 int amdgpu_xgmi_add_device(struct amdgpu_device *adev); 1223 1224 /* 1225 * functions used by amdgpu_encoder.c 1226 */ 1227 struct amdgpu_afmt_acr { 1228 u32 clock; 1229 1230 int n_32khz; 1231 int cts_32khz; 1232 1233 int n_44_1khz; 1234 int cts_44_1khz; 1235 1236 int n_48khz; 1237 int cts_48khz; 1238 1239 }; 1240 1241 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1242 1243 /* amdgpu_acpi.c */ 1244 #if defined(CONFIG_ACPI) 1245 int amdgpu_acpi_init(struct amdgpu_device *adev); 1246 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1247 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1248 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1249 u8 perf_req, bool advertise); 1250 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1251 #else 1252 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1253 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1254 #endif 1255 1256 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1257 uint64_t addr, struct amdgpu_bo **bo, 1258 struct amdgpu_bo_va_mapping **mapping); 1259 1260 #if defined(CONFIG_DRM_AMD_DC) 1261 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1262 #else 1263 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1264 #endif 1265 1266 #include "amdgpu_object.h" 1267 #endif 1268