1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_ttm.h" 55 #include "amdgpu_gds.h" 56 #include "amdgpu_sync.h" 57 #include "amdgpu_ring.h" 58 #include "amdgpu_vm.h" 59 #include "amd_powerplay.h" 60 #include "amdgpu_dpm.h" 61 #include "amdgpu_acp.h" 62 63 #include "gpu_scheduler.h" 64 #include "amdgpu_virt.h" 65 66 /* 67 * Modules parameters. 68 */ 69 extern int amdgpu_modeset; 70 extern int amdgpu_vram_limit; 71 extern int amdgpu_gart_size; 72 extern int amdgpu_moverate; 73 extern int amdgpu_benchmarking; 74 extern int amdgpu_testing; 75 extern int amdgpu_audio; 76 extern int amdgpu_disp_priority; 77 extern int amdgpu_hw_i2c; 78 extern int amdgpu_pcie_gen2; 79 extern int amdgpu_msi; 80 extern int amdgpu_lockup_timeout; 81 extern int amdgpu_dpm; 82 extern int amdgpu_smc_load_fw; 83 extern int amdgpu_aspm; 84 extern int amdgpu_runtime_pm; 85 extern unsigned amdgpu_ip_block_mask; 86 extern int amdgpu_bapm; 87 extern int amdgpu_deep_color; 88 extern int amdgpu_vm_size; 89 extern int amdgpu_vm_block_size; 90 extern int amdgpu_vm_fault_stop; 91 extern int amdgpu_vm_debug; 92 extern int amdgpu_sched_jobs; 93 extern int amdgpu_sched_hw_submission; 94 extern int amdgpu_no_evict; 95 extern int amdgpu_direct_gma_size; 96 extern unsigned amdgpu_pcie_gen_cap; 97 extern unsigned amdgpu_pcie_lane_cap; 98 extern unsigned amdgpu_cg_mask; 99 extern unsigned amdgpu_pg_mask; 100 extern char *amdgpu_disable_cu; 101 extern char *amdgpu_virtual_display; 102 extern unsigned amdgpu_pp_feature_mask; 103 extern int amdgpu_vram_page_split; 104 105 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 106 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 107 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 108 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 109 #define AMDGPU_IB_POOL_SIZE 16 110 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 111 #define AMDGPUFB_CONN_LIMIT 4 112 #define AMDGPU_BIOS_NUM_SCRATCH 8 113 114 /* max number of IP instances */ 115 #define AMDGPU_MAX_SDMA_INSTANCES 2 116 117 /* hardcode that limit for now */ 118 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 119 120 /* hard reset data */ 121 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 122 123 /* reset flags */ 124 #define AMDGPU_RESET_GFX (1 << 0) 125 #define AMDGPU_RESET_COMPUTE (1 << 1) 126 #define AMDGPU_RESET_DMA (1 << 2) 127 #define AMDGPU_RESET_CP (1 << 3) 128 #define AMDGPU_RESET_GRBM (1 << 4) 129 #define AMDGPU_RESET_DMA1 (1 << 5) 130 #define AMDGPU_RESET_RLC (1 << 6) 131 #define AMDGPU_RESET_SEM (1 << 7) 132 #define AMDGPU_RESET_IH (1 << 8) 133 #define AMDGPU_RESET_VMC (1 << 9) 134 #define AMDGPU_RESET_MC (1 << 10) 135 #define AMDGPU_RESET_DISPLAY (1 << 11) 136 #define AMDGPU_RESET_UVD (1 << 12) 137 #define AMDGPU_RESET_VCE (1 << 13) 138 #define AMDGPU_RESET_VCE1 (1 << 14) 139 140 /* GFX current status */ 141 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 142 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 143 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 144 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 145 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 146 147 /* max cursor sizes (in pixels) */ 148 #define CIK_CURSOR_WIDTH 128 149 #define CIK_CURSOR_HEIGHT 128 150 151 struct amdgpu_device; 152 struct amdgpu_ib; 153 struct amdgpu_cs_parser; 154 struct amdgpu_job; 155 struct amdgpu_irq_src; 156 struct amdgpu_fpriv; 157 158 enum amdgpu_cp_irq { 159 AMDGPU_CP_IRQ_GFX_EOP = 0, 160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 168 169 AMDGPU_CP_IRQ_LAST 170 }; 171 172 enum amdgpu_sdma_irq { 173 AMDGPU_SDMA_IRQ_TRAP0 = 0, 174 AMDGPU_SDMA_IRQ_TRAP1, 175 176 AMDGPU_SDMA_IRQ_LAST 177 }; 178 179 enum amdgpu_thermal_irq { 180 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 181 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 182 183 AMDGPU_THERMAL_IRQ_LAST 184 }; 185 186 enum amdgpu_kiq_irq { 187 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 188 AMDGPU_CP_KIQ_IRQ_LAST 189 }; 190 191 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 192 enum amd_ip_block_type block_type, 193 enum amd_clockgating_state state); 194 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 195 enum amd_ip_block_type block_type, 196 enum amd_powergating_state state); 197 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 198 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 199 enum amd_ip_block_type block_type); 200 bool amdgpu_is_idle(struct amdgpu_device *adev, 201 enum amd_ip_block_type block_type); 202 203 #define AMDGPU_MAX_IP_NUM 16 204 205 struct amdgpu_ip_block_status { 206 bool valid; 207 bool sw; 208 bool hw; 209 bool late_initialized; 210 bool hang; 211 }; 212 213 struct amdgpu_ip_block_version { 214 const enum amd_ip_block_type type; 215 const u32 major; 216 const u32 minor; 217 const u32 rev; 218 const struct amd_ip_funcs *funcs; 219 }; 220 221 struct amdgpu_ip_block { 222 struct amdgpu_ip_block_status status; 223 const struct amdgpu_ip_block_version *version; 224 }; 225 226 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 227 enum amd_ip_block_type type, 228 u32 major, u32 minor); 229 230 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 231 enum amd_ip_block_type type); 232 233 int amdgpu_ip_block_add(struct amdgpu_device *adev, 234 const struct amdgpu_ip_block_version *ip_block_version); 235 236 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 237 struct amdgpu_buffer_funcs { 238 /* maximum bytes in a single operation */ 239 uint32_t copy_max_bytes; 240 241 /* number of dw to reserve per operation */ 242 unsigned copy_num_dw; 243 244 /* used for buffer migration */ 245 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 246 /* src addr in bytes */ 247 uint64_t src_offset, 248 /* dst addr in bytes */ 249 uint64_t dst_offset, 250 /* number of byte to transfer */ 251 uint32_t byte_count); 252 253 /* maximum bytes in a single operation */ 254 uint32_t fill_max_bytes; 255 256 /* number of dw to reserve per operation */ 257 unsigned fill_num_dw; 258 259 /* used for buffer clearing */ 260 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 261 /* value to write to memory */ 262 uint32_t src_data, 263 /* dst addr in bytes */ 264 uint64_t dst_offset, 265 /* number of byte to fill */ 266 uint32_t byte_count); 267 }; 268 269 /* provided by hw blocks that can write ptes, e.g., sdma */ 270 struct amdgpu_vm_pte_funcs { 271 /* copy pte entries from GART */ 272 void (*copy_pte)(struct amdgpu_ib *ib, 273 uint64_t pe, uint64_t src, 274 unsigned count); 275 /* write pte one entry at a time with addr mapping */ 276 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 277 uint64_t value, unsigned count, 278 uint32_t incr); 279 /* for linear pte/pde updates without addr mapping */ 280 void (*set_pte_pde)(struct amdgpu_ib *ib, 281 uint64_t pe, 282 uint64_t addr, unsigned count, 283 uint32_t incr, uint32_t flags); 284 }; 285 286 /* provided by the gmc block */ 287 struct amdgpu_gart_funcs { 288 /* flush the vm tlb via mmio */ 289 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 290 uint32_t vmid); 291 /* write pte/pde updates using the cpu */ 292 int (*set_pte_pde)(struct amdgpu_device *adev, 293 void *cpu_pt_addr, /* cpu addr of page table */ 294 uint32_t gpu_page_idx, /* pte/pde to update */ 295 uint64_t addr, /* addr to write into pte/pde */ 296 uint32_t flags); /* access flags */ 297 /* enable/disable PRT support */ 298 void (*set_prt)(struct amdgpu_device *adev, bool enable); 299 }; 300 301 /* provided by the ih block */ 302 struct amdgpu_ih_funcs { 303 /* ring read/write ptr handling, called from interrupt context */ 304 u32 (*get_wptr)(struct amdgpu_device *adev); 305 void (*decode_iv)(struct amdgpu_device *adev, 306 struct amdgpu_iv_entry *entry); 307 void (*set_rptr)(struct amdgpu_device *adev); 308 }; 309 310 /* 311 * BIOS. 312 */ 313 bool amdgpu_get_bios(struct amdgpu_device *adev); 314 bool amdgpu_read_bios(struct amdgpu_device *adev); 315 316 /* 317 * Dummy page 318 */ 319 struct amdgpu_dummy_page { 320 struct page *page; 321 dma_addr_t addr; 322 }; 323 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 324 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 325 326 327 /* 328 * Clocks 329 */ 330 331 #define AMDGPU_MAX_PPLL 3 332 333 struct amdgpu_clock { 334 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 335 struct amdgpu_pll spll; 336 struct amdgpu_pll mpll; 337 /* 10 Khz units */ 338 uint32_t default_mclk; 339 uint32_t default_sclk; 340 uint32_t default_dispclk; 341 uint32_t current_dispclk; 342 uint32_t dp_extclk; 343 uint32_t max_pixel_clock; 344 }; 345 346 /* 347 * BO. 348 */ 349 struct amdgpu_bo_list_entry { 350 struct amdgpu_bo *robj; 351 struct ttm_validate_buffer tv; 352 struct amdgpu_bo_va *bo_va; 353 uint32_t priority; 354 struct page **user_pages; 355 int user_invalidated; 356 }; 357 358 struct amdgpu_bo_va_mapping { 359 struct list_head list; 360 struct interval_tree_node it; 361 uint64_t offset; 362 uint64_t flags; 363 }; 364 365 /* bo virtual addresses in a specific vm */ 366 struct amdgpu_bo_va { 367 /* protected by bo being reserved */ 368 struct list_head bo_list; 369 struct dma_fence *last_pt_update; 370 unsigned ref_count; 371 372 /* protected by vm mutex and spinlock */ 373 struct list_head vm_status; 374 375 /* mappings for this bo_va */ 376 struct list_head invalids; 377 struct list_head valids; 378 379 /* constant after initialization */ 380 struct amdgpu_vm *vm; 381 struct amdgpu_bo *bo; 382 }; 383 384 #define AMDGPU_GEM_DOMAIN_MAX 0x3 385 386 struct amdgpu_bo { 387 /* Protected by tbo.reserved */ 388 u32 prefered_domains; 389 u32 allowed_domains; 390 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 391 struct ttm_placement placement; 392 struct ttm_buffer_object tbo; 393 struct ttm_bo_kmap_obj kmap; 394 u64 flags; 395 unsigned pin_count; 396 void *kptr; 397 u64 tiling_flags; 398 u64 metadata_flags; 399 void *metadata; 400 u32 metadata_size; 401 unsigned prime_shared_count; 402 /* list of all virtual address to which this bo 403 * is associated to 404 */ 405 struct list_head va; 406 /* Constant after initialization */ 407 struct drm_gem_object gem_base; 408 struct amdgpu_bo *parent; 409 struct amdgpu_bo *shadow; 410 411 struct ttm_bo_kmap_obj dma_buf_vmap; 412 struct amdgpu_mn *mn; 413 struct list_head mn_list; 414 struct list_head shadow_list; 415 }; 416 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 417 418 void amdgpu_gem_object_free(struct drm_gem_object *obj); 419 int amdgpu_gem_object_open(struct drm_gem_object *obj, 420 struct drm_file *file_priv); 421 void amdgpu_gem_object_close(struct drm_gem_object *obj, 422 struct drm_file *file_priv); 423 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 424 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 425 struct drm_gem_object * 426 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 427 struct dma_buf_attachment *attach, 428 struct sg_table *sg); 429 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 430 struct drm_gem_object *gobj, 431 int flags); 432 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 433 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 434 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 435 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 436 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 437 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 438 439 /* sub-allocation manager, it has to be protected by another lock. 440 * By conception this is an helper for other part of the driver 441 * like the indirect buffer or semaphore, which both have their 442 * locking. 443 * 444 * Principe is simple, we keep a list of sub allocation in offset 445 * order (first entry has offset == 0, last entry has the highest 446 * offset). 447 * 448 * When allocating new object we first check if there is room at 449 * the end total_size - (last_object_offset + last_object_size) >= 450 * alloc_size. If so we allocate new object there. 451 * 452 * When there is not enough room at the end, we start waiting for 453 * each sub object until we reach object_offset+object_size >= 454 * alloc_size, this object then become the sub object we return. 455 * 456 * Alignment can't be bigger than page size. 457 * 458 * Hole are not considered for allocation to keep things simple. 459 * Assumption is that there won't be hole (all object on same 460 * alignment). 461 */ 462 463 #define AMDGPU_SA_NUM_FENCE_LISTS 32 464 465 struct amdgpu_sa_manager { 466 wait_queue_head_t wq; 467 struct amdgpu_bo *bo; 468 struct list_head *hole; 469 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 470 struct list_head olist; 471 unsigned size; 472 uint64_t gpu_addr; 473 void *cpu_ptr; 474 uint32_t domain; 475 uint32_t align; 476 }; 477 478 /* sub-allocation buffer */ 479 struct amdgpu_sa_bo { 480 struct list_head olist; 481 struct list_head flist; 482 struct amdgpu_sa_manager *manager; 483 unsigned soffset; 484 unsigned eoffset; 485 struct dma_fence *fence; 486 }; 487 488 /* 489 * GEM objects. 490 */ 491 void amdgpu_gem_force_release(struct amdgpu_device *adev); 492 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 493 int alignment, u32 initial_domain, 494 u64 flags, bool kernel, 495 struct drm_gem_object **obj); 496 497 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 498 struct drm_device *dev, 499 struct drm_mode_create_dumb *args); 500 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 501 struct drm_device *dev, 502 uint32_t handle, uint64_t *offset_p); 503 int amdgpu_fence_slab_init(void); 504 void amdgpu_fence_slab_fini(void); 505 506 /* 507 * GART structures, functions & helpers 508 */ 509 struct amdgpu_mc; 510 511 #define AMDGPU_GPU_PAGE_SIZE 4096 512 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 513 #define AMDGPU_GPU_PAGE_SHIFT 12 514 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 515 516 struct amdgpu_gart { 517 dma_addr_t table_addr; 518 struct amdgpu_bo *robj; 519 void *ptr; 520 unsigned num_gpu_pages; 521 unsigned num_cpu_pages; 522 unsigned table_size; 523 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 524 struct page **pages; 525 #endif 526 bool ready; 527 const struct amdgpu_gart_funcs *gart_funcs; 528 }; 529 530 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 531 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 532 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 533 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 534 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 535 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 536 int amdgpu_gart_init(struct amdgpu_device *adev); 537 void amdgpu_gart_fini(struct amdgpu_device *adev); 538 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 539 int pages); 540 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 541 int pages, struct page **pagelist, 542 dma_addr_t *dma_addr, uint32_t flags); 543 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 544 545 /* 546 * GPU MC structures, functions & helpers 547 */ 548 struct amdgpu_mc { 549 resource_size_t aper_size; 550 resource_size_t aper_base; 551 resource_size_t agp_base; 552 /* for some chips with <= 32MB we need to lie 553 * about vram size near mc fb location */ 554 u64 mc_vram_size; 555 u64 visible_vram_size; 556 u64 gtt_size; 557 u64 gtt_start; 558 u64 gtt_end; 559 u64 vram_start; 560 u64 vram_end; 561 unsigned vram_width; 562 u64 real_vram_size; 563 int vram_mtrr; 564 u64 gtt_base_align; 565 u64 mc_mask; 566 const struct firmware *fw; /* MC firmware */ 567 uint32_t fw_version; 568 struct amdgpu_irq_src vm_fault; 569 uint32_t vram_type; 570 uint32_t srbm_soft_reset; 571 struct amdgpu_mode_mc_save save; 572 bool prt_warning; 573 }; 574 575 /* 576 * GPU doorbell structures, functions & helpers 577 */ 578 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 579 { 580 AMDGPU_DOORBELL_KIQ = 0x000, 581 AMDGPU_DOORBELL_HIQ = 0x001, 582 AMDGPU_DOORBELL_DIQ = 0x002, 583 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 584 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 585 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 586 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 587 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 588 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 589 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 590 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 591 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 592 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 593 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 594 AMDGPU_DOORBELL_IH = 0x1E8, 595 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 596 AMDGPU_DOORBELL_INVALID = 0xFFFF 597 } AMDGPU_DOORBELL_ASSIGNMENT; 598 599 struct amdgpu_doorbell { 600 /* doorbell mmio */ 601 resource_size_t base; 602 resource_size_t size; 603 u32 __iomem *ptr; 604 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 605 }; 606 607 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 608 phys_addr_t *aperture_base, 609 size_t *aperture_size, 610 size_t *start_offset); 611 612 /* 613 * IRQS. 614 */ 615 616 struct amdgpu_flip_work { 617 struct delayed_work flip_work; 618 struct work_struct unpin_work; 619 struct amdgpu_device *adev; 620 int crtc_id; 621 u32 target_vblank; 622 uint64_t base; 623 struct drm_pending_vblank_event *event; 624 struct amdgpu_bo *old_abo; 625 struct dma_fence *excl; 626 unsigned shared_count; 627 struct dma_fence **shared; 628 struct dma_fence_cb cb; 629 bool async; 630 }; 631 632 633 /* 634 * CP & rings. 635 */ 636 637 struct amdgpu_ib { 638 struct amdgpu_sa_bo *sa_bo; 639 uint32_t length_dw; 640 uint64_t gpu_addr; 641 uint32_t *ptr; 642 uint32_t flags; 643 }; 644 645 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 646 647 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 648 struct amdgpu_job **job, struct amdgpu_vm *vm); 649 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 650 struct amdgpu_job **job); 651 652 void amdgpu_job_free_resources(struct amdgpu_job *job); 653 void amdgpu_job_free(struct amdgpu_job *job); 654 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 655 struct amd_sched_entity *entity, void *owner, 656 struct dma_fence **f); 657 658 /* 659 * context related structures 660 */ 661 662 struct amdgpu_ctx_ring { 663 uint64_t sequence; 664 struct dma_fence **fences; 665 struct amd_sched_entity entity; 666 }; 667 668 struct amdgpu_ctx { 669 struct kref refcount; 670 struct amdgpu_device *adev; 671 unsigned reset_counter; 672 spinlock_t ring_lock; 673 struct dma_fence **fences; 674 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 675 bool preamble_presented; 676 }; 677 678 struct amdgpu_ctx_mgr { 679 struct amdgpu_device *adev; 680 struct mutex lock; 681 /* protected by lock */ 682 struct idr ctx_handles; 683 }; 684 685 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 686 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 687 688 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 689 struct dma_fence *fence); 690 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 691 struct amdgpu_ring *ring, uint64_t seq); 692 693 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 694 struct drm_file *filp); 695 696 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 697 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 698 699 /* 700 * file private structure 701 */ 702 703 struct amdgpu_fpriv { 704 struct amdgpu_vm vm; 705 struct amdgpu_bo_va *prt_va; 706 struct mutex bo_list_lock; 707 struct idr bo_list_handles; 708 struct amdgpu_ctx_mgr ctx_mgr; 709 }; 710 711 /* 712 * residency list 713 */ 714 715 struct amdgpu_bo_list { 716 struct mutex lock; 717 struct amdgpu_bo *gds_obj; 718 struct amdgpu_bo *gws_obj; 719 struct amdgpu_bo *oa_obj; 720 unsigned first_userptr; 721 unsigned num_entries; 722 struct amdgpu_bo_list_entry *array; 723 }; 724 725 struct amdgpu_bo_list * 726 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 727 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 728 struct list_head *validated); 729 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 730 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 731 732 /* 733 * GFX stuff 734 */ 735 #include "clearstate_defs.h" 736 737 struct amdgpu_rlc_funcs { 738 void (*enter_safe_mode)(struct amdgpu_device *adev); 739 void (*exit_safe_mode)(struct amdgpu_device *adev); 740 }; 741 742 struct amdgpu_rlc { 743 /* for power gating */ 744 struct amdgpu_bo *save_restore_obj; 745 uint64_t save_restore_gpu_addr; 746 volatile uint32_t *sr_ptr; 747 const u32 *reg_list; 748 u32 reg_list_size; 749 /* for clear state */ 750 struct amdgpu_bo *clear_state_obj; 751 uint64_t clear_state_gpu_addr; 752 volatile uint32_t *cs_ptr; 753 const struct cs_section_def *cs_data; 754 u32 clear_state_size; 755 /* for cp tables */ 756 struct amdgpu_bo *cp_table_obj; 757 uint64_t cp_table_gpu_addr; 758 volatile uint32_t *cp_table_ptr; 759 u32 cp_table_size; 760 761 /* safe mode for updating CG/PG state */ 762 bool in_safe_mode; 763 const struct amdgpu_rlc_funcs *funcs; 764 765 /* for firmware data */ 766 u32 save_and_restore_offset; 767 u32 clear_state_descriptor_offset; 768 u32 avail_scratch_ram_locations; 769 u32 reg_restore_list_size; 770 u32 reg_list_format_start; 771 u32 reg_list_format_separate_start; 772 u32 starting_offsets_start; 773 u32 reg_list_format_size_bytes; 774 u32 reg_list_size_bytes; 775 776 u32 *register_list_format; 777 u32 *register_restore; 778 }; 779 780 struct amdgpu_mec { 781 struct amdgpu_bo *hpd_eop_obj; 782 u64 hpd_eop_gpu_addr; 783 u32 num_pipe; 784 u32 num_mec; 785 u32 num_queue; 786 }; 787 788 struct amdgpu_kiq { 789 u64 eop_gpu_addr; 790 struct amdgpu_bo *eop_obj; 791 struct amdgpu_ring ring; 792 struct amdgpu_irq_src irq; 793 }; 794 795 /* 796 * GPU scratch registers structures, functions & helpers 797 */ 798 struct amdgpu_scratch { 799 unsigned num_reg; 800 uint32_t reg_base; 801 uint32_t free_mask; 802 }; 803 804 /* 805 * GFX configurations 806 */ 807 #define AMDGPU_GFX_MAX_SE 4 808 #define AMDGPU_GFX_MAX_SH_PER_SE 2 809 810 struct amdgpu_rb_config { 811 uint32_t rb_backend_disable; 812 uint32_t user_rb_backend_disable; 813 uint32_t raster_config; 814 uint32_t raster_config_1; 815 }; 816 817 struct amdgpu_gca_config { 818 unsigned max_shader_engines; 819 unsigned max_tile_pipes; 820 unsigned max_cu_per_sh; 821 unsigned max_sh_per_se; 822 unsigned max_backends_per_se; 823 unsigned max_texture_channel_caches; 824 unsigned max_gprs; 825 unsigned max_gs_threads; 826 unsigned max_hw_contexts; 827 unsigned sc_prim_fifo_size_frontend; 828 unsigned sc_prim_fifo_size_backend; 829 unsigned sc_hiz_tile_fifo_size; 830 unsigned sc_earlyz_tile_fifo_size; 831 832 unsigned num_tile_pipes; 833 unsigned backend_enable_mask; 834 unsigned mem_max_burst_length_bytes; 835 unsigned mem_row_size_in_kb; 836 unsigned shader_engine_tile_size; 837 unsigned num_gpus; 838 unsigned multi_gpu_tile_size; 839 unsigned mc_arb_ramcfg; 840 unsigned gb_addr_config; 841 unsigned num_rbs; 842 843 uint32_t tile_mode_array[32]; 844 uint32_t macrotile_mode_array[16]; 845 846 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 847 }; 848 849 struct amdgpu_cu_info { 850 uint32_t number; /* total active CU number */ 851 uint32_t ao_cu_mask; 852 uint32_t bitmap[4][4]; 853 }; 854 855 struct amdgpu_gfx_funcs { 856 /* get the gpu clock counter */ 857 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 858 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 859 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 860 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 861 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 862 }; 863 864 struct amdgpu_gfx { 865 struct mutex gpu_clock_mutex; 866 struct amdgpu_gca_config config; 867 struct amdgpu_rlc rlc; 868 struct amdgpu_mec mec; 869 struct amdgpu_kiq kiq; 870 struct amdgpu_scratch scratch; 871 const struct firmware *me_fw; /* ME firmware */ 872 uint32_t me_fw_version; 873 const struct firmware *pfp_fw; /* PFP firmware */ 874 uint32_t pfp_fw_version; 875 const struct firmware *ce_fw; /* CE firmware */ 876 uint32_t ce_fw_version; 877 const struct firmware *rlc_fw; /* RLC firmware */ 878 uint32_t rlc_fw_version; 879 const struct firmware *mec_fw; /* MEC firmware */ 880 uint32_t mec_fw_version; 881 const struct firmware *mec2_fw; /* MEC2 firmware */ 882 uint32_t mec2_fw_version; 883 uint32_t me_feature_version; 884 uint32_t ce_feature_version; 885 uint32_t pfp_feature_version; 886 uint32_t rlc_feature_version; 887 uint32_t mec_feature_version; 888 uint32_t mec2_feature_version; 889 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 890 unsigned num_gfx_rings; 891 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 892 unsigned num_compute_rings; 893 struct amdgpu_irq_src eop_irq; 894 struct amdgpu_irq_src priv_reg_irq; 895 struct amdgpu_irq_src priv_inst_irq; 896 /* gfx status */ 897 uint32_t gfx_current_status; 898 /* ce ram size*/ 899 unsigned ce_ram_size; 900 struct amdgpu_cu_info cu_info; 901 const struct amdgpu_gfx_funcs *funcs; 902 903 /* reset mask */ 904 uint32_t grbm_soft_reset; 905 uint32_t srbm_soft_reset; 906 }; 907 908 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 909 unsigned size, struct amdgpu_ib *ib); 910 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 911 struct dma_fence *f); 912 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 913 struct amdgpu_ib *ibs, struct amdgpu_job *job, 914 struct dma_fence **f); 915 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 916 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 917 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 918 919 /* 920 * CS. 921 */ 922 struct amdgpu_cs_chunk { 923 uint32_t chunk_id; 924 uint32_t length_dw; 925 void *kdata; 926 }; 927 928 struct amdgpu_cs_parser { 929 struct amdgpu_device *adev; 930 struct drm_file *filp; 931 struct amdgpu_ctx *ctx; 932 933 /* chunks */ 934 unsigned nchunks; 935 struct amdgpu_cs_chunk *chunks; 936 937 /* scheduler job object */ 938 struct amdgpu_job *job; 939 940 /* buffer objects */ 941 struct ww_acquire_ctx ticket; 942 struct amdgpu_bo_list *bo_list; 943 struct amdgpu_bo_list_entry vm_pd; 944 struct list_head validated; 945 struct dma_fence *fence; 946 uint64_t bytes_moved_threshold; 947 uint64_t bytes_moved; 948 struct amdgpu_bo_list_entry *evictable; 949 950 /* user fence */ 951 struct amdgpu_bo_list_entry uf_entry; 952 }; 953 954 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 955 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 956 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 957 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */ 958 959 struct amdgpu_job { 960 struct amd_sched_job base; 961 struct amdgpu_device *adev; 962 struct amdgpu_vm *vm; 963 struct amdgpu_ring *ring; 964 struct amdgpu_sync sync; 965 struct amdgpu_ib *ibs; 966 struct dma_fence *fence; /* the hw fence */ 967 uint32_t preamble_status; 968 uint32_t num_ibs; 969 void *owner; 970 uint64_t fence_ctx; /* the fence_context this job uses */ 971 bool vm_needs_flush; 972 unsigned vm_id; 973 uint64_t vm_pd_addr; 974 uint32_t gds_base, gds_size; 975 uint32_t gws_base, gws_size; 976 uint32_t oa_base, oa_size; 977 978 /* user fence handling */ 979 uint64_t uf_addr; 980 uint64_t uf_sequence; 981 982 }; 983 #define to_amdgpu_job(sched_job) \ 984 container_of((sched_job), struct amdgpu_job, base) 985 986 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 987 uint32_t ib_idx, int idx) 988 { 989 return p->job->ibs[ib_idx].ptr[idx]; 990 } 991 992 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 993 uint32_t ib_idx, int idx, 994 uint32_t value) 995 { 996 p->job->ibs[ib_idx].ptr[idx] = value; 997 } 998 999 /* 1000 * Writeback 1001 */ 1002 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1003 1004 struct amdgpu_wb { 1005 struct amdgpu_bo *wb_obj; 1006 volatile uint32_t *wb; 1007 uint64_t gpu_addr; 1008 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1009 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1010 }; 1011 1012 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1013 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1014 1015 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1016 1017 /* 1018 * UVD 1019 */ 1020 #define AMDGPU_DEFAULT_UVD_HANDLES 10 1021 #define AMDGPU_MAX_UVD_HANDLES 40 1022 #define AMDGPU_UVD_STACK_SIZE (200*1024) 1023 #define AMDGPU_UVD_HEAP_SIZE (256*1024) 1024 #define AMDGPU_UVD_SESSION_SIZE (50*1024) 1025 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1026 1027 struct amdgpu_uvd { 1028 struct amdgpu_bo *vcpu_bo; 1029 void *cpu_addr; 1030 uint64_t gpu_addr; 1031 unsigned fw_version; 1032 void *saved_bo; 1033 unsigned max_handles; 1034 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1035 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1036 struct delayed_work idle_work; 1037 const struct firmware *fw; /* UVD firmware */ 1038 struct amdgpu_ring ring; 1039 struct amdgpu_irq_src irq; 1040 bool address_64_bit; 1041 bool use_ctx_buf; 1042 struct amd_sched_entity entity; 1043 uint32_t srbm_soft_reset; 1044 }; 1045 1046 /* 1047 * VCE 1048 */ 1049 #define AMDGPU_MAX_VCE_HANDLES 16 1050 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1051 1052 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1053 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1054 1055 struct amdgpu_vce { 1056 struct amdgpu_bo *vcpu_bo; 1057 uint64_t gpu_addr; 1058 unsigned fw_version; 1059 unsigned fb_version; 1060 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1061 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1062 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1063 struct delayed_work idle_work; 1064 struct mutex idle_mutex; 1065 const struct firmware *fw; /* VCE firmware */ 1066 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1067 struct amdgpu_irq_src irq; 1068 unsigned harvest_config; 1069 struct amd_sched_entity entity; 1070 uint32_t srbm_soft_reset; 1071 unsigned num_rings; 1072 }; 1073 1074 /* 1075 * SDMA 1076 */ 1077 struct amdgpu_sdma_instance { 1078 /* SDMA firmware */ 1079 const struct firmware *fw; 1080 uint32_t fw_version; 1081 uint32_t feature_version; 1082 1083 struct amdgpu_ring ring; 1084 bool burst_nop; 1085 }; 1086 1087 struct amdgpu_sdma { 1088 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1089 #ifdef CONFIG_DRM_AMDGPU_SI 1090 //SI DMA has a difference trap irq number for the second engine 1091 struct amdgpu_irq_src trap_irq_1; 1092 #endif 1093 struct amdgpu_irq_src trap_irq; 1094 struct amdgpu_irq_src illegal_inst_irq; 1095 int num_instances; 1096 uint32_t srbm_soft_reset; 1097 }; 1098 1099 /* 1100 * Firmware 1101 */ 1102 struct amdgpu_firmware { 1103 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1104 bool smu_load; 1105 struct amdgpu_bo *fw_buf; 1106 unsigned int fw_size; 1107 }; 1108 1109 /* 1110 * Benchmarking 1111 */ 1112 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1113 1114 1115 /* 1116 * Testing 1117 */ 1118 void amdgpu_test_moves(struct amdgpu_device *adev); 1119 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1120 struct amdgpu_ring *cpA, 1121 struct amdgpu_ring *cpB); 1122 void amdgpu_test_syncing(struct amdgpu_device *adev); 1123 1124 /* 1125 * MMU Notifier 1126 */ 1127 #if defined(CONFIG_MMU_NOTIFIER) 1128 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1129 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1130 #else 1131 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1132 { 1133 return -ENODEV; 1134 } 1135 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1136 #endif 1137 1138 /* 1139 * Debugfs 1140 */ 1141 struct amdgpu_debugfs { 1142 const struct drm_info_list *files; 1143 unsigned num_files; 1144 }; 1145 1146 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1147 const struct drm_info_list *files, 1148 unsigned nfiles); 1149 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1150 1151 #if defined(CONFIG_DEBUG_FS) 1152 int amdgpu_debugfs_init(struct drm_minor *minor); 1153 #endif 1154 1155 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1156 1157 /* 1158 * amdgpu smumgr functions 1159 */ 1160 struct amdgpu_smumgr_funcs { 1161 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1162 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1163 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1164 }; 1165 1166 /* 1167 * amdgpu smumgr 1168 */ 1169 struct amdgpu_smumgr { 1170 struct amdgpu_bo *toc_buf; 1171 struct amdgpu_bo *smu_buf; 1172 /* asic priv smu data */ 1173 void *priv; 1174 spinlock_t smu_lock; 1175 /* smumgr functions */ 1176 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1177 /* ucode loading complete flag */ 1178 uint32_t fw_flags; 1179 }; 1180 1181 /* 1182 * ASIC specific register table accessible by UMD 1183 */ 1184 struct amdgpu_allowed_register_entry { 1185 uint32_t reg_offset; 1186 bool untouched; 1187 bool grbm_indexed; 1188 }; 1189 1190 /* 1191 * ASIC specific functions. 1192 */ 1193 struct amdgpu_asic_funcs { 1194 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1195 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1196 u8 *bios, u32 length_bytes); 1197 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1198 u32 sh_num, u32 reg_offset, u32 *value); 1199 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1200 int (*reset)(struct amdgpu_device *adev); 1201 /* get the reference clock */ 1202 u32 (*get_xclk)(struct amdgpu_device *adev); 1203 /* MM block clocks */ 1204 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1205 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1206 /* static power management */ 1207 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1208 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1209 }; 1210 1211 /* 1212 * IOCTL. 1213 */ 1214 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1215 struct drm_file *filp); 1216 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1217 struct drm_file *filp); 1218 1219 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1220 struct drm_file *filp); 1221 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1222 struct drm_file *filp); 1223 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1224 struct drm_file *filp); 1225 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1226 struct drm_file *filp); 1227 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1228 struct drm_file *filp); 1229 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1230 struct drm_file *filp); 1231 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1232 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1233 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1234 struct drm_file *filp); 1235 1236 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1237 struct drm_file *filp); 1238 1239 /* VRAM scratch page for HDP bug, default vram page */ 1240 struct amdgpu_vram_scratch { 1241 struct amdgpu_bo *robj; 1242 volatile uint32_t *ptr; 1243 u64 gpu_addr; 1244 }; 1245 1246 /* 1247 * ACPI 1248 */ 1249 struct amdgpu_atif_notification_cfg { 1250 bool enabled; 1251 int command_code; 1252 }; 1253 1254 struct amdgpu_atif_notifications { 1255 bool display_switch; 1256 bool expansion_mode_change; 1257 bool thermal_state; 1258 bool forced_power_state; 1259 bool system_power_state; 1260 bool display_conf_change; 1261 bool px_gfx_switch; 1262 bool brightness_change; 1263 bool dgpu_display_event; 1264 }; 1265 1266 struct amdgpu_atif_functions { 1267 bool system_params; 1268 bool sbios_requests; 1269 bool select_active_disp; 1270 bool lid_state; 1271 bool get_tv_standard; 1272 bool set_tv_standard; 1273 bool get_panel_expansion_mode; 1274 bool set_panel_expansion_mode; 1275 bool temperature_change; 1276 bool graphics_device_types; 1277 }; 1278 1279 struct amdgpu_atif { 1280 struct amdgpu_atif_notifications notifications; 1281 struct amdgpu_atif_functions functions; 1282 struct amdgpu_atif_notification_cfg notification_cfg; 1283 struct amdgpu_encoder *encoder_for_bl; 1284 }; 1285 1286 struct amdgpu_atcs_functions { 1287 bool get_ext_state; 1288 bool pcie_perf_req; 1289 bool pcie_dev_rdy; 1290 bool pcie_bus_width; 1291 }; 1292 1293 struct amdgpu_atcs { 1294 struct amdgpu_atcs_functions functions; 1295 }; 1296 1297 /* 1298 * CGS 1299 */ 1300 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1301 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1302 1303 /* 1304 * Core structure, functions and helpers. 1305 */ 1306 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1307 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1308 1309 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1310 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1311 1312 struct amdgpu_device { 1313 struct device *dev; 1314 struct drm_device *ddev; 1315 struct pci_dev *pdev; 1316 1317 #ifdef CONFIG_DRM_AMD_ACP 1318 struct amdgpu_acp acp; 1319 #endif 1320 1321 /* ASIC */ 1322 enum amd_asic_type asic_type; 1323 uint32_t family; 1324 uint32_t rev_id; 1325 uint32_t external_rev_id; 1326 unsigned long flags; 1327 int usec_timeout; 1328 const struct amdgpu_asic_funcs *asic_funcs; 1329 bool shutdown; 1330 bool need_dma32; 1331 bool accel_working; 1332 struct work_struct reset_work; 1333 struct notifier_block acpi_nb; 1334 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1335 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1336 unsigned debugfs_count; 1337 #if defined(CONFIG_DEBUG_FS) 1338 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1339 #endif 1340 struct amdgpu_atif atif; 1341 struct amdgpu_atcs atcs; 1342 struct mutex srbm_mutex; 1343 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1344 struct mutex grbm_idx_mutex; 1345 struct dev_pm_domain vga_pm_domain; 1346 bool have_disp_power_ref; 1347 1348 /* BIOS */ 1349 uint8_t *bios; 1350 uint32_t bios_size; 1351 struct amdgpu_bo *stollen_vga_memory; 1352 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1353 1354 /* Register/doorbell mmio */ 1355 resource_size_t rmmio_base; 1356 resource_size_t rmmio_size; 1357 void __iomem *rmmio; 1358 /* protects concurrent MM_INDEX/DATA based register access */ 1359 spinlock_t mmio_idx_lock; 1360 /* protects concurrent SMC based register access */ 1361 spinlock_t smc_idx_lock; 1362 amdgpu_rreg_t smc_rreg; 1363 amdgpu_wreg_t smc_wreg; 1364 /* protects concurrent PCIE register access */ 1365 spinlock_t pcie_idx_lock; 1366 amdgpu_rreg_t pcie_rreg; 1367 amdgpu_wreg_t pcie_wreg; 1368 amdgpu_rreg_t pciep_rreg; 1369 amdgpu_wreg_t pciep_wreg; 1370 /* protects concurrent UVD register access */ 1371 spinlock_t uvd_ctx_idx_lock; 1372 amdgpu_rreg_t uvd_ctx_rreg; 1373 amdgpu_wreg_t uvd_ctx_wreg; 1374 /* protects concurrent DIDT register access */ 1375 spinlock_t didt_idx_lock; 1376 amdgpu_rreg_t didt_rreg; 1377 amdgpu_wreg_t didt_wreg; 1378 /* protects concurrent gc_cac register access */ 1379 spinlock_t gc_cac_idx_lock; 1380 amdgpu_rreg_t gc_cac_rreg; 1381 amdgpu_wreg_t gc_cac_wreg; 1382 /* protects concurrent ENDPOINT (audio) register access */ 1383 spinlock_t audio_endpt_idx_lock; 1384 amdgpu_block_rreg_t audio_endpt_rreg; 1385 amdgpu_block_wreg_t audio_endpt_wreg; 1386 void __iomem *rio_mem; 1387 resource_size_t rio_mem_size; 1388 struct amdgpu_doorbell doorbell; 1389 1390 /* clock/pll info */ 1391 struct amdgpu_clock clock; 1392 1393 /* MC */ 1394 struct amdgpu_mc mc; 1395 struct amdgpu_gart gart; 1396 struct amdgpu_dummy_page dummy_page; 1397 struct amdgpu_vm_manager vm_manager; 1398 1399 /* memory management */ 1400 struct amdgpu_mman mman; 1401 struct amdgpu_vram_scratch vram_scratch; 1402 struct amdgpu_wb wb; 1403 atomic64_t vram_usage; 1404 atomic64_t vram_vis_usage; 1405 atomic64_t gtt_usage; 1406 atomic64_t num_bytes_moved; 1407 atomic64_t num_evictions; 1408 atomic_t gpu_reset_counter; 1409 1410 /* data for buffer migration throttling */ 1411 struct { 1412 spinlock_t lock; 1413 s64 last_update_us; 1414 s64 accum_us; /* accumulated microseconds */ 1415 u32 log2_max_MBps; 1416 } mm_stats; 1417 1418 /* display */ 1419 bool enable_virtual_display; 1420 struct amdgpu_mode_info mode_info; 1421 struct work_struct hotplug_work; 1422 struct amdgpu_irq_src crtc_irq; 1423 struct amdgpu_irq_src pageflip_irq; 1424 struct amdgpu_irq_src hpd_irq; 1425 1426 /* rings */ 1427 u64 fence_context; 1428 unsigned num_rings; 1429 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1430 bool ib_pool_ready; 1431 struct amdgpu_sa_manager ring_tmp_bo; 1432 1433 /* interrupts */ 1434 struct amdgpu_irq irq; 1435 1436 /* powerplay */ 1437 struct amd_powerplay powerplay; 1438 bool pp_enabled; 1439 bool pp_force_state_enabled; 1440 1441 /* dpm */ 1442 struct amdgpu_pm pm; 1443 u32 cg_flags; 1444 u32 pg_flags; 1445 1446 /* amdgpu smumgr */ 1447 struct amdgpu_smumgr smu; 1448 1449 /* gfx */ 1450 struct amdgpu_gfx gfx; 1451 1452 /* sdma */ 1453 struct amdgpu_sdma sdma; 1454 1455 /* uvd */ 1456 struct amdgpu_uvd uvd; 1457 1458 /* vce */ 1459 struct amdgpu_vce vce; 1460 1461 /* firmwares */ 1462 struct amdgpu_firmware firmware; 1463 1464 /* GDS */ 1465 struct amdgpu_gds gds; 1466 1467 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1468 int num_ip_blocks; 1469 struct mutex mn_lock; 1470 DECLARE_HASHTABLE(mn_hash, 7); 1471 1472 /* tracking pinned memory */ 1473 u64 vram_pin_size; 1474 u64 invisible_pin_size; 1475 u64 gart_pin_size; 1476 1477 /* amdkfd interface */ 1478 struct kfd_dev *kfd; 1479 1480 struct amdgpu_virt virt; 1481 1482 /* link all shadow bo */ 1483 struct list_head shadow_list; 1484 struct mutex shadow_list_lock; 1485 /* link all gtt */ 1486 spinlock_t gtt_list_lock; 1487 struct list_head gtt_list; 1488 1489 /* record hw reset is performed */ 1490 bool has_hw_reset; 1491 1492 }; 1493 1494 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1495 { 1496 return container_of(bdev, struct amdgpu_device, mman.bdev); 1497 } 1498 1499 bool amdgpu_device_is_px(struct drm_device *dev); 1500 int amdgpu_device_init(struct amdgpu_device *adev, 1501 struct drm_device *ddev, 1502 struct pci_dev *pdev, 1503 uint32_t flags); 1504 void amdgpu_device_fini(struct amdgpu_device *adev); 1505 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1506 1507 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1508 bool always_indirect); 1509 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1510 bool always_indirect); 1511 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1512 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1513 1514 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1515 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1516 1517 /* 1518 * Registers read & write functions. 1519 */ 1520 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 1521 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 1522 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 1523 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 1524 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 1525 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1526 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1527 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1528 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1529 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1530 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1531 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1532 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1533 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1534 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1535 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1536 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1537 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1538 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1539 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1540 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1541 #define WREG32_P(reg, val, mask) \ 1542 do { \ 1543 uint32_t tmp_ = RREG32(reg); \ 1544 tmp_ &= (mask); \ 1545 tmp_ |= ((val) & ~(mask)); \ 1546 WREG32(reg, tmp_); \ 1547 } while (0) 1548 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1549 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1550 #define WREG32_PLL_P(reg, val, mask) \ 1551 do { \ 1552 uint32_t tmp_ = RREG32_PLL(reg); \ 1553 tmp_ &= (mask); \ 1554 tmp_ |= ((val) & ~(mask)); \ 1555 WREG32_PLL(reg, tmp_); \ 1556 } while (0) 1557 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1558 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1559 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1560 1561 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1562 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1563 1564 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1565 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1566 1567 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1568 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1569 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1570 1571 #define REG_GET_FIELD(value, reg, field) \ 1572 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1573 1574 #define WREG32_FIELD(reg, field, val) \ 1575 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1576 1577 /* 1578 * BIOS helpers. 1579 */ 1580 #define RBIOS8(i) (adev->bios[i]) 1581 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1582 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1583 1584 /* 1585 * RING helpers. 1586 */ 1587 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 1588 { 1589 if (ring->count_dw <= 0) 1590 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1591 ring->ring[ring->wptr++] = v; 1592 ring->wptr &= ring->ptr_mask; 1593 ring->count_dw--; 1594 } 1595 1596 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 1597 { 1598 unsigned occupied, chunk1, chunk2; 1599 void *dst; 1600 1601 if (ring->count_dw < count_dw) { 1602 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1603 } else { 1604 occupied = ring->wptr & ring->ptr_mask; 1605 dst = (void *)&ring->ring[occupied]; 1606 chunk1 = ring->ptr_mask + 1 - occupied; 1607 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 1608 chunk2 = count_dw - chunk1; 1609 chunk1 <<= 2; 1610 chunk2 <<= 2; 1611 1612 if (chunk1) 1613 memcpy(dst, src, chunk1); 1614 1615 if (chunk2) { 1616 src += chunk1; 1617 dst = (void *)ring->ring; 1618 memcpy(dst, src, chunk2); 1619 } 1620 1621 ring->wptr += count_dw; 1622 ring->wptr &= ring->ptr_mask; 1623 ring->count_dw -= count_dw; 1624 } 1625 } 1626 1627 static inline struct amdgpu_sdma_instance * 1628 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1629 { 1630 struct amdgpu_device *adev = ring->adev; 1631 int i; 1632 1633 for (i = 0; i < adev->sdma.num_instances; i++) 1634 if (&adev->sdma.instance[i].ring == ring) 1635 break; 1636 1637 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1638 return &adev->sdma.instance[i]; 1639 else 1640 return NULL; 1641 } 1642 1643 /* 1644 * ASICs macro. 1645 */ 1646 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1647 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1648 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1649 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1650 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1651 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1652 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1653 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1654 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1655 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1656 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1657 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1658 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1659 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1660 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1661 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1662 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1663 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1664 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1665 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1666 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1667 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1668 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1669 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1670 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1671 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1672 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1673 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1674 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1675 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1676 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1677 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1678 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1679 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1680 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1681 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1682 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1683 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1684 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1685 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1686 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1687 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1688 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1689 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1690 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1691 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1692 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1693 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1694 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1695 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1696 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1697 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1698 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 1699 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1700 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1701 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1702 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1703 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1704 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1705 1706 /* Common functions */ 1707 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1708 bool amdgpu_need_backup(struct amdgpu_device *adev); 1709 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1710 bool amdgpu_need_post(struct amdgpu_device *adev); 1711 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1712 1713 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 1714 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1715 u32 ip_instance, u32 ring, 1716 struct amdgpu_ring **out_ring); 1717 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1718 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1719 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1720 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1721 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1722 uint32_t flags); 1723 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1724 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1725 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1726 unsigned long end); 1727 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1728 int *last_invalidated); 1729 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 1730 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1731 struct ttm_mem_reg *mem); 1732 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1733 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1734 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1735 int amdgpu_ttm_init(struct amdgpu_device *adev); 1736 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1737 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1738 const u32 *registers, 1739 const u32 array_size); 1740 1741 bool amdgpu_device_is_px(struct drm_device *dev); 1742 /* atpx handler */ 1743 #if defined(CONFIG_VGA_SWITCHEROO) 1744 void amdgpu_register_atpx_handler(void); 1745 void amdgpu_unregister_atpx_handler(void); 1746 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1747 bool amdgpu_is_atpx_hybrid(void); 1748 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1749 #else 1750 static inline void amdgpu_register_atpx_handler(void) {} 1751 static inline void amdgpu_unregister_atpx_handler(void) {} 1752 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1753 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1754 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1755 #endif 1756 1757 /* 1758 * KMS 1759 */ 1760 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1761 extern const int amdgpu_max_kms_ioctl; 1762 1763 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1764 void amdgpu_driver_unload_kms(struct drm_device *dev); 1765 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1766 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1767 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1768 struct drm_file *file_priv); 1769 void amdgpu_driver_preclose_kms(struct drm_device *dev, 1770 struct drm_file *file_priv); 1771 int amdgpu_suspend(struct amdgpu_device *adev); 1772 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1773 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1774 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1775 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1776 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1777 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 1778 int *max_error, 1779 struct timeval *vblank_time, 1780 unsigned flags); 1781 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1782 unsigned long arg); 1783 1784 /* 1785 * functions used by amdgpu_encoder.c 1786 */ 1787 struct amdgpu_afmt_acr { 1788 u32 clock; 1789 1790 int n_32khz; 1791 int cts_32khz; 1792 1793 int n_44_1khz; 1794 int cts_44_1khz; 1795 1796 int n_48khz; 1797 int cts_48khz; 1798 1799 }; 1800 1801 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1802 1803 /* amdgpu_acpi.c */ 1804 #if defined(CONFIG_ACPI) 1805 int amdgpu_acpi_init(struct amdgpu_device *adev); 1806 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1807 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1808 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1809 u8 perf_req, bool advertise); 1810 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1811 #else 1812 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1813 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1814 #endif 1815 1816 struct amdgpu_bo_va_mapping * 1817 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1818 uint64_t addr, struct amdgpu_bo **bo); 1819 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 1820 1821 #include "amdgpu_object.h" 1822 #endif 1823