1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #ifdef pr_fmt 32 #undef pr_fmt 33 #endif 34 35 #define pr_fmt(fmt) "amdgpu: " fmt 36 37 #ifdef dev_fmt 38 #undef dev_fmt 39 #endif 40 41 #define dev_fmt(fmt) "amdgpu: " fmt 42 43 #include "amdgpu_ctx.h" 44 45 #include <linux/atomic.h> 46 #include <linux/wait.h> 47 #include <linux/list.h> 48 #include <linux/kref.h> 49 #include <linux/rbtree.h> 50 #include <linux/hashtable.h> 51 #include <linux/dma-fence.h> 52 #include <linux/pci.h> 53 #include <linux/aer.h> 54 55 #include <drm/ttm/ttm_bo_api.h> 56 #include <drm/ttm/ttm_bo_driver.h> 57 #include <drm/ttm/ttm_placement.h> 58 #include <drm/ttm/ttm_execbuf_util.h> 59 60 #include <drm/amdgpu_drm.h> 61 #include <drm/drm_gem.h> 62 #include <drm/drm_ioctl.h> 63 #include <drm/gpu_scheduler.h> 64 65 #include <kgd_kfd_interface.h> 66 #include "dm_pp_interface.h" 67 #include "kgd_pp_interface.h" 68 69 #include "amd_shared.h" 70 #include "amdgpu_mode.h" 71 #include "amdgpu_ih.h" 72 #include "amdgpu_irq.h" 73 #include "amdgpu_ucode.h" 74 #include "amdgpu_ttm.h" 75 #include "amdgpu_psp.h" 76 #include "amdgpu_gds.h" 77 #include "amdgpu_sync.h" 78 #include "amdgpu_ring.h" 79 #include "amdgpu_vm.h" 80 #include "amdgpu_dpm.h" 81 #include "amdgpu_acp.h" 82 #include "amdgpu_uvd.h" 83 #include "amdgpu_vce.h" 84 #include "amdgpu_vcn.h" 85 #include "amdgpu_jpeg.h" 86 #include "amdgpu_mn.h" 87 #include "amdgpu_gmc.h" 88 #include "amdgpu_gfx.h" 89 #include "amdgpu_sdma.h" 90 #include "amdgpu_nbio.h" 91 #include "amdgpu_hdp.h" 92 #include "amdgpu_dm.h" 93 #include "amdgpu_virt.h" 94 #include "amdgpu_csa.h" 95 #include "amdgpu_gart.h" 96 #include "amdgpu_debugfs.h" 97 #include "amdgpu_job.h" 98 #include "amdgpu_bo_list.h" 99 #include "amdgpu_gem.h" 100 #include "amdgpu_doorbell.h" 101 #include "amdgpu_amdkfd.h" 102 #include "amdgpu_smu.h" 103 #include "amdgpu_discovery.h" 104 #include "amdgpu_mes.h" 105 #include "amdgpu_umc.h" 106 #include "amdgpu_mmhub.h" 107 #include "amdgpu_gfxhub.h" 108 #include "amdgpu_df.h" 109 #include "amdgpu_smuio.h" 110 #include "amdgpu_fdinfo.h" 111 #include "amdgpu_mca.h" 112 113 #define MAX_GPU_INSTANCE 16 114 115 struct amdgpu_gpu_instance 116 { 117 struct amdgpu_device *adev; 118 int mgpu_fan_enabled; 119 }; 120 121 struct amdgpu_mgpu_info 122 { 123 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 124 struct mutex mutex; 125 uint32_t num_gpu; 126 uint32_t num_dgpu; 127 uint32_t num_apu; 128 129 /* delayed reset_func for XGMI configuration if necessary */ 130 struct delayed_work delayed_reset_work; 131 bool pending_reset; 132 }; 133 134 enum amdgpu_ss { 135 AMDGPU_SS_DRV_LOAD, 136 AMDGPU_SS_DEV_D0, 137 AMDGPU_SS_DEV_D3, 138 AMDGPU_SS_DRV_UNLOAD 139 }; 140 141 struct amdgpu_watchdog_timer 142 { 143 bool timeout_fatal_disable; 144 uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */ 145 }; 146 147 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 148 149 /* 150 * Modules parameters. 151 */ 152 extern int amdgpu_modeset; 153 extern int amdgpu_vram_limit; 154 extern int amdgpu_vis_vram_limit; 155 extern int amdgpu_gart_size; 156 extern int amdgpu_gtt_size; 157 extern int amdgpu_moverate; 158 extern int amdgpu_benchmarking; 159 extern int amdgpu_testing; 160 extern int amdgpu_audio; 161 extern int amdgpu_disp_priority; 162 extern int amdgpu_hw_i2c; 163 extern int amdgpu_pcie_gen2; 164 extern int amdgpu_msi; 165 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 166 extern int amdgpu_dpm; 167 extern int amdgpu_fw_load_type; 168 extern int amdgpu_aspm; 169 extern int amdgpu_runtime_pm; 170 extern uint amdgpu_ip_block_mask; 171 extern int amdgpu_bapm; 172 extern int amdgpu_deep_color; 173 extern int amdgpu_vm_size; 174 extern int amdgpu_vm_block_size; 175 extern int amdgpu_vm_fragment_size; 176 extern int amdgpu_vm_fault_stop; 177 extern int amdgpu_vm_debug; 178 extern int amdgpu_vm_update_mode; 179 extern int amdgpu_exp_hw_support; 180 extern int amdgpu_dc; 181 extern int amdgpu_sched_jobs; 182 extern int amdgpu_sched_hw_submission; 183 extern uint amdgpu_pcie_gen_cap; 184 extern uint amdgpu_pcie_lane_cap; 185 extern uint amdgpu_cg_mask; 186 extern uint amdgpu_pg_mask; 187 extern uint amdgpu_sdma_phase_quantum; 188 extern char *amdgpu_disable_cu; 189 extern char *amdgpu_virtual_display; 190 extern uint amdgpu_pp_feature_mask; 191 extern uint amdgpu_force_long_training; 192 extern int amdgpu_job_hang_limit; 193 extern int amdgpu_lbpw; 194 extern int amdgpu_compute_multipipe; 195 extern int amdgpu_gpu_recovery; 196 extern int amdgpu_emu_mode; 197 extern uint amdgpu_smu_memory_pool_size; 198 extern int amdgpu_smu_pptable_id; 199 extern uint amdgpu_dc_feature_mask; 200 extern uint amdgpu_freesync_vid_mode; 201 extern uint amdgpu_dc_debug_mask; 202 extern uint amdgpu_dm_abm_level; 203 extern int amdgpu_backlight; 204 extern struct amdgpu_mgpu_info mgpu_info; 205 extern int amdgpu_ras_enable; 206 extern uint amdgpu_ras_mask; 207 extern int amdgpu_bad_page_threshold; 208 extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer; 209 extern int amdgpu_async_gfx_ring; 210 extern int amdgpu_mcbp; 211 extern int amdgpu_discovery; 212 extern int amdgpu_mes; 213 extern int amdgpu_noretry; 214 extern int amdgpu_force_asic_type; 215 extern int amdgpu_smartshift_bias; 216 #ifdef CONFIG_HSA_AMD 217 extern int sched_policy; 218 extern bool debug_evictions; 219 extern bool no_system_mem_limit; 220 #else 221 static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; 222 static const bool __maybe_unused debug_evictions; /* = false */ 223 static const bool __maybe_unused no_system_mem_limit; 224 #endif 225 226 extern int amdgpu_tmz; 227 extern int amdgpu_reset_method; 228 229 #ifdef CONFIG_DRM_AMDGPU_SI 230 extern int amdgpu_si_support; 231 #endif 232 #ifdef CONFIG_DRM_AMDGPU_CIK 233 extern int amdgpu_cik_support; 234 #endif 235 extern int amdgpu_num_kcq; 236 237 #define AMDGPU_VM_MAX_NUM_CTX 4096 238 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 239 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 240 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 241 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 242 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 243 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 244 #define AMDGPUFB_CONN_LIMIT 4 245 #define AMDGPU_BIOS_NUM_SCRATCH 16 246 247 #define AMDGPU_VBIOS_VGA_ALLOCATION (9 * 1024 * 1024) /* reserve 8MB for vga emulator and 1 MB for FB */ 248 249 /* hard reset data */ 250 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 251 252 /* reset flags */ 253 #define AMDGPU_RESET_GFX (1 << 0) 254 #define AMDGPU_RESET_COMPUTE (1 << 1) 255 #define AMDGPU_RESET_DMA (1 << 2) 256 #define AMDGPU_RESET_CP (1 << 3) 257 #define AMDGPU_RESET_GRBM (1 << 4) 258 #define AMDGPU_RESET_DMA1 (1 << 5) 259 #define AMDGPU_RESET_RLC (1 << 6) 260 #define AMDGPU_RESET_SEM (1 << 7) 261 #define AMDGPU_RESET_IH (1 << 8) 262 #define AMDGPU_RESET_VMC (1 << 9) 263 #define AMDGPU_RESET_MC (1 << 10) 264 #define AMDGPU_RESET_DISPLAY (1 << 11) 265 #define AMDGPU_RESET_UVD (1 << 12) 266 #define AMDGPU_RESET_VCE (1 << 13) 267 #define AMDGPU_RESET_VCE1 (1 << 14) 268 269 /* max cursor sizes (in pixels) */ 270 #define CIK_CURSOR_WIDTH 128 271 #define CIK_CURSOR_HEIGHT 128 272 273 /* smasrt shift bias level limits */ 274 #define AMDGPU_SMARTSHIFT_MAX_BIAS (100) 275 #define AMDGPU_SMARTSHIFT_MIN_BIAS (-100) 276 277 struct amdgpu_device; 278 struct amdgpu_ib; 279 struct amdgpu_cs_parser; 280 struct amdgpu_job; 281 struct amdgpu_irq_src; 282 struct amdgpu_fpriv; 283 struct amdgpu_bo_va_mapping; 284 struct kfd_vm_fault_info; 285 struct amdgpu_hive_info; 286 struct amdgpu_reset_context; 287 struct amdgpu_reset_control; 288 289 enum amdgpu_cp_irq { 290 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 291 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 292 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 293 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 294 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 295 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 296 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 297 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 298 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 299 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 300 301 AMDGPU_CP_IRQ_LAST 302 }; 303 304 enum amdgpu_thermal_irq { 305 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 306 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 307 308 AMDGPU_THERMAL_IRQ_LAST 309 }; 310 311 enum amdgpu_kiq_irq { 312 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 313 AMDGPU_CP_KIQ_IRQ_LAST 314 }; 315 316 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 317 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 318 #define MAX_KIQ_REG_TRY 1000 319 320 int amdgpu_device_ip_set_clockgating_state(void *dev, 321 enum amd_ip_block_type block_type, 322 enum amd_clockgating_state state); 323 int amdgpu_device_ip_set_powergating_state(void *dev, 324 enum amd_ip_block_type block_type, 325 enum amd_powergating_state state); 326 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 327 u32 *flags); 328 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 329 enum amd_ip_block_type block_type); 330 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 331 enum amd_ip_block_type block_type); 332 333 #define AMDGPU_MAX_IP_NUM 16 334 335 struct amdgpu_ip_block_status { 336 bool valid; 337 bool sw; 338 bool hw; 339 bool late_initialized; 340 bool hang; 341 }; 342 343 struct amdgpu_ip_block_version { 344 const enum amd_ip_block_type type; 345 const u32 major; 346 const u32 minor; 347 const u32 rev; 348 const struct amd_ip_funcs *funcs; 349 }; 350 351 #define HW_REV(_Major, _Minor, _Rev) \ 352 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 353 354 struct amdgpu_ip_block { 355 struct amdgpu_ip_block_status status; 356 const struct amdgpu_ip_block_version *version; 357 }; 358 359 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 360 enum amd_ip_block_type type, 361 u32 major, u32 minor); 362 363 struct amdgpu_ip_block * 364 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 365 enum amd_ip_block_type type); 366 367 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 368 const struct amdgpu_ip_block_version *ip_block_version); 369 370 /* 371 * BIOS. 372 */ 373 bool amdgpu_get_bios(struct amdgpu_device *adev); 374 bool amdgpu_read_bios(struct amdgpu_device *adev); 375 376 /* 377 * Clocks 378 */ 379 380 #define AMDGPU_MAX_PPLL 3 381 382 struct amdgpu_clock { 383 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 384 struct amdgpu_pll spll; 385 struct amdgpu_pll mpll; 386 /* 10 Khz units */ 387 uint32_t default_mclk; 388 uint32_t default_sclk; 389 uint32_t default_dispclk; 390 uint32_t current_dispclk; 391 uint32_t dp_extclk; 392 uint32_t max_pixel_clock; 393 }; 394 395 /* sub-allocation manager, it has to be protected by another lock. 396 * By conception this is an helper for other part of the driver 397 * like the indirect buffer or semaphore, which both have their 398 * locking. 399 * 400 * Principe is simple, we keep a list of sub allocation in offset 401 * order (first entry has offset == 0, last entry has the highest 402 * offset). 403 * 404 * When allocating new object we first check if there is room at 405 * the end total_size - (last_object_offset + last_object_size) >= 406 * alloc_size. If so we allocate new object there. 407 * 408 * When there is not enough room at the end, we start waiting for 409 * each sub object until we reach object_offset+object_size >= 410 * alloc_size, this object then become the sub object we return. 411 * 412 * Alignment can't be bigger than page size. 413 * 414 * Hole are not considered for allocation to keep things simple. 415 * Assumption is that there won't be hole (all object on same 416 * alignment). 417 */ 418 419 #define AMDGPU_SA_NUM_FENCE_LISTS 32 420 421 struct amdgpu_sa_manager { 422 wait_queue_head_t wq; 423 struct amdgpu_bo *bo; 424 struct list_head *hole; 425 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 426 struct list_head olist; 427 unsigned size; 428 uint64_t gpu_addr; 429 void *cpu_ptr; 430 uint32_t domain; 431 uint32_t align; 432 }; 433 434 /* sub-allocation buffer */ 435 struct amdgpu_sa_bo { 436 struct list_head olist; 437 struct list_head flist; 438 struct amdgpu_sa_manager *manager; 439 unsigned soffset; 440 unsigned eoffset; 441 struct dma_fence *fence; 442 }; 443 444 int amdgpu_fence_slab_init(void); 445 void amdgpu_fence_slab_fini(void); 446 447 /* 448 * IRQS. 449 */ 450 451 struct amdgpu_flip_work { 452 struct delayed_work flip_work; 453 struct work_struct unpin_work; 454 struct amdgpu_device *adev; 455 int crtc_id; 456 u32 target_vblank; 457 uint64_t base; 458 struct drm_pending_vblank_event *event; 459 struct amdgpu_bo *old_abo; 460 struct dma_fence *excl; 461 unsigned shared_count; 462 struct dma_fence **shared; 463 struct dma_fence_cb cb; 464 bool async; 465 }; 466 467 468 /* 469 * CP & rings. 470 */ 471 472 struct amdgpu_ib { 473 struct amdgpu_sa_bo *sa_bo; 474 uint32_t length_dw; 475 uint64_t gpu_addr; 476 uint32_t *ptr; 477 uint32_t flags; 478 }; 479 480 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 481 482 /* 483 * file private structure 484 */ 485 486 struct amdgpu_fpriv { 487 struct amdgpu_vm vm; 488 struct amdgpu_bo_va *prt_va; 489 struct amdgpu_bo_va *csa_va; 490 struct mutex bo_list_lock; 491 struct idr bo_list_handles; 492 struct amdgpu_ctx_mgr ctx_mgr; 493 }; 494 495 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 496 497 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 498 unsigned size, 499 enum amdgpu_ib_pool_type pool, 500 struct amdgpu_ib *ib); 501 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 502 struct dma_fence *f); 503 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 504 struct amdgpu_ib *ibs, struct amdgpu_job *job, 505 struct dma_fence **f); 506 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 507 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 508 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 509 510 /* 511 * CS. 512 */ 513 struct amdgpu_cs_chunk { 514 uint32_t chunk_id; 515 uint32_t length_dw; 516 void *kdata; 517 }; 518 519 struct amdgpu_cs_post_dep { 520 struct drm_syncobj *syncobj; 521 struct dma_fence_chain *chain; 522 u64 point; 523 }; 524 525 struct amdgpu_cs_parser { 526 struct amdgpu_device *adev; 527 struct drm_file *filp; 528 struct amdgpu_ctx *ctx; 529 530 /* chunks */ 531 unsigned nchunks; 532 struct amdgpu_cs_chunk *chunks; 533 534 /* scheduler job object */ 535 struct amdgpu_job *job; 536 struct drm_sched_entity *entity; 537 538 /* buffer objects */ 539 struct ww_acquire_ctx ticket; 540 struct amdgpu_bo_list *bo_list; 541 struct amdgpu_mn *mn; 542 struct amdgpu_bo_list_entry vm_pd; 543 struct list_head validated; 544 struct dma_fence *fence; 545 uint64_t bytes_moved_threshold; 546 uint64_t bytes_moved_vis_threshold; 547 uint64_t bytes_moved; 548 uint64_t bytes_moved_vis; 549 550 /* user fence */ 551 struct amdgpu_bo_list_entry uf_entry; 552 553 unsigned num_post_deps; 554 struct amdgpu_cs_post_dep *post_deps; 555 }; 556 557 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 558 uint32_t ib_idx, int idx) 559 { 560 return p->job->ibs[ib_idx].ptr[idx]; 561 } 562 563 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 564 uint32_t ib_idx, int idx, 565 uint32_t value) 566 { 567 p->job->ibs[ib_idx].ptr[idx] = value; 568 } 569 570 /* 571 * Writeback 572 */ 573 #define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for amdgpu-owned rings. */ 574 575 struct amdgpu_wb { 576 struct amdgpu_bo *wb_obj; 577 volatile uint32_t *wb; 578 uint64_t gpu_addr; 579 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 580 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 581 }; 582 583 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 584 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 585 586 /* 587 * Benchmarking 588 */ 589 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 590 591 592 /* 593 * Testing 594 */ 595 void amdgpu_test_moves(struct amdgpu_device *adev); 596 597 /* 598 * ASIC specific register table accessible by UMD 599 */ 600 struct amdgpu_allowed_register_entry { 601 uint32_t reg_offset; 602 bool grbm_indexed; 603 }; 604 605 enum amd_reset_method { 606 AMD_RESET_METHOD_NONE = -1, 607 AMD_RESET_METHOD_LEGACY = 0, 608 AMD_RESET_METHOD_MODE0, 609 AMD_RESET_METHOD_MODE1, 610 AMD_RESET_METHOD_MODE2, 611 AMD_RESET_METHOD_BACO, 612 AMD_RESET_METHOD_PCI, 613 }; 614 615 struct amdgpu_video_codec_info { 616 u32 codec_type; 617 u32 max_width; 618 u32 max_height; 619 u32 max_pixels_per_frame; 620 u32 max_level; 621 }; 622 623 #define codec_info_build(type, width, height, level) \ 624 .codec_type = type,\ 625 .max_width = width,\ 626 .max_height = height,\ 627 .max_pixels_per_frame = height * width,\ 628 .max_level = level, 629 630 struct amdgpu_video_codecs { 631 const u32 codec_count; 632 const struct amdgpu_video_codec_info *codec_array; 633 }; 634 635 /* 636 * ASIC specific functions. 637 */ 638 struct amdgpu_asic_funcs { 639 bool (*read_disabled_bios)(struct amdgpu_device *adev); 640 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 641 u8 *bios, u32 length_bytes); 642 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 643 u32 sh_num, u32 reg_offset, u32 *value); 644 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 645 int (*reset)(struct amdgpu_device *adev); 646 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 647 /* get the reference clock */ 648 u32 (*get_xclk)(struct amdgpu_device *adev); 649 /* MM block clocks */ 650 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 651 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 652 /* static power management */ 653 int (*get_pcie_lanes)(struct amdgpu_device *adev); 654 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 655 /* get config memsize register */ 656 u32 (*get_config_memsize)(struct amdgpu_device *adev); 657 /* flush hdp write queue */ 658 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 659 /* invalidate hdp read cache */ 660 void (*invalidate_hdp)(struct amdgpu_device *adev, 661 struct amdgpu_ring *ring); 662 /* check if the asic needs a full reset of if soft reset will work */ 663 bool (*need_full_reset)(struct amdgpu_device *adev); 664 /* initialize doorbell layout for specific asic*/ 665 void (*init_doorbell_index)(struct amdgpu_device *adev); 666 /* PCIe bandwidth usage */ 667 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 668 uint64_t *count1); 669 /* do we need to reset the asic at init time (e.g., kexec) */ 670 bool (*need_reset_on_init)(struct amdgpu_device *adev); 671 /* PCIe replay counter */ 672 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 673 /* device supports BACO */ 674 bool (*supports_baco)(struct amdgpu_device *adev); 675 /* pre asic_init quirks */ 676 void (*pre_asic_init)(struct amdgpu_device *adev); 677 /* enter/exit umd stable pstate */ 678 int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter); 679 /* query video codecs */ 680 int (*query_video_codecs)(struct amdgpu_device *adev, bool encode, 681 const struct amdgpu_video_codecs **codecs); 682 }; 683 684 /* 685 * IOCTL. 686 */ 687 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 688 struct drm_file *filp); 689 690 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 691 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 692 struct drm_file *filp); 693 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 694 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 695 struct drm_file *filp); 696 697 /* VRAM scratch page for HDP bug, default vram page */ 698 struct amdgpu_vram_scratch { 699 struct amdgpu_bo *robj; 700 volatile uint32_t *ptr; 701 u64 gpu_addr; 702 }; 703 704 /* 705 * CGS 706 */ 707 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 708 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 709 710 /* 711 * Core structure, functions and helpers. 712 */ 713 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 714 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 715 716 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 717 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 718 719 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 720 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 721 722 struct amdgpu_mmio_remap { 723 u32 reg_offset; 724 resource_size_t bus_addr; 725 }; 726 727 /* Define the HW IP blocks will be used in driver , add more if necessary */ 728 enum amd_hw_ip_block_type { 729 GC_HWIP = 1, 730 HDP_HWIP, 731 SDMA0_HWIP, 732 SDMA1_HWIP, 733 SDMA2_HWIP, 734 SDMA3_HWIP, 735 SDMA4_HWIP, 736 SDMA5_HWIP, 737 SDMA6_HWIP, 738 SDMA7_HWIP, 739 MMHUB_HWIP, 740 ATHUB_HWIP, 741 NBIO_HWIP, 742 MP0_HWIP, 743 MP1_HWIP, 744 UVD_HWIP, 745 VCN_HWIP = UVD_HWIP, 746 JPEG_HWIP = VCN_HWIP, 747 VCE_HWIP, 748 DF_HWIP, 749 DCE_HWIP, 750 OSSSYS_HWIP, 751 SMUIO_HWIP, 752 PWR_HWIP, 753 NBIF_HWIP, 754 THM_HWIP, 755 CLK_HWIP, 756 UMC_HWIP, 757 RSMU_HWIP, 758 MAX_HWIP 759 }; 760 761 #define HWIP_MAX_INSTANCE 10 762 763 struct amd_powerplay { 764 void *pp_handle; 765 const struct amd_pm_funcs *pp_funcs; 766 }; 767 768 /* polaris10 kickers */ 769 #define ASICID_IS_P20(did, rid) (((did == 0x67DF) && \ 770 ((rid == 0xE3) || \ 771 (rid == 0xE4) || \ 772 (rid == 0xE5) || \ 773 (rid == 0xE7) || \ 774 (rid == 0xEF))) || \ 775 ((did == 0x6FDF) && \ 776 ((rid == 0xE7) || \ 777 (rid == 0xEF) || \ 778 (rid == 0xFF)))) 779 780 #define ASICID_IS_P30(did, rid) ((did == 0x67DF) && \ 781 ((rid == 0xE1) || \ 782 (rid == 0xF7))) 783 784 /* polaris11 kickers */ 785 #define ASICID_IS_P21(did, rid) (((did == 0x67EF) && \ 786 ((rid == 0xE0) || \ 787 (rid == 0xE5))) || \ 788 ((did == 0x67FF) && \ 789 ((rid == 0xCF) || \ 790 (rid == 0xEF) || \ 791 (rid == 0xFF)))) 792 793 #define ASICID_IS_P31(did, rid) ((did == 0x67EF) && \ 794 ((rid == 0xE2))) 795 796 /* polaris12 kickers */ 797 #define ASICID_IS_P23(did, rid) (((did == 0x6987) && \ 798 ((rid == 0xC0) || \ 799 (rid == 0xC1) || \ 800 (rid == 0xC3) || \ 801 (rid == 0xC7))) || \ 802 ((did == 0x6981) && \ 803 ((rid == 0x00) || \ 804 (rid == 0x01) || \ 805 (rid == 0x10)))) 806 807 #define AMDGPU_RESET_MAGIC_NUM 64 808 #define AMDGPU_MAX_DF_PERFMONS 4 809 struct amdgpu_device { 810 struct device *dev; 811 struct pci_dev *pdev; 812 struct drm_device ddev; 813 814 #ifdef CONFIG_DRM_AMD_ACP 815 struct amdgpu_acp acp; 816 #endif 817 struct amdgpu_hive_info *hive; 818 /* ASIC */ 819 enum amd_asic_type asic_type; 820 uint32_t family; 821 uint32_t rev_id; 822 uint32_t external_rev_id; 823 unsigned long flags; 824 unsigned long apu_flags; 825 int usec_timeout; 826 const struct amdgpu_asic_funcs *asic_funcs; 827 bool shutdown; 828 bool need_swiotlb; 829 bool accel_working; 830 struct notifier_block acpi_nb; 831 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 832 struct debugfs_blob_wrapper debugfs_vbios_blob; 833 struct mutex srbm_mutex; 834 /* GRBM index mutex. Protects concurrent access to GRBM index */ 835 struct mutex grbm_idx_mutex; 836 struct dev_pm_domain vga_pm_domain; 837 bool have_disp_power_ref; 838 bool have_atomics_support; 839 840 /* BIOS */ 841 bool is_atom_fw; 842 uint8_t *bios; 843 uint32_t bios_size; 844 uint32_t bios_scratch_reg_offset; 845 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 846 847 /* Register/doorbell mmio */ 848 resource_size_t rmmio_base; 849 resource_size_t rmmio_size; 850 void __iomem *rmmio; 851 /* protects concurrent MM_INDEX/DATA based register access */ 852 spinlock_t mmio_idx_lock; 853 struct amdgpu_mmio_remap rmmio_remap; 854 /* protects concurrent SMC based register access */ 855 spinlock_t smc_idx_lock; 856 amdgpu_rreg_t smc_rreg; 857 amdgpu_wreg_t smc_wreg; 858 /* protects concurrent PCIE register access */ 859 spinlock_t pcie_idx_lock; 860 amdgpu_rreg_t pcie_rreg; 861 amdgpu_wreg_t pcie_wreg; 862 amdgpu_rreg_t pciep_rreg; 863 amdgpu_wreg_t pciep_wreg; 864 amdgpu_rreg64_t pcie_rreg64; 865 amdgpu_wreg64_t pcie_wreg64; 866 /* protects concurrent UVD register access */ 867 spinlock_t uvd_ctx_idx_lock; 868 amdgpu_rreg_t uvd_ctx_rreg; 869 amdgpu_wreg_t uvd_ctx_wreg; 870 /* protects concurrent DIDT register access */ 871 spinlock_t didt_idx_lock; 872 amdgpu_rreg_t didt_rreg; 873 amdgpu_wreg_t didt_wreg; 874 /* protects concurrent gc_cac register access */ 875 spinlock_t gc_cac_idx_lock; 876 amdgpu_rreg_t gc_cac_rreg; 877 amdgpu_wreg_t gc_cac_wreg; 878 /* protects concurrent se_cac register access */ 879 spinlock_t se_cac_idx_lock; 880 amdgpu_rreg_t se_cac_rreg; 881 amdgpu_wreg_t se_cac_wreg; 882 /* protects concurrent ENDPOINT (audio) register access */ 883 spinlock_t audio_endpt_idx_lock; 884 amdgpu_block_rreg_t audio_endpt_rreg; 885 amdgpu_block_wreg_t audio_endpt_wreg; 886 struct amdgpu_doorbell doorbell; 887 888 /* clock/pll info */ 889 struct amdgpu_clock clock; 890 891 /* MC */ 892 struct amdgpu_gmc gmc; 893 struct amdgpu_gart gart; 894 dma_addr_t dummy_page_addr; 895 struct amdgpu_vm_manager vm_manager; 896 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 897 unsigned num_vmhubs; 898 899 /* memory management */ 900 struct amdgpu_mman mman; 901 struct amdgpu_vram_scratch vram_scratch; 902 struct amdgpu_wb wb; 903 atomic64_t num_bytes_moved; 904 atomic64_t num_evictions; 905 atomic64_t num_vram_cpu_page_faults; 906 atomic_t gpu_reset_counter; 907 atomic_t vram_lost_counter; 908 909 /* data for buffer migration throttling */ 910 struct { 911 spinlock_t lock; 912 s64 last_update_us; 913 s64 accum_us; /* accumulated microseconds */ 914 s64 accum_us_vis; /* for visible VRAM */ 915 u32 log2_max_MBps; 916 } mm_stats; 917 918 /* display */ 919 bool enable_virtual_display; 920 struct amdgpu_vkms_output *amdgpu_vkms_output; 921 struct amdgpu_mode_info mode_info; 922 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 923 struct work_struct hotplug_work; 924 struct amdgpu_irq_src crtc_irq; 925 struct amdgpu_irq_src vline0_irq; 926 struct amdgpu_irq_src vupdate_irq; 927 struct amdgpu_irq_src pageflip_irq; 928 struct amdgpu_irq_src hpd_irq; 929 struct amdgpu_irq_src dmub_trace_irq; 930 struct amdgpu_irq_src dmub_outbox_irq; 931 932 /* rings */ 933 u64 fence_context; 934 unsigned num_rings; 935 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 936 bool ib_pool_ready; 937 struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; 938 struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; 939 940 /* interrupts */ 941 struct amdgpu_irq irq; 942 943 /* powerplay */ 944 struct amd_powerplay powerplay; 945 bool pp_force_state_enabled; 946 947 /* smu */ 948 struct smu_context smu; 949 950 /* dpm */ 951 struct amdgpu_pm pm; 952 u32 cg_flags; 953 u32 pg_flags; 954 955 /* nbio */ 956 struct amdgpu_nbio nbio; 957 958 /* hdp */ 959 struct amdgpu_hdp hdp; 960 961 /* smuio */ 962 struct amdgpu_smuio smuio; 963 964 /* mmhub */ 965 struct amdgpu_mmhub mmhub; 966 967 /* gfxhub */ 968 struct amdgpu_gfxhub gfxhub; 969 970 /* gfx */ 971 struct amdgpu_gfx gfx; 972 973 /* sdma */ 974 struct amdgpu_sdma sdma; 975 976 /* uvd */ 977 struct amdgpu_uvd uvd; 978 979 /* vce */ 980 struct amdgpu_vce vce; 981 982 /* vcn */ 983 struct amdgpu_vcn vcn; 984 985 /* jpeg */ 986 struct amdgpu_jpeg jpeg; 987 988 /* firmwares */ 989 struct amdgpu_firmware firmware; 990 991 /* PSP */ 992 struct psp_context psp; 993 994 /* GDS */ 995 struct amdgpu_gds gds; 996 997 /* KFD */ 998 struct amdgpu_kfd_dev kfd; 999 1000 /* UMC */ 1001 struct amdgpu_umc umc; 1002 1003 /* display related functionality */ 1004 struct amdgpu_display_manager dm; 1005 1006 /* mes */ 1007 bool enable_mes; 1008 struct amdgpu_mes mes; 1009 1010 /* df */ 1011 struct amdgpu_df df; 1012 1013 /* MCA */ 1014 struct amdgpu_mca mca; 1015 1016 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1017 uint32_t harvest_ip_mask; 1018 int num_ip_blocks; 1019 struct mutex mn_lock; 1020 DECLARE_HASHTABLE(mn_hash, 7); 1021 1022 /* tracking pinned memory */ 1023 atomic64_t vram_pin_size; 1024 atomic64_t visible_pin_size; 1025 atomic64_t gart_pin_size; 1026 1027 /* soc15 register offset based on ip, instance and segment */ 1028 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 1029 1030 /* delayed work_func for deferring clockgating during resume */ 1031 struct delayed_work delayed_init_work; 1032 1033 struct amdgpu_virt virt; 1034 1035 /* link all shadow bo */ 1036 struct list_head shadow_list; 1037 struct mutex shadow_list_lock; 1038 1039 /* record hw reset is performed */ 1040 bool has_hw_reset; 1041 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 1042 1043 /* s3/s4 mask */ 1044 bool in_suspend; 1045 bool in_s3; 1046 bool in_s4; 1047 bool in_s0ix; 1048 1049 atomic_t in_gpu_reset; 1050 enum pp_mp1_state mp1_state; 1051 struct rw_semaphore reset_sem; 1052 struct amdgpu_doorbell_index doorbell_index; 1053 1054 struct mutex notifier_lock; 1055 1056 int asic_reset_res; 1057 struct work_struct xgmi_reset_work; 1058 struct list_head reset_list; 1059 1060 long gfx_timeout; 1061 long sdma_timeout; 1062 long video_timeout; 1063 long compute_timeout; 1064 1065 uint64_t unique_id; 1066 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 1067 1068 /* enable runtime pm on the device */ 1069 bool runpm; 1070 bool in_runpm; 1071 bool has_pr3; 1072 1073 bool pm_sysfs_en; 1074 bool ucode_sysfs_en; 1075 1076 /* Chip product information */ 1077 char product_number[16]; 1078 char product_name[32]; 1079 char serial[20]; 1080 1081 struct amdgpu_autodump autodump; 1082 1083 atomic_t throttling_logging_enabled; 1084 struct ratelimit_state throttling_logging_rs; 1085 uint32_t ras_hw_enabled; 1086 uint32_t ras_enabled; 1087 1088 bool no_hw_access; 1089 struct pci_saved_state *pci_state; 1090 1091 struct amdgpu_reset_control *reset_cntl; 1092 }; 1093 1094 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) 1095 { 1096 return container_of(ddev, struct amdgpu_device, ddev); 1097 } 1098 1099 static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) 1100 { 1101 return &adev->ddev; 1102 } 1103 1104 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) 1105 { 1106 return container_of(bdev, struct amdgpu_device, mman.bdev); 1107 } 1108 1109 int amdgpu_device_init(struct amdgpu_device *adev, 1110 uint32_t flags); 1111 void amdgpu_device_fini_hw(struct amdgpu_device *adev); 1112 void amdgpu_device_fini_sw(struct amdgpu_device *adev); 1113 1114 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1115 1116 void amdgpu_device_mm_access(struct amdgpu_device *adev, loff_t pos, 1117 void *buf, size_t size, bool write); 1118 size_t amdgpu_device_aper_access(struct amdgpu_device *adev, loff_t pos, 1119 void *buf, size_t size, bool write); 1120 1121 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1122 void *buf, size_t size, bool write); 1123 uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, 1124 uint32_t reg, uint32_t acc_flags); 1125 void amdgpu_device_wreg(struct amdgpu_device *adev, 1126 uint32_t reg, uint32_t v, 1127 uint32_t acc_flags); 1128 void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 1129 uint32_t reg, uint32_t v); 1130 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1131 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1132 1133 u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, 1134 u32 pcie_index, u32 pcie_data, 1135 u32 reg_addr); 1136 u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, 1137 u32 pcie_index, u32 pcie_data, 1138 u32 reg_addr); 1139 void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, 1140 u32 pcie_index, u32 pcie_data, 1141 u32 reg_addr, u32 reg_data); 1142 void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 1143 u32 pcie_index, u32 pcie_data, 1144 u32 reg_addr, u64 reg_data); 1145 1146 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1147 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1148 1149 int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, 1150 struct amdgpu_reset_context *reset_context); 1151 1152 int amdgpu_do_asic_reset(struct list_head *device_list_handle, 1153 struct amdgpu_reset_context *reset_context); 1154 1155 int emu_soc_asic_init(struct amdgpu_device *adev); 1156 1157 /* 1158 * Registers read & write functions. 1159 */ 1160 #define AMDGPU_REGS_NO_KIQ (1<<1) 1161 #define AMDGPU_REGS_RLC (1<<2) 1162 1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1164 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1165 1166 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg)) 1167 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v)) 1168 1169 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1170 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1171 1172 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0) 1173 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0)) 1174 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0) 1175 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1176 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1177 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1178 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1179 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1180 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1181 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1182 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1183 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1184 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1185 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1186 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1187 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1188 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1189 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1190 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1191 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1192 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1193 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1194 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1195 #define WREG32_P(reg, val, mask) \ 1196 do { \ 1197 uint32_t tmp_ = RREG32(reg); \ 1198 tmp_ &= (mask); \ 1199 tmp_ |= ((val) & ~(mask)); \ 1200 WREG32(reg, tmp_); \ 1201 } while (0) 1202 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1203 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1204 #define WREG32_PLL_P(reg, val, mask) \ 1205 do { \ 1206 uint32_t tmp_ = RREG32_PLL(reg); \ 1207 tmp_ &= (mask); \ 1208 tmp_ |= ((val) & ~(mask)); \ 1209 WREG32_PLL(reg, tmp_); \ 1210 } while (0) 1211 1212 #define WREG32_SMC_P(_Reg, _Val, _Mask) \ 1213 do { \ 1214 u32 tmp = RREG32_SMC(_Reg); \ 1215 tmp &= (_Mask); \ 1216 tmp |= ((_Val) & ~(_Mask)); \ 1217 WREG32_SMC(_Reg, tmp); \ 1218 } while (0) 1219 1220 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false)) 1221 1222 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1223 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1224 1225 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1226 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1227 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1228 1229 #define REG_GET_FIELD(value, reg, field) \ 1230 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1231 1232 #define WREG32_FIELD(reg, field, val) \ 1233 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1234 1235 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1236 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1237 1238 /* 1239 * BIOS helpers. 1240 */ 1241 #define RBIOS8(i) (adev->bios[i]) 1242 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1243 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1244 1245 /* 1246 * ASICs macro. 1247 */ 1248 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1249 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1250 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1251 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1252 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1253 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1254 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1255 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1256 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1257 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1258 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1259 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1260 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1261 #define amdgpu_asic_flush_hdp(adev, r) \ 1262 ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r))) 1263 #define amdgpu_asic_invalidate_hdp(adev, r) \ 1264 ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r))) 1265 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1266 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1267 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1268 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1269 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1270 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1271 #define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev)) 1272 #define amdgpu_asic_update_umd_stable_pstate(adev, enter) \ 1273 ((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0) 1274 #define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c)) 1275 1276 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1277 1278 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y)) 1279 1280 /* Common functions */ 1281 bool amdgpu_device_has_job_running(struct amdgpu_device *adev); 1282 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1283 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1284 struct amdgpu_job* job); 1285 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1286 int amdgpu_device_pci_reset(struct amdgpu_device *adev); 1287 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1288 1289 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1290 u64 num_vis_bytes); 1291 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1292 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1293 const u32 *registers, 1294 const u32 array_size); 1295 1296 int amdgpu_device_mode1_reset(struct amdgpu_device *adev); 1297 bool amdgpu_device_supports_atpx(struct drm_device *dev); 1298 bool amdgpu_device_supports_px(struct drm_device *dev); 1299 bool amdgpu_device_supports_boco(struct drm_device *dev); 1300 bool amdgpu_device_supports_smart_shift(struct drm_device *dev); 1301 bool amdgpu_device_supports_baco(struct drm_device *dev); 1302 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1303 struct amdgpu_device *peer_adev); 1304 int amdgpu_device_baco_enter(struct drm_device *dev); 1305 int amdgpu_device_baco_exit(struct drm_device *dev); 1306 1307 void amdgpu_device_flush_hdp(struct amdgpu_device *adev, 1308 struct amdgpu_ring *ring); 1309 void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 1310 struct amdgpu_ring *ring); 1311 1312 /* atpx handler */ 1313 #if defined(CONFIG_VGA_SWITCHEROO) 1314 void amdgpu_register_atpx_handler(void); 1315 void amdgpu_unregister_atpx_handler(void); 1316 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1317 bool amdgpu_is_atpx_hybrid(void); 1318 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1319 bool amdgpu_has_atpx(void); 1320 #else 1321 static inline void amdgpu_register_atpx_handler(void) {} 1322 static inline void amdgpu_unregister_atpx_handler(void) {} 1323 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1324 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1325 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1326 static inline bool amdgpu_has_atpx(void) { return false; } 1327 #endif 1328 1329 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1330 void *amdgpu_atpx_get_dhandle(void); 1331 #else 1332 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1333 #endif 1334 1335 /* 1336 * KMS 1337 */ 1338 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1339 extern const int amdgpu_max_kms_ioctl; 1340 1341 int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags); 1342 void amdgpu_driver_unload_kms(struct drm_device *dev); 1343 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1344 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1345 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1346 struct drm_file *file_priv); 1347 void amdgpu_driver_release_kms(struct drm_device *dev); 1348 1349 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1350 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1351 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1352 u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); 1353 int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); 1354 void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); 1355 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1356 unsigned long arg); 1357 int amdgpu_info_ioctl(struct drm_device *dev, void *data, 1358 struct drm_file *filp); 1359 1360 /* 1361 * functions used by amdgpu_encoder.c 1362 */ 1363 struct amdgpu_afmt_acr { 1364 u32 clock; 1365 1366 int n_32khz; 1367 int cts_32khz; 1368 1369 int n_44_1khz; 1370 int cts_44_1khz; 1371 1372 int n_48khz; 1373 int cts_48khz; 1374 1375 }; 1376 1377 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1378 1379 /* amdgpu_acpi.c */ 1380 1381 /* ATCS Device/Driver State */ 1382 #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 1383 #define AMDGPU_ATCS_PSC_DEV_STATE_D3_HOT 3 1384 #define AMDGPU_ATCS_PSC_DRV_STATE_OPR 0 1385 #define AMDGPU_ATCS_PSC_DRV_STATE_NOT_OPR 1 1386 1387 #if defined(CONFIG_ACPI) 1388 int amdgpu_acpi_init(struct amdgpu_device *adev); 1389 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1390 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1391 bool amdgpu_acpi_is_power_shift_control_supported(void); 1392 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1393 u8 perf_req, bool advertise); 1394 int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1395 u8 dev_state, bool drv_state); 1396 int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); 1397 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1398 1399 void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); 1400 bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev); 1401 void amdgpu_acpi_detect(void); 1402 #else 1403 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1404 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1405 static inline bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { return false; } 1406 static inline void amdgpu_acpi_detect(void) { } 1407 static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } 1408 static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, 1409 u8 dev_state, bool drv_state) { return 0; } 1410 static inline int amdgpu_acpi_smart_shift_update(struct drm_device *dev, 1411 enum amdgpu_ss ss_state) { return 0; } 1412 #endif 1413 1414 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1415 uint64_t addr, struct amdgpu_bo **bo, 1416 struct amdgpu_bo_va_mapping **mapping); 1417 1418 #if defined(CONFIG_DRM_AMD_DC) 1419 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1420 #else 1421 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1422 #endif 1423 1424 1425 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1426 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1427 1428 pci_ers_result_t amdgpu_pci_error_detected(struct pci_dev *pdev, 1429 pci_channel_state_t state); 1430 pci_ers_result_t amdgpu_pci_mmio_enabled(struct pci_dev *pdev); 1431 pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev); 1432 void amdgpu_pci_resume(struct pci_dev *pdev); 1433 1434 bool amdgpu_device_cache_pci_state(struct pci_dev *pdev); 1435 bool amdgpu_device_load_pci_state(struct pci_dev *pdev); 1436 1437 bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev); 1438 1439 int amdgpu_device_set_cg_state(struct amdgpu_device *adev, 1440 enum amd_clockgating_state state); 1441 int amdgpu_device_set_pg_state(struct amdgpu_device *adev, 1442 enum amd_powergating_state state); 1443 1444 #include "amdgpu_object.h" 1445 1446 static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 1447 { 1448 return adev->gmc.tmz_enabled; 1449 } 1450 1451 static inline int amdgpu_in_reset(struct amdgpu_device *adev) 1452 { 1453 return atomic_read(&adev->in_gpu_reset); 1454 } 1455 #endif 1456