1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/dma-fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_ttm.h" 55 #include "amdgpu_psp.h" 56 #include "amdgpu_gds.h" 57 #include "amdgpu_sync.h" 58 #include "amdgpu_ring.h" 59 #include "amdgpu_vm.h" 60 #include "amd_powerplay.h" 61 #include "amdgpu_dpm.h" 62 #include "amdgpu_acp.h" 63 #include "amdgpu_uvd.h" 64 #include "amdgpu_vce.h" 65 66 #include "gpu_scheduler.h" 67 #include "amdgpu_virt.h" 68 69 /* 70 * Modules parameters. 71 */ 72 extern int amdgpu_modeset; 73 extern int amdgpu_vram_limit; 74 extern int amdgpu_gart_size; 75 extern int amdgpu_moverate; 76 extern int amdgpu_benchmarking; 77 extern int amdgpu_testing; 78 extern int amdgpu_audio; 79 extern int amdgpu_disp_priority; 80 extern int amdgpu_hw_i2c; 81 extern int amdgpu_pcie_gen2; 82 extern int amdgpu_msi; 83 extern int amdgpu_lockup_timeout; 84 extern int amdgpu_dpm; 85 extern int amdgpu_fw_load_type; 86 extern int amdgpu_aspm; 87 extern int amdgpu_runtime_pm; 88 extern unsigned amdgpu_ip_block_mask; 89 extern int amdgpu_bapm; 90 extern int amdgpu_deep_color; 91 extern int amdgpu_vm_size; 92 extern int amdgpu_vm_block_size; 93 extern int amdgpu_vm_fault_stop; 94 extern int amdgpu_vm_debug; 95 extern int amdgpu_sched_jobs; 96 extern int amdgpu_sched_hw_submission; 97 extern int amdgpu_no_evict; 98 extern int amdgpu_direct_gma_size; 99 extern unsigned amdgpu_pcie_gen_cap; 100 extern unsigned amdgpu_pcie_lane_cap; 101 extern unsigned amdgpu_cg_mask; 102 extern unsigned amdgpu_pg_mask; 103 extern char *amdgpu_disable_cu; 104 extern char *amdgpu_virtual_display; 105 extern unsigned amdgpu_pp_feature_mask; 106 extern int amdgpu_vram_page_split; 107 extern int amdgpu_ngg; 108 extern int amdgpu_prim_buf_per_se; 109 extern int amdgpu_pos_buf_per_se; 110 extern int amdgpu_cntl_sb_buf_per_se; 111 extern int amdgpu_param_buf_per_se; 112 113 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 114 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 115 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 116 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 117 #define AMDGPU_IB_POOL_SIZE 16 118 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 119 #define AMDGPUFB_CONN_LIMIT 4 120 #define AMDGPU_BIOS_NUM_SCRATCH 16 121 122 /* max number of IP instances */ 123 #define AMDGPU_MAX_SDMA_INSTANCES 2 124 125 /* max number of VMHUB */ 126 #define AMDGPU_MAX_VMHUBS 2 127 #define AMDGPU_MMHUB 0 128 #define AMDGPU_GFXHUB 1 129 130 /* hardcode that limit for now */ 131 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 132 133 /* hard reset data */ 134 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 135 136 /* reset flags */ 137 #define AMDGPU_RESET_GFX (1 << 0) 138 #define AMDGPU_RESET_COMPUTE (1 << 1) 139 #define AMDGPU_RESET_DMA (1 << 2) 140 #define AMDGPU_RESET_CP (1 << 3) 141 #define AMDGPU_RESET_GRBM (1 << 4) 142 #define AMDGPU_RESET_DMA1 (1 << 5) 143 #define AMDGPU_RESET_RLC (1 << 6) 144 #define AMDGPU_RESET_SEM (1 << 7) 145 #define AMDGPU_RESET_IH (1 << 8) 146 #define AMDGPU_RESET_VMC (1 << 9) 147 #define AMDGPU_RESET_MC (1 << 10) 148 #define AMDGPU_RESET_DISPLAY (1 << 11) 149 #define AMDGPU_RESET_UVD (1 << 12) 150 #define AMDGPU_RESET_VCE (1 << 13) 151 #define AMDGPU_RESET_VCE1 (1 << 14) 152 153 /* GFX current status */ 154 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 155 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 156 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 157 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 158 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 159 160 /* max cursor sizes (in pixels) */ 161 #define CIK_CURSOR_WIDTH 128 162 #define CIK_CURSOR_HEIGHT 128 163 164 struct amdgpu_device; 165 struct amdgpu_ib; 166 struct amdgpu_cs_parser; 167 struct amdgpu_job; 168 struct amdgpu_irq_src; 169 struct amdgpu_fpriv; 170 171 enum amdgpu_cp_irq { 172 AMDGPU_CP_IRQ_GFX_EOP = 0, 173 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 174 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 175 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 176 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 177 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 178 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 179 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 180 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 181 182 AMDGPU_CP_IRQ_LAST 183 }; 184 185 enum amdgpu_sdma_irq { 186 AMDGPU_SDMA_IRQ_TRAP0 = 0, 187 AMDGPU_SDMA_IRQ_TRAP1, 188 189 AMDGPU_SDMA_IRQ_LAST 190 }; 191 192 enum amdgpu_thermal_irq { 193 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 194 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 195 196 AMDGPU_THERMAL_IRQ_LAST 197 }; 198 199 enum amdgpu_kiq_irq { 200 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 201 AMDGPU_CP_KIQ_IRQ_LAST 202 }; 203 204 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 205 enum amd_ip_block_type block_type, 206 enum amd_clockgating_state state); 207 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 208 enum amd_ip_block_type block_type, 209 enum amd_powergating_state state); 210 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags); 211 int amdgpu_wait_for_idle(struct amdgpu_device *adev, 212 enum amd_ip_block_type block_type); 213 bool amdgpu_is_idle(struct amdgpu_device *adev, 214 enum amd_ip_block_type block_type); 215 216 #define AMDGPU_MAX_IP_NUM 16 217 218 struct amdgpu_ip_block_status { 219 bool valid; 220 bool sw; 221 bool hw; 222 bool late_initialized; 223 bool hang; 224 }; 225 226 struct amdgpu_ip_block_version { 227 const enum amd_ip_block_type type; 228 const u32 major; 229 const u32 minor; 230 const u32 rev; 231 const struct amd_ip_funcs *funcs; 232 }; 233 234 struct amdgpu_ip_block { 235 struct amdgpu_ip_block_status status; 236 const struct amdgpu_ip_block_version *version; 237 }; 238 239 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 240 enum amd_ip_block_type type, 241 u32 major, u32 minor); 242 243 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev, 244 enum amd_ip_block_type type); 245 246 int amdgpu_ip_block_add(struct amdgpu_device *adev, 247 const struct amdgpu_ip_block_version *ip_block_version); 248 249 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 250 struct amdgpu_buffer_funcs { 251 /* maximum bytes in a single operation */ 252 uint32_t copy_max_bytes; 253 254 /* number of dw to reserve per operation */ 255 unsigned copy_num_dw; 256 257 /* used for buffer migration */ 258 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 259 /* src addr in bytes */ 260 uint64_t src_offset, 261 /* dst addr in bytes */ 262 uint64_t dst_offset, 263 /* number of byte to transfer */ 264 uint32_t byte_count); 265 266 /* maximum bytes in a single operation */ 267 uint32_t fill_max_bytes; 268 269 /* number of dw to reserve per operation */ 270 unsigned fill_num_dw; 271 272 /* used for buffer clearing */ 273 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 274 /* value to write to memory */ 275 uint32_t src_data, 276 /* dst addr in bytes */ 277 uint64_t dst_offset, 278 /* number of byte to fill */ 279 uint32_t byte_count); 280 }; 281 282 /* provided by hw blocks that can write ptes, e.g., sdma */ 283 struct amdgpu_vm_pte_funcs { 284 /* copy pte entries from GART */ 285 void (*copy_pte)(struct amdgpu_ib *ib, 286 uint64_t pe, uint64_t src, 287 unsigned count); 288 /* write pte one entry at a time with addr mapping */ 289 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe, 290 uint64_t value, unsigned count, 291 uint32_t incr); 292 /* for linear pte/pde updates without addr mapping */ 293 void (*set_pte_pde)(struct amdgpu_ib *ib, 294 uint64_t pe, 295 uint64_t addr, unsigned count, 296 uint32_t incr, uint64_t flags); 297 }; 298 299 /* provided by the gmc block */ 300 struct amdgpu_gart_funcs { 301 /* flush the vm tlb via mmio */ 302 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 303 uint32_t vmid); 304 /* write pte/pde updates using the cpu */ 305 int (*set_pte_pde)(struct amdgpu_device *adev, 306 void *cpu_pt_addr, /* cpu addr of page table */ 307 uint32_t gpu_page_idx, /* pte/pde to update */ 308 uint64_t addr, /* addr to write into pte/pde */ 309 uint64_t flags); /* access flags */ 310 /* enable/disable PRT support */ 311 void (*set_prt)(struct amdgpu_device *adev, bool enable); 312 /* set pte flags based per asic */ 313 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev, 314 uint32_t flags); 315 }; 316 317 /* provided by the mc block */ 318 struct amdgpu_mc_funcs { 319 /* adjust mc addr in fb for APU case */ 320 u64 (*adjust_mc_addr)(struct amdgpu_device *adev, u64 addr); 321 }; 322 323 /* provided by the ih block */ 324 struct amdgpu_ih_funcs { 325 /* ring read/write ptr handling, called from interrupt context */ 326 u32 (*get_wptr)(struct amdgpu_device *adev); 327 void (*decode_iv)(struct amdgpu_device *adev, 328 struct amdgpu_iv_entry *entry); 329 void (*set_rptr)(struct amdgpu_device *adev); 330 }; 331 332 /* 333 * BIOS. 334 */ 335 bool amdgpu_get_bios(struct amdgpu_device *adev); 336 bool amdgpu_read_bios(struct amdgpu_device *adev); 337 338 /* 339 * Dummy page 340 */ 341 struct amdgpu_dummy_page { 342 struct page *page; 343 dma_addr_t addr; 344 }; 345 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 346 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 347 348 349 /* 350 * Clocks 351 */ 352 353 #define AMDGPU_MAX_PPLL 3 354 355 struct amdgpu_clock { 356 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 357 struct amdgpu_pll spll; 358 struct amdgpu_pll mpll; 359 /* 10 Khz units */ 360 uint32_t default_mclk; 361 uint32_t default_sclk; 362 uint32_t default_dispclk; 363 uint32_t current_dispclk; 364 uint32_t dp_extclk; 365 uint32_t max_pixel_clock; 366 }; 367 368 /* 369 * BO. 370 */ 371 struct amdgpu_bo_list_entry { 372 struct amdgpu_bo *robj; 373 struct ttm_validate_buffer tv; 374 struct amdgpu_bo_va *bo_va; 375 uint32_t priority; 376 struct page **user_pages; 377 int user_invalidated; 378 }; 379 380 struct amdgpu_bo_va_mapping { 381 struct list_head list; 382 struct interval_tree_node it; 383 uint64_t offset; 384 uint64_t flags; 385 }; 386 387 /* bo virtual addresses in a specific vm */ 388 struct amdgpu_bo_va { 389 /* protected by bo being reserved */ 390 struct list_head bo_list; 391 struct dma_fence *last_pt_update; 392 unsigned ref_count; 393 394 /* protected by vm mutex and spinlock */ 395 struct list_head vm_status; 396 397 /* mappings for this bo_va */ 398 struct list_head invalids; 399 struct list_head valids; 400 401 /* constant after initialization */ 402 struct amdgpu_vm *vm; 403 struct amdgpu_bo *bo; 404 }; 405 406 #define AMDGPU_GEM_DOMAIN_MAX 0x3 407 408 struct amdgpu_bo { 409 /* Protected by tbo.reserved */ 410 u32 prefered_domains; 411 u32 allowed_domains; 412 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 413 struct ttm_placement placement; 414 struct ttm_buffer_object tbo; 415 struct ttm_bo_kmap_obj kmap; 416 u64 flags; 417 unsigned pin_count; 418 void *kptr; 419 u64 tiling_flags; 420 u64 metadata_flags; 421 void *metadata; 422 u32 metadata_size; 423 unsigned prime_shared_count; 424 /* list of all virtual address to which this bo 425 * is associated to 426 */ 427 struct list_head va; 428 /* Constant after initialization */ 429 struct drm_gem_object gem_base; 430 struct amdgpu_bo *parent; 431 struct amdgpu_bo *shadow; 432 433 struct ttm_bo_kmap_obj dma_buf_vmap; 434 struct amdgpu_mn *mn; 435 struct list_head mn_list; 436 struct list_head shadow_list; 437 }; 438 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 439 440 void amdgpu_gem_object_free(struct drm_gem_object *obj); 441 int amdgpu_gem_object_open(struct drm_gem_object *obj, 442 struct drm_file *file_priv); 443 void amdgpu_gem_object_close(struct drm_gem_object *obj, 444 struct drm_file *file_priv); 445 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 446 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 447 struct drm_gem_object * 448 amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 449 struct dma_buf_attachment *attach, 450 struct sg_table *sg); 451 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 452 struct drm_gem_object *gobj, 453 int flags); 454 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 455 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 456 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 457 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 458 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 459 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 460 461 /* sub-allocation manager, it has to be protected by another lock. 462 * By conception this is an helper for other part of the driver 463 * like the indirect buffer or semaphore, which both have their 464 * locking. 465 * 466 * Principe is simple, we keep a list of sub allocation in offset 467 * order (first entry has offset == 0, last entry has the highest 468 * offset). 469 * 470 * When allocating new object we first check if there is room at 471 * the end total_size - (last_object_offset + last_object_size) >= 472 * alloc_size. If so we allocate new object there. 473 * 474 * When there is not enough room at the end, we start waiting for 475 * each sub object until we reach object_offset+object_size >= 476 * alloc_size, this object then become the sub object we return. 477 * 478 * Alignment can't be bigger than page size. 479 * 480 * Hole are not considered for allocation to keep things simple. 481 * Assumption is that there won't be hole (all object on same 482 * alignment). 483 */ 484 485 #define AMDGPU_SA_NUM_FENCE_LISTS 32 486 487 struct amdgpu_sa_manager { 488 wait_queue_head_t wq; 489 struct amdgpu_bo *bo; 490 struct list_head *hole; 491 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 492 struct list_head olist; 493 unsigned size; 494 uint64_t gpu_addr; 495 void *cpu_ptr; 496 uint32_t domain; 497 uint32_t align; 498 }; 499 500 /* sub-allocation buffer */ 501 struct amdgpu_sa_bo { 502 struct list_head olist; 503 struct list_head flist; 504 struct amdgpu_sa_manager *manager; 505 unsigned soffset; 506 unsigned eoffset; 507 struct dma_fence *fence; 508 }; 509 510 /* 511 * GEM objects. 512 */ 513 void amdgpu_gem_force_release(struct amdgpu_device *adev); 514 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 515 int alignment, u32 initial_domain, 516 u64 flags, bool kernel, 517 struct drm_gem_object **obj); 518 519 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 520 struct drm_device *dev, 521 struct drm_mode_create_dumb *args); 522 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 523 struct drm_device *dev, 524 uint32_t handle, uint64_t *offset_p); 525 int amdgpu_fence_slab_init(void); 526 void amdgpu_fence_slab_fini(void); 527 528 /* 529 * GART structures, functions & helpers 530 */ 531 struct amdgpu_mc; 532 533 #define AMDGPU_GPU_PAGE_SIZE 4096 534 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 535 #define AMDGPU_GPU_PAGE_SHIFT 12 536 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 537 538 struct amdgpu_gart { 539 dma_addr_t table_addr; 540 struct amdgpu_bo *robj; 541 void *ptr; 542 unsigned num_gpu_pages; 543 unsigned num_cpu_pages; 544 unsigned table_size; 545 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 546 struct page **pages; 547 #endif 548 bool ready; 549 550 /* Asic default pte flags */ 551 uint64_t gart_pte_flags; 552 553 const struct amdgpu_gart_funcs *gart_funcs; 554 }; 555 556 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 557 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 558 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 559 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 560 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 561 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 562 int amdgpu_gart_init(struct amdgpu_device *adev); 563 void amdgpu_gart_fini(struct amdgpu_device *adev); 564 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 565 int pages); 566 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 567 int pages, struct page **pagelist, 568 dma_addr_t *dma_addr, uint64_t flags); 569 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev); 570 571 /* 572 * VMHUB structures, functions & helpers 573 */ 574 struct amdgpu_vmhub { 575 uint32_t ctx0_ptb_addr_lo32; 576 uint32_t ctx0_ptb_addr_hi32; 577 uint32_t vm_inv_eng0_req; 578 uint32_t vm_inv_eng0_ack; 579 uint32_t vm_context0_cntl; 580 uint32_t vm_l2_pro_fault_status; 581 uint32_t vm_l2_pro_fault_cntl; 582 uint32_t (*get_invalidate_req)(unsigned int vm_id); 583 uint32_t (*get_vm_protection_bits)(void); 584 }; 585 586 /* 587 * GPU MC structures, functions & helpers 588 */ 589 struct amdgpu_mc { 590 resource_size_t aper_size; 591 resource_size_t aper_base; 592 resource_size_t agp_base; 593 /* for some chips with <= 32MB we need to lie 594 * about vram size near mc fb location */ 595 u64 mc_vram_size; 596 u64 visible_vram_size; 597 u64 gtt_size; 598 u64 gtt_start; 599 u64 gtt_end; 600 u64 vram_start; 601 u64 vram_end; 602 unsigned vram_width; 603 u64 real_vram_size; 604 int vram_mtrr; 605 u64 gtt_base_align; 606 u64 mc_mask; 607 const struct firmware *fw; /* MC firmware */ 608 uint32_t fw_version; 609 struct amdgpu_irq_src vm_fault; 610 uint32_t vram_type; 611 uint32_t srbm_soft_reset; 612 struct amdgpu_mode_mc_save save; 613 bool prt_warning; 614 /* apertures */ 615 u64 shared_aperture_start; 616 u64 shared_aperture_end; 617 u64 private_aperture_start; 618 u64 private_aperture_end; 619 /* protects concurrent invalidation */ 620 spinlock_t invalidate_lock; 621 const struct amdgpu_mc_funcs *mc_funcs; 622 }; 623 624 /* 625 * GPU doorbell structures, functions & helpers 626 */ 627 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 628 { 629 AMDGPU_DOORBELL_KIQ = 0x000, 630 AMDGPU_DOORBELL_HIQ = 0x001, 631 AMDGPU_DOORBELL_DIQ = 0x002, 632 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 633 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 634 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 635 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 636 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 637 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 638 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 639 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 640 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 641 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 642 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 643 AMDGPU_DOORBELL_IH = 0x1E8, 644 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 645 AMDGPU_DOORBELL_INVALID = 0xFFFF 646 } AMDGPU_DOORBELL_ASSIGNMENT; 647 648 struct amdgpu_doorbell { 649 /* doorbell mmio */ 650 resource_size_t base; 651 resource_size_t size; 652 u32 __iomem *ptr; 653 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 654 }; 655 656 /* 657 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space 658 */ 659 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT 660 { 661 /* 662 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in 663 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range. 664 * Compute related doorbells are allocated from 0x00 to 0x8a 665 */ 666 667 668 /* kernel scheduling */ 669 AMDGPU_DOORBELL64_KIQ = 0x00, 670 671 /* HSA interface queue and debug queue */ 672 AMDGPU_DOORBELL64_HIQ = 0x01, 673 AMDGPU_DOORBELL64_DIQ = 0x02, 674 675 /* Compute engines */ 676 AMDGPU_DOORBELL64_MEC_RING0 = 0x03, 677 AMDGPU_DOORBELL64_MEC_RING1 = 0x04, 678 AMDGPU_DOORBELL64_MEC_RING2 = 0x05, 679 AMDGPU_DOORBELL64_MEC_RING3 = 0x06, 680 AMDGPU_DOORBELL64_MEC_RING4 = 0x07, 681 AMDGPU_DOORBELL64_MEC_RING5 = 0x08, 682 AMDGPU_DOORBELL64_MEC_RING6 = 0x09, 683 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a, 684 685 /* User queue doorbell range (128 doorbells) */ 686 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b, 687 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a, 688 689 /* Graphics engine */ 690 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b, 691 692 /* 693 * Other graphics doorbells can be allocated here: from 0x8c to 0xef 694 * Graphics voltage island aperture 1 695 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive 696 */ 697 698 /* sDMA engines */ 699 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0, 700 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1, 701 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2, 702 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3, 703 704 /* Interrupt handler */ 705 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */ 706 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */ 707 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */ 708 709 /* VCN engine use 32 bits doorbell */ 710 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */ 711 AMDGPU_DOORBELL64_VCN2_3 = 0xF9, 712 AMDGPU_DOORBELL64_VCN4_5 = 0xFA, 713 AMDGPU_DOORBELL64_VCN6_7 = 0xFB, 714 715 /* overlap the doorbell assignment with VCN as they are mutually exclusive 716 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD 717 */ 718 AMDGPU_DOORBELL64_RING0_1 = 0xF8, 719 AMDGPU_DOORBELL64_RING2_3 = 0xF9, 720 AMDGPU_DOORBELL64_RING4_5 = 0xFA, 721 AMDGPU_DOORBELL64_RING6_7 = 0xFB, 722 723 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xFC, 724 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xFD, 725 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFE, 726 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFF, 727 728 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF, 729 AMDGPU_DOORBELL64_INVALID = 0xFFFF 730 } AMDGPU_DOORBELL64_ASSIGNMENT; 731 732 733 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 734 phys_addr_t *aperture_base, 735 size_t *aperture_size, 736 size_t *start_offset); 737 738 /* 739 * IRQS. 740 */ 741 742 struct amdgpu_flip_work { 743 struct delayed_work flip_work; 744 struct work_struct unpin_work; 745 struct amdgpu_device *adev; 746 int crtc_id; 747 u32 target_vblank; 748 uint64_t base; 749 struct drm_pending_vblank_event *event; 750 struct amdgpu_bo *old_abo; 751 struct dma_fence *excl; 752 unsigned shared_count; 753 struct dma_fence **shared; 754 struct dma_fence_cb cb; 755 bool async; 756 }; 757 758 759 /* 760 * CP & rings. 761 */ 762 763 struct amdgpu_ib { 764 struct amdgpu_sa_bo *sa_bo; 765 uint32_t length_dw; 766 uint64_t gpu_addr; 767 uint32_t *ptr; 768 uint32_t flags; 769 }; 770 771 extern const struct amd_sched_backend_ops amdgpu_sched_ops; 772 773 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs, 774 struct amdgpu_job **job, struct amdgpu_vm *vm); 775 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size, 776 struct amdgpu_job **job); 777 778 void amdgpu_job_free_resources(struct amdgpu_job *job); 779 void amdgpu_job_free(struct amdgpu_job *job); 780 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring, 781 struct amd_sched_entity *entity, void *owner, 782 struct dma_fence **f); 783 784 /* 785 * context related structures 786 */ 787 788 struct amdgpu_ctx_ring { 789 uint64_t sequence; 790 struct dma_fence **fences; 791 struct amd_sched_entity entity; 792 }; 793 794 struct amdgpu_ctx { 795 struct kref refcount; 796 struct amdgpu_device *adev; 797 unsigned reset_counter; 798 spinlock_t ring_lock; 799 struct dma_fence **fences; 800 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 801 bool preamble_presented; 802 }; 803 804 struct amdgpu_ctx_mgr { 805 struct amdgpu_device *adev; 806 struct mutex lock; 807 /* protected by lock */ 808 struct idr ctx_handles; 809 }; 810 811 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 812 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 813 814 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 815 struct dma_fence *fence); 816 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 817 struct amdgpu_ring *ring, uint64_t seq); 818 819 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 820 struct drm_file *filp); 821 822 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 823 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 824 825 /* 826 * file private structure 827 */ 828 829 struct amdgpu_fpriv { 830 struct amdgpu_vm vm; 831 struct amdgpu_bo_va *prt_va; 832 struct mutex bo_list_lock; 833 struct idr bo_list_handles; 834 struct amdgpu_ctx_mgr ctx_mgr; 835 }; 836 837 /* 838 * residency list 839 */ 840 841 struct amdgpu_bo_list { 842 struct mutex lock; 843 struct amdgpu_bo *gds_obj; 844 struct amdgpu_bo *gws_obj; 845 struct amdgpu_bo *oa_obj; 846 unsigned first_userptr; 847 unsigned num_entries; 848 struct amdgpu_bo_list_entry *array; 849 }; 850 851 struct amdgpu_bo_list * 852 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 853 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list, 854 struct list_head *validated); 855 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 856 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 857 858 /* 859 * GFX stuff 860 */ 861 #include "clearstate_defs.h" 862 863 struct amdgpu_rlc_funcs { 864 void (*enter_safe_mode)(struct amdgpu_device *adev); 865 void (*exit_safe_mode)(struct amdgpu_device *adev); 866 }; 867 868 struct amdgpu_rlc { 869 /* for power gating */ 870 struct amdgpu_bo *save_restore_obj; 871 uint64_t save_restore_gpu_addr; 872 volatile uint32_t *sr_ptr; 873 const u32 *reg_list; 874 u32 reg_list_size; 875 /* for clear state */ 876 struct amdgpu_bo *clear_state_obj; 877 uint64_t clear_state_gpu_addr; 878 volatile uint32_t *cs_ptr; 879 const struct cs_section_def *cs_data; 880 u32 clear_state_size; 881 /* for cp tables */ 882 struct amdgpu_bo *cp_table_obj; 883 uint64_t cp_table_gpu_addr; 884 volatile uint32_t *cp_table_ptr; 885 u32 cp_table_size; 886 887 /* safe mode for updating CG/PG state */ 888 bool in_safe_mode; 889 const struct amdgpu_rlc_funcs *funcs; 890 891 /* for firmware data */ 892 u32 save_and_restore_offset; 893 u32 clear_state_descriptor_offset; 894 u32 avail_scratch_ram_locations; 895 u32 reg_restore_list_size; 896 u32 reg_list_format_start; 897 u32 reg_list_format_separate_start; 898 u32 starting_offsets_start; 899 u32 reg_list_format_size_bytes; 900 u32 reg_list_size_bytes; 901 902 u32 *register_list_format; 903 u32 *register_restore; 904 }; 905 906 struct amdgpu_mec { 907 struct amdgpu_bo *hpd_eop_obj; 908 u64 hpd_eop_gpu_addr; 909 struct amdgpu_bo *mec_fw_obj; 910 u64 mec_fw_gpu_addr; 911 u32 num_pipe; 912 u32 num_mec; 913 u32 num_queue; 914 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1]; 915 }; 916 917 struct amdgpu_kiq { 918 u64 eop_gpu_addr; 919 struct amdgpu_bo *eop_obj; 920 struct amdgpu_ring ring; 921 struct amdgpu_irq_src irq; 922 }; 923 924 /* 925 * GPU scratch registers structures, functions & helpers 926 */ 927 struct amdgpu_scratch { 928 unsigned num_reg; 929 uint32_t reg_base; 930 uint32_t free_mask; 931 }; 932 933 /* 934 * GFX configurations 935 */ 936 #define AMDGPU_GFX_MAX_SE 4 937 #define AMDGPU_GFX_MAX_SH_PER_SE 2 938 939 struct amdgpu_rb_config { 940 uint32_t rb_backend_disable; 941 uint32_t user_rb_backend_disable; 942 uint32_t raster_config; 943 uint32_t raster_config_1; 944 }; 945 946 struct gb_addr_config { 947 uint16_t pipe_interleave_size; 948 uint8_t num_pipes; 949 uint8_t max_compress_frags; 950 uint8_t num_banks; 951 uint8_t num_se; 952 uint8_t num_rb_per_se; 953 }; 954 955 struct amdgpu_gfx_config { 956 unsigned max_shader_engines; 957 unsigned max_tile_pipes; 958 unsigned max_cu_per_sh; 959 unsigned max_sh_per_se; 960 unsigned max_backends_per_se; 961 unsigned max_texture_channel_caches; 962 unsigned max_gprs; 963 unsigned max_gs_threads; 964 unsigned max_hw_contexts; 965 unsigned sc_prim_fifo_size_frontend; 966 unsigned sc_prim_fifo_size_backend; 967 unsigned sc_hiz_tile_fifo_size; 968 unsigned sc_earlyz_tile_fifo_size; 969 970 unsigned num_tile_pipes; 971 unsigned backend_enable_mask; 972 unsigned mem_max_burst_length_bytes; 973 unsigned mem_row_size_in_kb; 974 unsigned shader_engine_tile_size; 975 unsigned num_gpus; 976 unsigned multi_gpu_tile_size; 977 unsigned mc_arb_ramcfg; 978 unsigned gb_addr_config; 979 unsigned num_rbs; 980 981 uint32_t tile_mode_array[32]; 982 uint32_t macrotile_mode_array[16]; 983 984 struct gb_addr_config gb_addr_config_fields; 985 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE]; 986 987 /* gfx configure feature */ 988 uint32_t double_offchip_lds_buf; 989 }; 990 991 struct amdgpu_cu_info { 992 uint32_t number; /* total active CU number */ 993 uint32_t ao_cu_mask; 994 uint32_t bitmap[4][4]; 995 }; 996 997 struct amdgpu_gfx_funcs { 998 /* get the gpu clock counter */ 999 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1000 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance); 1001 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields); 1002 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst); 1003 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst); 1004 }; 1005 1006 struct amdgpu_ngg_buf { 1007 struct amdgpu_bo *bo; 1008 uint64_t gpu_addr; 1009 uint32_t size; 1010 uint32_t bo_size; 1011 }; 1012 1013 enum { 1014 PRIM = 0, 1015 POS, 1016 CNTL, 1017 PARAM, 1018 NGG_BUF_MAX 1019 }; 1020 1021 struct amdgpu_ngg { 1022 struct amdgpu_ngg_buf buf[NGG_BUF_MAX]; 1023 uint32_t gds_reserve_addr; 1024 uint32_t gds_reserve_size; 1025 bool init; 1026 }; 1027 1028 struct amdgpu_gfx { 1029 struct mutex gpu_clock_mutex; 1030 struct amdgpu_gfx_config config; 1031 struct amdgpu_rlc rlc; 1032 struct amdgpu_mec mec; 1033 struct amdgpu_kiq kiq; 1034 struct amdgpu_scratch scratch; 1035 const struct firmware *me_fw; /* ME firmware */ 1036 uint32_t me_fw_version; 1037 const struct firmware *pfp_fw; /* PFP firmware */ 1038 uint32_t pfp_fw_version; 1039 const struct firmware *ce_fw; /* CE firmware */ 1040 uint32_t ce_fw_version; 1041 const struct firmware *rlc_fw; /* RLC firmware */ 1042 uint32_t rlc_fw_version; 1043 const struct firmware *mec_fw; /* MEC firmware */ 1044 uint32_t mec_fw_version; 1045 const struct firmware *mec2_fw; /* MEC2 firmware */ 1046 uint32_t mec2_fw_version; 1047 uint32_t me_feature_version; 1048 uint32_t ce_feature_version; 1049 uint32_t pfp_feature_version; 1050 uint32_t rlc_feature_version; 1051 uint32_t mec_feature_version; 1052 uint32_t mec2_feature_version; 1053 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1054 unsigned num_gfx_rings; 1055 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1056 unsigned num_compute_rings; 1057 struct amdgpu_irq_src eop_irq; 1058 struct amdgpu_irq_src priv_reg_irq; 1059 struct amdgpu_irq_src priv_inst_irq; 1060 /* gfx status */ 1061 uint32_t gfx_current_status; 1062 /* ce ram size*/ 1063 unsigned ce_ram_size; 1064 struct amdgpu_cu_info cu_info; 1065 const struct amdgpu_gfx_funcs *funcs; 1066 1067 /* reset mask */ 1068 uint32_t grbm_soft_reset; 1069 uint32_t srbm_soft_reset; 1070 bool in_reset; 1071 /* NGG */ 1072 struct amdgpu_ngg ngg; 1073 }; 1074 1075 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1076 unsigned size, struct amdgpu_ib *ib); 1077 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 1078 struct dma_fence *f); 1079 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 1080 struct amdgpu_ib *ibs, struct amdgpu_job *job, 1081 struct dma_fence **f); 1082 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1083 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1084 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1085 1086 /* 1087 * CS. 1088 */ 1089 struct amdgpu_cs_chunk { 1090 uint32_t chunk_id; 1091 uint32_t length_dw; 1092 void *kdata; 1093 }; 1094 1095 struct amdgpu_cs_parser { 1096 struct amdgpu_device *adev; 1097 struct drm_file *filp; 1098 struct amdgpu_ctx *ctx; 1099 1100 /* chunks */ 1101 unsigned nchunks; 1102 struct amdgpu_cs_chunk *chunks; 1103 1104 /* scheduler job object */ 1105 struct amdgpu_job *job; 1106 1107 /* buffer objects */ 1108 struct ww_acquire_ctx ticket; 1109 struct amdgpu_bo_list *bo_list; 1110 struct amdgpu_bo_list_entry vm_pd; 1111 struct list_head validated; 1112 struct dma_fence *fence; 1113 uint64_t bytes_moved_threshold; 1114 uint64_t bytes_moved; 1115 struct amdgpu_bo_list_entry *evictable; 1116 1117 /* user fence */ 1118 struct amdgpu_bo_list_entry uf_entry; 1119 }; 1120 1121 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */ 1122 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */ 1123 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */ 1124 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */ 1125 1126 struct amdgpu_job { 1127 struct amd_sched_job base; 1128 struct amdgpu_device *adev; 1129 struct amdgpu_vm *vm; 1130 struct amdgpu_ring *ring; 1131 struct amdgpu_sync sync; 1132 struct amdgpu_ib *ibs; 1133 struct dma_fence *fence; /* the hw fence */ 1134 uint32_t preamble_status; 1135 uint32_t num_ibs; 1136 void *owner; 1137 uint64_t fence_ctx; /* the fence_context this job uses */ 1138 bool vm_needs_flush; 1139 unsigned vm_id; 1140 uint64_t vm_pd_addr; 1141 uint32_t gds_base, gds_size; 1142 uint32_t gws_base, gws_size; 1143 uint32_t oa_base, oa_size; 1144 1145 /* user fence handling */ 1146 uint64_t uf_addr; 1147 uint64_t uf_sequence; 1148 1149 }; 1150 #define to_amdgpu_job(sched_job) \ 1151 container_of((sched_job), struct amdgpu_job, base) 1152 1153 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 1154 uint32_t ib_idx, int idx) 1155 { 1156 return p->job->ibs[ib_idx].ptr[idx]; 1157 } 1158 1159 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 1160 uint32_t ib_idx, int idx, 1161 uint32_t value) 1162 { 1163 p->job->ibs[ib_idx].ptr[idx] = value; 1164 } 1165 1166 /* 1167 * Writeback 1168 */ 1169 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1170 1171 struct amdgpu_wb { 1172 struct amdgpu_bo *wb_obj; 1173 volatile uint32_t *wb; 1174 uint64_t gpu_addr; 1175 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1176 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1177 }; 1178 1179 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1180 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1181 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb); 1182 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb); 1183 1184 void amdgpu_get_pcie_info(struct amdgpu_device *adev); 1185 1186 /* 1187 * SDMA 1188 */ 1189 struct amdgpu_sdma_instance { 1190 /* SDMA firmware */ 1191 const struct firmware *fw; 1192 uint32_t fw_version; 1193 uint32_t feature_version; 1194 1195 struct amdgpu_ring ring; 1196 bool burst_nop; 1197 }; 1198 1199 struct amdgpu_sdma { 1200 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1201 #ifdef CONFIG_DRM_AMDGPU_SI 1202 //SI DMA has a difference trap irq number for the second engine 1203 struct amdgpu_irq_src trap_irq_1; 1204 #endif 1205 struct amdgpu_irq_src trap_irq; 1206 struct amdgpu_irq_src illegal_inst_irq; 1207 int num_instances; 1208 uint32_t srbm_soft_reset; 1209 }; 1210 1211 /* 1212 * Firmware 1213 */ 1214 enum amdgpu_firmware_load_type { 1215 AMDGPU_FW_LOAD_DIRECT = 0, 1216 AMDGPU_FW_LOAD_SMU, 1217 AMDGPU_FW_LOAD_PSP, 1218 }; 1219 1220 struct amdgpu_firmware { 1221 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1222 enum amdgpu_firmware_load_type load_type; 1223 struct amdgpu_bo *fw_buf; 1224 unsigned int fw_size; 1225 unsigned int max_ucodes; 1226 /* firmwares are loaded by psp instead of smu from vega10 */ 1227 const struct amdgpu_psp_funcs *funcs; 1228 struct amdgpu_bo *rbuf; 1229 struct mutex mutex; 1230 }; 1231 1232 /* 1233 * Benchmarking 1234 */ 1235 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1236 1237 1238 /* 1239 * Testing 1240 */ 1241 void amdgpu_test_moves(struct amdgpu_device *adev); 1242 1243 /* 1244 * MMU Notifier 1245 */ 1246 #if defined(CONFIG_MMU_NOTIFIER) 1247 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1248 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1249 #else 1250 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1251 { 1252 return -ENODEV; 1253 } 1254 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1255 #endif 1256 1257 /* 1258 * Debugfs 1259 */ 1260 struct amdgpu_debugfs { 1261 const struct drm_info_list *files; 1262 unsigned num_files; 1263 }; 1264 1265 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1266 const struct drm_info_list *files, 1267 unsigned nfiles); 1268 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1269 1270 #if defined(CONFIG_DEBUG_FS) 1271 int amdgpu_debugfs_init(struct drm_minor *minor); 1272 #endif 1273 1274 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev); 1275 1276 /* 1277 * amdgpu smumgr functions 1278 */ 1279 struct amdgpu_smumgr_funcs { 1280 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1281 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1282 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1283 }; 1284 1285 /* 1286 * amdgpu smumgr 1287 */ 1288 struct amdgpu_smumgr { 1289 struct amdgpu_bo *toc_buf; 1290 struct amdgpu_bo *smu_buf; 1291 /* asic priv smu data */ 1292 void *priv; 1293 spinlock_t smu_lock; 1294 /* smumgr functions */ 1295 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1296 /* ucode loading complete flag */ 1297 uint32_t fw_flags; 1298 }; 1299 1300 /* 1301 * ASIC specific register table accessible by UMD 1302 */ 1303 struct amdgpu_allowed_register_entry { 1304 uint32_t reg_offset; 1305 bool untouched; 1306 bool grbm_indexed; 1307 }; 1308 1309 /* 1310 * ASIC specific functions. 1311 */ 1312 struct amdgpu_asic_funcs { 1313 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1314 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 1315 u8 *bios, u32 length_bytes); 1316 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1317 u32 sh_num, u32 reg_offset, u32 *value); 1318 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1319 int (*reset)(struct amdgpu_device *adev); 1320 /* get the reference clock */ 1321 u32 (*get_xclk)(struct amdgpu_device *adev); 1322 /* MM block clocks */ 1323 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1324 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1325 /* static power management */ 1326 int (*get_pcie_lanes)(struct amdgpu_device *adev); 1327 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 1328 /* get config memsize register */ 1329 u32 (*get_config_memsize)(struct amdgpu_device *adev); 1330 }; 1331 1332 /* 1333 * IOCTL. 1334 */ 1335 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1336 struct drm_file *filp); 1337 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1338 struct drm_file *filp); 1339 1340 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1341 struct drm_file *filp); 1342 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1343 struct drm_file *filp); 1344 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1345 struct drm_file *filp); 1346 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1347 struct drm_file *filp); 1348 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1349 struct drm_file *filp); 1350 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1351 struct drm_file *filp); 1352 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1353 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1354 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 1355 struct drm_file *filp); 1356 1357 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1358 struct drm_file *filp); 1359 1360 /* VRAM scratch page for HDP bug, default vram page */ 1361 struct amdgpu_vram_scratch { 1362 struct amdgpu_bo *robj; 1363 volatile uint32_t *ptr; 1364 u64 gpu_addr; 1365 }; 1366 1367 /* 1368 * ACPI 1369 */ 1370 struct amdgpu_atif_notification_cfg { 1371 bool enabled; 1372 int command_code; 1373 }; 1374 1375 struct amdgpu_atif_notifications { 1376 bool display_switch; 1377 bool expansion_mode_change; 1378 bool thermal_state; 1379 bool forced_power_state; 1380 bool system_power_state; 1381 bool display_conf_change; 1382 bool px_gfx_switch; 1383 bool brightness_change; 1384 bool dgpu_display_event; 1385 }; 1386 1387 struct amdgpu_atif_functions { 1388 bool system_params; 1389 bool sbios_requests; 1390 bool select_active_disp; 1391 bool lid_state; 1392 bool get_tv_standard; 1393 bool set_tv_standard; 1394 bool get_panel_expansion_mode; 1395 bool set_panel_expansion_mode; 1396 bool temperature_change; 1397 bool graphics_device_types; 1398 }; 1399 1400 struct amdgpu_atif { 1401 struct amdgpu_atif_notifications notifications; 1402 struct amdgpu_atif_functions functions; 1403 struct amdgpu_atif_notification_cfg notification_cfg; 1404 struct amdgpu_encoder *encoder_for_bl; 1405 }; 1406 1407 struct amdgpu_atcs_functions { 1408 bool get_ext_state; 1409 bool pcie_perf_req; 1410 bool pcie_dev_rdy; 1411 bool pcie_bus_width; 1412 }; 1413 1414 struct amdgpu_atcs { 1415 struct amdgpu_atcs_functions functions; 1416 }; 1417 1418 /* 1419 * CGS 1420 */ 1421 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1422 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 1423 1424 /* 1425 * Core structure, functions and helpers. 1426 */ 1427 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1428 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1429 1430 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1431 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1432 1433 struct amdgpu_device { 1434 struct device *dev; 1435 struct drm_device *ddev; 1436 struct pci_dev *pdev; 1437 1438 #ifdef CONFIG_DRM_AMD_ACP 1439 struct amdgpu_acp acp; 1440 #endif 1441 1442 /* ASIC */ 1443 enum amd_asic_type asic_type; 1444 uint32_t family; 1445 uint32_t rev_id; 1446 uint32_t external_rev_id; 1447 unsigned long flags; 1448 int usec_timeout; 1449 const struct amdgpu_asic_funcs *asic_funcs; 1450 bool shutdown; 1451 bool need_dma32; 1452 bool accel_working; 1453 struct work_struct reset_work; 1454 struct notifier_block acpi_nb; 1455 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1456 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1457 unsigned debugfs_count; 1458 #if defined(CONFIG_DEBUG_FS) 1459 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1460 #endif 1461 struct amdgpu_atif atif; 1462 struct amdgpu_atcs atcs; 1463 struct mutex srbm_mutex; 1464 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1465 struct mutex grbm_idx_mutex; 1466 struct dev_pm_domain vga_pm_domain; 1467 bool have_disp_power_ref; 1468 1469 /* BIOS */ 1470 bool is_atom_fw; 1471 uint8_t *bios; 1472 uint32_t bios_size; 1473 struct amdgpu_bo *stollen_vga_memory; 1474 uint32_t bios_scratch_reg_offset; 1475 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1476 1477 /* Register/doorbell mmio */ 1478 resource_size_t rmmio_base; 1479 resource_size_t rmmio_size; 1480 void __iomem *rmmio; 1481 /* protects concurrent MM_INDEX/DATA based register access */ 1482 spinlock_t mmio_idx_lock; 1483 /* protects concurrent SMC based register access */ 1484 spinlock_t smc_idx_lock; 1485 amdgpu_rreg_t smc_rreg; 1486 amdgpu_wreg_t smc_wreg; 1487 /* protects concurrent PCIE register access */ 1488 spinlock_t pcie_idx_lock; 1489 amdgpu_rreg_t pcie_rreg; 1490 amdgpu_wreg_t pcie_wreg; 1491 amdgpu_rreg_t pciep_rreg; 1492 amdgpu_wreg_t pciep_wreg; 1493 /* protects concurrent UVD register access */ 1494 spinlock_t uvd_ctx_idx_lock; 1495 amdgpu_rreg_t uvd_ctx_rreg; 1496 amdgpu_wreg_t uvd_ctx_wreg; 1497 /* protects concurrent DIDT register access */ 1498 spinlock_t didt_idx_lock; 1499 amdgpu_rreg_t didt_rreg; 1500 amdgpu_wreg_t didt_wreg; 1501 /* protects concurrent gc_cac register access */ 1502 spinlock_t gc_cac_idx_lock; 1503 amdgpu_rreg_t gc_cac_rreg; 1504 amdgpu_wreg_t gc_cac_wreg; 1505 /* protects concurrent ENDPOINT (audio) register access */ 1506 spinlock_t audio_endpt_idx_lock; 1507 amdgpu_block_rreg_t audio_endpt_rreg; 1508 amdgpu_block_wreg_t audio_endpt_wreg; 1509 void __iomem *rio_mem; 1510 resource_size_t rio_mem_size; 1511 struct amdgpu_doorbell doorbell; 1512 1513 /* clock/pll info */ 1514 struct amdgpu_clock clock; 1515 1516 /* MC */ 1517 struct amdgpu_mc mc; 1518 struct amdgpu_gart gart; 1519 struct amdgpu_dummy_page dummy_page; 1520 struct amdgpu_vm_manager vm_manager; 1521 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 1522 1523 /* memory management */ 1524 struct amdgpu_mman mman; 1525 struct amdgpu_vram_scratch vram_scratch; 1526 struct amdgpu_wb wb; 1527 atomic64_t vram_usage; 1528 atomic64_t vram_vis_usage; 1529 atomic64_t gtt_usage; 1530 atomic64_t num_bytes_moved; 1531 atomic64_t num_evictions; 1532 atomic_t gpu_reset_counter; 1533 1534 /* data for buffer migration throttling */ 1535 struct { 1536 spinlock_t lock; 1537 s64 last_update_us; 1538 s64 accum_us; /* accumulated microseconds */ 1539 u32 log2_max_MBps; 1540 } mm_stats; 1541 1542 /* display */ 1543 bool enable_virtual_display; 1544 struct amdgpu_mode_info mode_info; 1545 struct work_struct hotplug_work; 1546 struct amdgpu_irq_src crtc_irq; 1547 struct amdgpu_irq_src pageflip_irq; 1548 struct amdgpu_irq_src hpd_irq; 1549 1550 /* rings */ 1551 u64 fence_context; 1552 unsigned num_rings; 1553 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 1554 bool ib_pool_ready; 1555 struct amdgpu_sa_manager ring_tmp_bo; 1556 1557 /* interrupts */ 1558 struct amdgpu_irq irq; 1559 1560 /* powerplay */ 1561 struct amd_powerplay powerplay; 1562 bool pp_enabled; 1563 bool pp_force_state_enabled; 1564 1565 /* dpm */ 1566 struct amdgpu_pm pm; 1567 u32 cg_flags; 1568 u32 pg_flags; 1569 1570 /* amdgpu smumgr */ 1571 struct amdgpu_smumgr smu; 1572 1573 /* gfx */ 1574 struct amdgpu_gfx gfx; 1575 1576 /* sdma */ 1577 struct amdgpu_sdma sdma; 1578 1579 /* uvd */ 1580 struct amdgpu_uvd uvd; 1581 1582 /* vce */ 1583 struct amdgpu_vce vce; 1584 1585 /* firmwares */ 1586 struct amdgpu_firmware firmware; 1587 1588 /* PSP */ 1589 struct psp_context psp; 1590 1591 /* GDS */ 1592 struct amdgpu_gds gds; 1593 1594 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 1595 int num_ip_blocks; 1596 struct mutex mn_lock; 1597 DECLARE_HASHTABLE(mn_hash, 7); 1598 1599 /* tracking pinned memory */ 1600 u64 vram_pin_size; 1601 u64 invisible_pin_size; 1602 u64 gart_pin_size; 1603 1604 /* amdkfd interface */ 1605 struct kfd_dev *kfd; 1606 1607 struct amdgpu_virt virt; 1608 1609 /* link all shadow bo */ 1610 struct list_head shadow_list; 1611 struct mutex shadow_list_lock; 1612 /* link all gtt */ 1613 spinlock_t gtt_list_lock; 1614 struct list_head gtt_list; 1615 1616 /* record hw reset is performed */ 1617 bool has_hw_reset; 1618 1619 }; 1620 1621 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1622 { 1623 return container_of(bdev, struct amdgpu_device, mman.bdev); 1624 } 1625 1626 bool amdgpu_device_is_px(struct drm_device *dev); 1627 int amdgpu_device_init(struct amdgpu_device *adev, 1628 struct drm_device *ddev, 1629 struct pci_dev *pdev, 1630 uint32_t flags); 1631 void amdgpu_device_fini(struct amdgpu_device *adev); 1632 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1633 1634 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1635 uint32_t acc_flags); 1636 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1637 uint32_t acc_flags); 1638 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1639 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1640 1641 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 1642 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 1643 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); 1644 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v); 1645 1646 /* 1647 * Registers read & write functions. 1648 */ 1649 1650 #define AMDGPU_REGS_IDX (1<<0) 1651 #define AMDGPU_REGS_NO_KIQ (1<<1) 1652 1653 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1654 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1655 1656 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1657 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1658 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1659 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1660 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1661 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1662 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1663 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1664 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1665 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1666 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1667 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1668 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1669 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1670 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1671 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1672 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1673 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1674 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1675 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1676 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1677 #define WREG32_P(reg, val, mask) \ 1678 do { \ 1679 uint32_t tmp_ = RREG32(reg); \ 1680 tmp_ &= (mask); \ 1681 tmp_ |= ((val) & ~(mask)); \ 1682 WREG32(reg, tmp_); \ 1683 } while (0) 1684 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1685 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1686 #define WREG32_PLL_P(reg, val, mask) \ 1687 do { \ 1688 uint32_t tmp_ = RREG32_PLL(reg); \ 1689 tmp_ &= (mask); \ 1690 tmp_ |= ((val) & ~(mask)); \ 1691 WREG32_PLL(reg, tmp_); \ 1692 } while (0) 1693 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1694 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1695 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1696 1697 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 1698 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 1699 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index)) 1700 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v)) 1701 1702 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1703 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1704 1705 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1706 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1707 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1708 1709 #define REG_GET_FIELD(value, reg, field) \ 1710 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1711 1712 #define WREG32_FIELD(reg, field, val) \ 1713 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1714 1715 /* 1716 * BIOS helpers. 1717 */ 1718 #define RBIOS8(i) (adev->bios[i]) 1719 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1720 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1721 1722 /* 1723 * RING helpers. 1724 */ 1725 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 1726 { 1727 if (ring->count_dw <= 0) 1728 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1729 ring->ring[ring->wptr++ & ring->buf_mask] = v; 1730 ring->wptr &= ring->ptr_mask; 1731 ring->count_dw--; 1732 } 1733 1734 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw) 1735 { 1736 unsigned occupied, chunk1, chunk2; 1737 void *dst; 1738 1739 if (ring->count_dw < count_dw) { 1740 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 1741 } else { 1742 occupied = ring->wptr & ring->buf_mask; 1743 dst = (void *)&ring->ring[occupied]; 1744 chunk1 = ring->buf_mask + 1 - occupied; 1745 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 1746 chunk2 = count_dw - chunk1; 1747 chunk1 <<= 2; 1748 chunk2 <<= 2; 1749 1750 if (chunk1) 1751 memcpy(dst, src, chunk1); 1752 1753 if (chunk2) { 1754 src += chunk1; 1755 dst = (void *)ring->ring; 1756 memcpy(dst, src, chunk2); 1757 } 1758 1759 ring->wptr += count_dw; 1760 ring->wptr &= ring->ptr_mask; 1761 ring->count_dw -= count_dw; 1762 } 1763 } 1764 1765 static inline struct amdgpu_sdma_instance * 1766 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 1767 { 1768 struct amdgpu_device *adev = ring->adev; 1769 int i; 1770 1771 for (i = 0; i < adev->sdma.num_instances; i++) 1772 if (&adev->sdma.instance[i].ring == ring) 1773 break; 1774 1775 if (i < AMDGPU_MAX_SDMA_INSTANCES) 1776 return &adev->sdma.instance[i]; 1777 else 1778 return NULL; 1779 } 1780 1781 /* 1782 * ASICs macro. 1783 */ 1784 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1785 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1786 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1787 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1788 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1789 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1790 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1791 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1792 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1793 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1794 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1795 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1796 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 1797 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 1798 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 1799 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr))) 1800 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 1801 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags)) 1802 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 1803 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 1804 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 1805 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 1806 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 1807 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 1808 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c)) 1809 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 1810 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 1811 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 1812 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 1813 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 1814 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r)) 1815 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 1816 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 1817 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 1818 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 1819 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 1820 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 1821 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 1822 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 1823 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 1824 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 1825 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 1826 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 1827 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 1828 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 1829 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 1830 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 1831 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 1832 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 1833 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 1834 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async)) 1835 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 1836 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 1837 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 1838 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 1839 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 1840 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 1841 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 1842 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev)) 1843 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance)) 1844 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 1845 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) 1846 1847 /* Common functions */ 1848 int amdgpu_gpu_reset(struct amdgpu_device *adev); 1849 bool amdgpu_need_backup(struct amdgpu_device *adev); 1850 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 1851 bool amdgpu_need_post(struct amdgpu_device *adev); 1852 void amdgpu_update_display_priority(struct amdgpu_device *adev); 1853 1854 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 1855 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 1856 u32 ip_instance, u32 ring, 1857 struct amdgpu_ring **out_ring); 1858 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes); 1859 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain); 1860 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 1861 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages); 1862 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 1863 uint32_t flags); 1864 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 1865 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); 1866 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 1867 unsigned long end); 1868 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, 1869 int *last_invalidated); 1870 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 1871 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 1872 struct ttm_mem_reg *mem); 1873 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 1874 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 1875 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 1876 int amdgpu_ttm_init(struct amdgpu_device *adev); 1877 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1878 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 1879 const u32 *registers, 1880 const u32 array_size); 1881 1882 bool amdgpu_device_is_px(struct drm_device *dev); 1883 /* atpx handler */ 1884 #if defined(CONFIG_VGA_SWITCHEROO) 1885 void amdgpu_register_atpx_handler(void); 1886 void amdgpu_unregister_atpx_handler(void); 1887 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1888 bool amdgpu_is_atpx_hybrid(void); 1889 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1890 #else 1891 static inline void amdgpu_register_atpx_handler(void) {} 1892 static inline void amdgpu_unregister_atpx_handler(void) {} 1893 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1894 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1895 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1896 #endif 1897 1898 /* 1899 * KMS 1900 */ 1901 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1902 extern const int amdgpu_max_kms_ioctl; 1903 1904 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1905 void amdgpu_driver_unload_kms(struct drm_device *dev); 1906 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1907 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1908 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1909 struct drm_file *file_priv); 1910 int amdgpu_suspend(struct amdgpu_device *adev); 1911 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1912 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1913 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1914 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1915 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1916 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 1917 int *max_error, 1918 struct timeval *vblank_time, 1919 unsigned flags); 1920 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1921 unsigned long arg); 1922 1923 /* 1924 * functions used by amdgpu_encoder.c 1925 */ 1926 struct amdgpu_afmt_acr { 1927 u32 clock; 1928 1929 int n_32khz; 1930 int cts_32khz; 1931 1932 int n_44_1khz; 1933 int cts_44_1khz; 1934 1935 int n_48khz; 1936 int cts_48khz; 1937 1938 }; 1939 1940 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1941 1942 /* amdgpu_acpi.c */ 1943 #if defined(CONFIG_ACPI) 1944 int amdgpu_acpi_init(struct amdgpu_device *adev); 1945 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1946 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1947 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1948 u8 perf_req, bool advertise); 1949 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1950 #else 1951 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1952 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1953 #endif 1954 1955 struct amdgpu_bo_va_mapping * 1956 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1957 uint64_t addr, struct amdgpu_bo **bo); 1958 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser); 1959 1960 #include "amdgpu_object.h" 1961 #endif 1962