1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 #include "gpu_scheduler.h" 57 58 /* 59 * Modules parameters. 60 */ 61 extern int amdgpu_modeset; 62 extern int amdgpu_vram_limit; 63 extern int amdgpu_gart_size; 64 extern int amdgpu_benchmarking; 65 extern int amdgpu_testing; 66 extern int amdgpu_audio; 67 extern int amdgpu_disp_priority; 68 extern int amdgpu_hw_i2c; 69 extern int amdgpu_pcie_gen2; 70 extern int amdgpu_msi; 71 extern int amdgpu_lockup_timeout; 72 extern int amdgpu_dpm; 73 extern int amdgpu_smc_load_fw; 74 extern int amdgpu_aspm; 75 extern int amdgpu_runtime_pm; 76 extern int amdgpu_hard_reset; 77 extern unsigned amdgpu_ip_block_mask; 78 extern int amdgpu_bapm; 79 extern int amdgpu_deep_color; 80 extern int amdgpu_vm_size; 81 extern int amdgpu_vm_block_size; 82 extern int amdgpu_enable_scheduler; 83 extern int amdgpu_sched_jobs; 84 extern int amdgpu_sched_hw_submission; 85 86 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 87 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 88 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 89 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 90 #define AMDGPU_IB_POOL_SIZE 16 91 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 92 #define AMDGPUFB_CONN_LIMIT 4 93 #define AMDGPU_BIOS_NUM_SCRATCH 8 94 95 /* max number of rings */ 96 #define AMDGPU_MAX_RINGS 16 97 #define AMDGPU_MAX_GFX_RINGS 1 98 #define AMDGPU_MAX_COMPUTE_RINGS 8 99 #define AMDGPU_MAX_VCE_RINGS 2 100 101 /* number of hw syncs before falling back on blocking */ 102 #define AMDGPU_NUM_SYNCS 4 103 104 /* hardcode that limit for now */ 105 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 106 107 /* hard reset data */ 108 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 109 110 /* reset flags */ 111 #define AMDGPU_RESET_GFX (1 << 0) 112 #define AMDGPU_RESET_COMPUTE (1 << 1) 113 #define AMDGPU_RESET_DMA (1 << 2) 114 #define AMDGPU_RESET_CP (1 << 3) 115 #define AMDGPU_RESET_GRBM (1 << 4) 116 #define AMDGPU_RESET_DMA1 (1 << 5) 117 #define AMDGPU_RESET_RLC (1 << 6) 118 #define AMDGPU_RESET_SEM (1 << 7) 119 #define AMDGPU_RESET_IH (1 << 8) 120 #define AMDGPU_RESET_VMC (1 << 9) 121 #define AMDGPU_RESET_MC (1 << 10) 122 #define AMDGPU_RESET_DISPLAY (1 << 11) 123 #define AMDGPU_RESET_UVD (1 << 12) 124 #define AMDGPU_RESET_VCE (1 << 13) 125 #define AMDGPU_RESET_VCE1 (1 << 14) 126 127 /* CG block flags */ 128 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 129 #define AMDGPU_CG_BLOCK_MC (1 << 1) 130 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 131 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 132 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 133 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 134 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 135 136 /* CG flags */ 137 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 138 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 139 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 140 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 141 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 142 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 143 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 144 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 145 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 146 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 147 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 148 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 149 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 150 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 151 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 152 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 153 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 154 155 /* PG flags */ 156 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 157 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 158 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 159 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 160 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 161 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 162 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 163 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 164 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 165 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 166 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 167 168 /* GFX current status */ 169 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 170 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 171 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 172 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 173 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 174 175 /* max cursor sizes (in pixels) */ 176 #define CIK_CURSOR_WIDTH 128 177 #define CIK_CURSOR_HEIGHT 128 178 179 struct amdgpu_device; 180 struct amdgpu_fence; 181 struct amdgpu_ib; 182 struct amdgpu_vm; 183 struct amdgpu_ring; 184 struct amdgpu_semaphore; 185 struct amdgpu_cs_parser; 186 struct amdgpu_job; 187 struct amdgpu_irq_src; 188 struct amdgpu_fpriv; 189 190 enum amdgpu_cp_irq { 191 AMDGPU_CP_IRQ_GFX_EOP = 0, 192 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 193 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 194 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 195 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 196 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 200 201 AMDGPU_CP_IRQ_LAST 202 }; 203 204 enum amdgpu_sdma_irq { 205 AMDGPU_SDMA_IRQ_TRAP0 = 0, 206 AMDGPU_SDMA_IRQ_TRAP1, 207 208 AMDGPU_SDMA_IRQ_LAST 209 }; 210 211 enum amdgpu_thermal_irq { 212 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 213 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 214 215 AMDGPU_THERMAL_IRQ_LAST 216 }; 217 218 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 219 enum amd_ip_block_type block_type, 220 enum amd_clockgating_state state); 221 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 222 enum amd_ip_block_type block_type, 223 enum amd_powergating_state state); 224 225 struct amdgpu_ip_block_version { 226 enum amd_ip_block_type type; 227 u32 major; 228 u32 minor; 229 u32 rev; 230 const struct amd_ip_funcs *funcs; 231 }; 232 233 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 234 enum amd_ip_block_type type, 235 u32 major, u32 minor); 236 237 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 238 struct amdgpu_device *adev, 239 enum amd_ip_block_type type); 240 241 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 242 struct amdgpu_buffer_funcs { 243 /* maximum bytes in a single operation */ 244 uint32_t copy_max_bytes; 245 246 /* number of dw to reserve per operation */ 247 unsigned copy_num_dw; 248 249 /* used for buffer migration */ 250 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 251 /* src addr in bytes */ 252 uint64_t src_offset, 253 /* dst addr in bytes */ 254 uint64_t dst_offset, 255 /* number of byte to transfer */ 256 uint32_t byte_count); 257 258 /* maximum bytes in a single operation */ 259 uint32_t fill_max_bytes; 260 261 /* number of dw to reserve per operation */ 262 unsigned fill_num_dw; 263 264 /* used for buffer clearing */ 265 void (*emit_fill_buffer)(struct amdgpu_ring *ring, 266 /* value to write to memory */ 267 uint32_t src_data, 268 /* dst addr in bytes */ 269 uint64_t dst_offset, 270 /* number of byte to fill */ 271 uint32_t byte_count); 272 }; 273 274 /* provided by hw blocks that can write ptes, e.g., sdma */ 275 struct amdgpu_vm_pte_funcs { 276 /* copy pte entries from GART */ 277 void (*copy_pte)(struct amdgpu_ib *ib, 278 uint64_t pe, uint64_t src, 279 unsigned count); 280 /* write pte one entry at a time with addr mapping */ 281 void (*write_pte)(struct amdgpu_ib *ib, 282 uint64_t pe, 283 uint64_t addr, unsigned count, 284 uint32_t incr, uint32_t flags); 285 /* for linear pte/pde updates without addr mapping */ 286 void (*set_pte_pde)(struct amdgpu_ib *ib, 287 uint64_t pe, 288 uint64_t addr, unsigned count, 289 uint32_t incr, uint32_t flags); 290 /* pad the indirect buffer to the necessary number of dw */ 291 void (*pad_ib)(struct amdgpu_ib *ib); 292 }; 293 294 /* provided by the gmc block */ 295 struct amdgpu_gart_funcs { 296 /* flush the vm tlb via mmio */ 297 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 298 uint32_t vmid); 299 /* write pte/pde updates using the cpu */ 300 int (*set_pte_pde)(struct amdgpu_device *adev, 301 void *cpu_pt_addr, /* cpu addr of page table */ 302 uint32_t gpu_page_idx, /* pte/pde to update */ 303 uint64_t addr, /* addr to write into pte/pde */ 304 uint32_t flags); /* access flags */ 305 }; 306 307 /* provided by the ih block */ 308 struct amdgpu_ih_funcs { 309 /* ring read/write ptr handling, called from interrupt context */ 310 u32 (*get_wptr)(struct amdgpu_device *adev); 311 void (*decode_iv)(struct amdgpu_device *adev, 312 struct amdgpu_iv_entry *entry); 313 void (*set_rptr)(struct amdgpu_device *adev); 314 }; 315 316 /* provided by hw blocks that expose a ring buffer for commands */ 317 struct amdgpu_ring_funcs { 318 /* ring read/write ptr handling */ 319 u32 (*get_rptr)(struct amdgpu_ring *ring); 320 u32 (*get_wptr)(struct amdgpu_ring *ring); 321 void (*set_wptr)(struct amdgpu_ring *ring); 322 /* validating and patching of IBs */ 323 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 324 /* command emit functions */ 325 void (*emit_ib)(struct amdgpu_ring *ring, 326 struct amdgpu_ib *ib); 327 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 328 uint64_t seq, unsigned flags); 329 bool (*emit_semaphore)(struct amdgpu_ring *ring, 330 struct amdgpu_semaphore *semaphore, 331 bool emit_wait); 332 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 333 uint64_t pd_addr); 334 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 335 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 336 uint32_t gds_base, uint32_t gds_size, 337 uint32_t gws_base, uint32_t gws_size, 338 uint32_t oa_base, uint32_t oa_size); 339 /* testing functions */ 340 int (*test_ring)(struct amdgpu_ring *ring); 341 int (*test_ib)(struct amdgpu_ring *ring); 342 bool (*is_lockup)(struct amdgpu_ring *ring); 343 }; 344 345 /* 346 * BIOS. 347 */ 348 bool amdgpu_get_bios(struct amdgpu_device *adev); 349 bool amdgpu_read_bios(struct amdgpu_device *adev); 350 351 /* 352 * Dummy page 353 */ 354 struct amdgpu_dummy_page { 355 struct page *page; 356 dma_addr_t addr; 357 }; 358 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 359 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 360 361 362 /* 363 * Clocks 364 */ 365 366 #define AMDGPU_MAX_PPLL 3 367 368 struct amdgpu_clock { 369 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 370 struct amdgpu_pll spll; 371 struct amdgpu_pll mpll; 372 /* 10 Khz units */ 373 uint32_t default_mclk; 374 uint32_t default_sclk; 375 uint32_t default_dispclk; 376 uint32_t current_dispclk; 377 uint32_t dp_extclk; 378 uint32_t max_pixel_clock; 379 }; 380 381 /* 382 * Fences. 383 */ 384 struct amdgpu_fence_driver { 385 struct amdgpu_ring *ring; 386 uint64_t gpu_addr; 387 volatile uint32_t *cpu_addr; 388 /* sync_seq is protected by ring emission lock */ 389 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 390 atomic64_t last_seq; 391 bool initialized; 392 struct amdgpu_irq_src *irq_src; 393 unsigned irq_type; 394 struct delayed_work lockup_work; 395 wait_queue_head_t fence_queue; 396 }; 397 398 /* some special values for the owner field */ 399 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 400 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 401 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 402 403 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 404 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 405 406 struct amdgpu_fence { 407 struct fence base; 408 409 /* RB, DMA, etc. */ 410 struct amdgpu_ring *ring; 411 uint64_t seq; 412 413 /* filp or special value for fence creator */ 414 void *owner; 415 416 wait_queue_t fence_wake; 417 }; 418 419 struct amdgpu_user_fence { 420 /* write-back bo */ 421 struct amdgpu_bo *bo; 422 /* write-back address offset to bo start */ 423 uint32_t offset; 424 }; 425 426 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 427 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 428 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 429 430 void amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 431 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 432 struct amdgpu_irq_src *irq_src, 433 unsigned irq_type); 434 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 435 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 436 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 437 struct amdgpu_fence **fence); 438 void amdgpu_fence_process(struct amdgpu_ring *ring); 439 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 440 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 441 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 442 443 signed long amdgpu_fence_wait_multiple(struct amdgpu_device *adev, 444 struct fence **array, 445 uint32_t count, 446 bool wait_all, 447 bool intr, 448 signed long t); 449 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); 450 void amdgpu_fence_unref(struct amdgpu_fence **fence); 451 452 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 453 struct amdgpu_ring *ring); 454 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 455 struct amdgpu_ring *ring); 456 457 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, 458 struct amdgpu_fence *b) 459 { 460 if (!a) { 461 return b; 462 } 463 464 if (!b) { 465 return a; 466 } 467 468 BUG_ON(a->ring != b->ring); 469 470 if (a->seq > b->seq) { 471 return a; 472 } else { 473 return b; 474 } 475 } 476 477 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, 478 struct amdgpu_fence *b) 479 { 480 if (!a) { 481 return false; 482 } 483 484 if (!b) { 485 return true; 486 } 487 488 BUG_ON(a->ring != b->ring); 489 490 return a->seq < b->seq; 491 } 492 493 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 494 void *owner, struct amdgpu_fence **fence); 495 496 /* 497 * TTM. 498 */ 499 struct amdgpu_mman { 500 struct ttm_bo_global_ref bo_global_ref; 501 struct drm_global_reference mem_global_ref; 502 struct ttm_bo_device bdev; 503 bool mem_global_referenced; 504 bool initialized; 505 506 #if defined(CONFIG_DEBUG_FS) 507 struct dentry *vram; 508 struct dentry *gtt; 509 #endif 510 511 /* buffer handling */ 512 const struct amdgpu_buffer_funcs *buffer_funcs; 513 struct amdgpu_ring *buffer_funcs_ring; 514 }; 515 516 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 517 uint64_t src_offset, 518 uint64_t dst_offset, 519 uint32_t byte_count, 520 struct reservation_object *resv, 521 struct fence **fence); 522 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 523 524 struct amdgpu_bo_list_entry { 525 struct amdgpu_bo *robj; 526 struct ttm_validate_buffer tv; 527 struct amdgpu_bo_va *bo_va; 528 unsigned prefered_domains; 529 unsigned allowed_domains; 530 uint32_t priority; 531 }; 532 533 struct amdgpu_bo_va_mapping { 534 struct list_head list; 535 struct interval_tree_node it; 536 uint64_t offset; 537 uint32_t flags; 538 }; 539 540 /* bo virtual addresses in a specific vm */ 541 struct amdgpu_bo_va { 542 /* protected by bo being reserved */ 543 struct list_head bo_list; 544 struct fence *last_pt_update; 545 unsigned ref_count; 546 547 /* protected by vm mutex and spinlock */ 548 struct list_head vm_status; 549 550 /* mappings for this bo_va */ 551 struct list_head invalids; 552 struct list_head valids; 553 554 /* constant after initialization */ 555 struct amdgpu_vm *vm; 556 struct amdgpu_bo *bo; 557 }; 558 559 #define AMDGPU_GEM_DOMAIN_MAX 0x3 560 561 struct amdgpu_bo { 562 /* Protected by gem.mutex */ 563 struct list_head list; 564 /* Protected by tbo.reserved */ 565 u32 initial_domain; 566 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 567 struct ttm_placement placement; 568 struct ttm_buffer_object tbo; 569 struct ttm_bo_kmap_obj kmap; 570 u64 flags; 571 unsigned pin_count; 572 void *kptr; 573 u64 tiling_flags; 574 u64 metadata_flags; 575 void *metadata; 576 u32 metadata_size; 577 /* list of all virtual address to which this bo 578 * is associated to 579 */ 580 struct list_head va; 581 /* Constant after initialization */ 582 struct amdgpu_device *adev; 583 struct drm_gem_object gem_base; 584 585 struct ttm_bo_kmap_obj dma_buf_vmap; 586 pid_t pid; 587 struct amdgpu_mn *mn; 588 struct list_head mn_list; 589 }; 590 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 591 592 void amdgpu_gem_object_free(struct drm_gem_object *obj); 593 int amdgpu_gem_object_open(struct drm_gem_object *obj, 594 struct drm_file *file_priv); 595 void amdgpu_gem_object_close(struct drm_gem_object *obj, 596 struct drm_file *file_priv); 597 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 598 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 599 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 600 struct dma_buf_attachment *attach, 601 struct sg_table *sg); 602 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 603 struct drm_gem_object *gobj, 604 int flags); 605 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 606 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 607 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 608 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 609 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 610 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 611 612 /* sub-allocation manager, it has to be protected by another lock. 613 * By conception this is an helper for other part of the driver 614 * like the indirect buffer or semaphore, which both have their 615 * locking. 616 * 617 * Principe is simple, we keep a list of sub allocation in offset 618 * order (first entry has offset == 0, last entry has the highest 619 * offset). 620 * 621 * When allocating new object we first check if there is room at 622 * the end total_size - (last_object_offset + last_object_size) >= 623 * alloc_size. If so we allocate new object there. 624 * 625 * When there is not enough room at the end, we start waiting for 626 * each sub object until we reach object_offset+object_size >= 627 * alloc_size, this object then become the sub object we return. 628 * 629 * Alignment can't be bigger than page size. 630 * 631 * Hole are not considered for allocation to keep things simple. 632 * Assumption is that there won't be hole (all object on same 633 * alignment). 634 */ 635 struct amdgpu_sa_manager { 636 wait_queue_head_t wq; 637 struct amdgpu_bo *bo; 638 struct list_head *hole; 639 struct list_head flist[AMDGPU_MAX_RINGS]; 640 struct list_head olist; 641 unsigned size; 642 uint64_t gpu_addr; 643 void *cpu_ptr; 644 uint32_t domain; 645 uint32_t align; 646 }; 647 648 struct amdgpu_sa_bo; 649 650 /* sub-allocation buffer */ 651 struct amdgpu_sa_bo { 652 struct list_head olist; 653 struct list_head flist; 654 struct amdgpu_sa_manager *manager; 655 unsigned soffset; 656 unsigned eoffset; 657 struct fence *fence; 658 }; 659 660 /* 661 * GEM objects. 662 */ 663 struct amdgpu_gem { 664 struct mutex mutex; 665 struct list_head objects; 666 }; 667 668 int amdgpu_gem_init(struct amdgpu_device *adev); 669 void amdgpu_gem_fini(struct amdgpu_device *adev); 670 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 671 int alignment, u32 initial_domain, 672 u64 flags, bool kernel, 673 struct drm_gem_object **obj); 674 675 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 676 struct drm_device *dev, 677 struct drm_mode_create_dumb *args); 678 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 679 struct drm_device *dev, 680 uint32_t handle, uint64_t *offset_p); 681 682 /* 683 * Semaphores. 684 */ 685 struct amdgpu_semaphore { 686 struct amdgpu_sa_bo *sa_bo; 687 signed waiters; 688 uint64_t gpu_addr; 689 }; 690 691 int amdgpu_semaphore_create(struct amdgpu_device *adev, 692 struct amdgpu_semaphore **semaphore); 693 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 694 struct amdgpu_semaphore *semaphore); 695 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 696 struct amdgpu_semaphore *semaphore); 697 void amdgpu_semaphore_free(struct amdgpu_device *adev, 698 struct amdgpu_semaphore **semaphore, 699 struct fence *fence); 700 701 /* 702 * Synchronization 703 */ 704 struct amdgpu_sync { 705 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 706 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; 707 DECLARE_HASHTABLE(fences, 4); 708 struct fence *last_vm_update; 709 }; 710 711 void amdgpu_sync_create(struct amdgpu_sync *sync); 712 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 713 struct fence *f); 714 int amdgpu_sync_resv(struct amdgpu_device *adev, 715 struct amdgpu_sync *sync, 716 struct reservation_object *resv, 717 void *owner); 718 int amdgpu_sync_rings(struct amdgpu_sync *sync, 719 struct amdgpu_ring *ring); 720 int amdgpu_sync_wait(struct amdgpu_sync *sync); 721 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 722 struct fence *fence); 723 724 /* 725 * GART structures, functions & helpers 726 */ 727 struct amdgpu_mc; 728 729 #define AMDGPU_GPU_PAGE_SIZE 4096 730 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 731 #define AMDGPU_GPU_PAGE_SHIFT 12 732 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 733 734 struct amdgpu_gart { 735 dma_addr_t table_addr; 736 struct amdgpu_bo *robj; 737 void *ptr; 738 unsigned num_gpu_pages; 739 unsigned num_cpu_pages; 740 unsigned table_size; 741 struct page **pages; 742 dma_addr_t *pages_addr; 743 bool ready; 744 const struct amdgpu_gart_funcs *gart_funcs; 745 }; 746 747 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 748 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 749 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 750 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 751 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 752 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 753 int amdgpu_gart_init(struct amdgpu_device *adev); 754 void amdgpu_gart_fini(struct amdgpu_device *adev); 755 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 756 int pages); 757 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 758 int pages, struct page **pagelist, 759 dma_addr_t *dma_addr, uint32_t flags); 760 761 /* 762 * GPU MC structures, functions & helpers 763 */ 764 struct amdgpu_mc { 765 resource_size_t aper_size; 766 resource_size_t aper_base; 767 resource_size_t agp_base; 768 /* for some chips with <= 32MB we need to lie 769 * about vram size near mc fb location */ 770 u64 mc_vram_size; 771 u64 visible_vram_size; 772 u64 gtt_size; 773 u64 gtt_start; 774 u64 gtt_end; 775 u64 vram_start; 776 u64 vram_end; 777 unsigned vram_width; 778 u64 real_vram_size; 779 int vram_mtrr; 780 u64 gtt_base_align; 781 u64 mc_mask; 782 const struct firmware *fw; /* MC firmware */ 783 uint32_t fw_version; 784 struct amdgpu_irq_src vm_fault; 785 uint32_t vram_type; 786 }; 787 788 /* 789 * GPU doorbell structures, functions & helpers 790 */ 791 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 792 { 793 AMDGPU_DOORBELL_KIQ = 0x000, 794 AMDGPU_DOORBELL_HIQ = 0x001, 795 AMDGPU_DOORBELL_DIQ = 0x002, 796 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 797 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 798 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 799 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 800 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 801 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 802 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 803 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 804 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 805 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 806 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 807 AMDGPU_DOORBELL_IH = 0x1E8, 808 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 809 AMDGPU_DOORBELL_INVALID = 0xFFFF 810 } AMDGPU_DOORBELL_ASSIGNMENT; 811 812 struct amdgpu_doorbell { 813 /* doorbell mmio */ 814 resource_size_t base; 815 resource_size_t size; 816 u32 __iomem *ptr; 817 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 818 }; 819 820 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 821 phys_addr_t *aperture_base, 822 size_t *aperture_size, 823 size_t *start_offset); 824 825 /* 826 * IRQS. 827 */ 828 829 struct amdgpu_flip_work { 830 struct work_struct flip_work; 831 struct work_struct unpin_work; 832 struct amdgpu_device *adev; 833 int crtc_id; 834 uint64_t base; 835 struct drm_pending_vblank_event *event; 836 struct amdgpu_bo *old_rbo; 837 struct fence *excl; 838 unsigned shared_count; 839 struct fence **shared; 840 }; 841 842 843 /* 844 * CP & rings. 845 */ 846 847 struct amdgpu_ib { 848 struct amdgpu_sa_bo *sa_bo; 849 uint32_t length_dw; 850 uint64_t gpu_addr; 851 uint32_t *ptr; 852 struct amdgpu_ring *ring; 853 struct amdgpu_fence *fence; 854 struct amdgpu_user_fence *user; 855 struct amdgpu_vm *vm; 856 struct amdgpu_ctx *ctx; 857 struct amdgpu_sync sync; 858 uint32_t gds_base, gds_size; 859 uint32_t gws_base, gws_size; 860 uint32_t oa_base, oa_size; 861 uint32_t flags; 862 /* resulting sequence number */ 863 uint64_t sequence; 864 }; 865 866 enum amdgpu_ring_type { 867 AMDGPU_RING_TYPE_GFX, 868 AMDGPU_RING_TYPE_COMPUTE, 869 AMDGPU_RING_TYPE_SDMA, 870 AMDGPU_RING_TYPE_UVD, 871 AMDGPU_RING_TYPE_VCE 872 }; 873 874 extern struct amd_sched_backend_ops amdgpu_sched_ops; 875 876 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 877 struct amdgpu_ring *ring, 878 struct amdgpu_ib *ibs, 879 unsigned num_ibs, 880 int (*free_job)(struct amdgpu_job *), 881 void *owner, 882 struct fence **fence); 883 884 struct amdgpu_ring { 885 struct amdgpu_device *adev; 886 const struct amdgpu_ring_funcs *funcs; 887 struct amdgpu_fence_driver fence_drv; 888 struct amd_gpu_scheduler *scheduler; 889 890 spinlock_t fence_lock; 891 struct mutex *ring_lock; 892 struct amdgpu_bo *ring_obj; 893 volatile uint32_t *ring; 894 unsigned rptr_offs; 895 u64 next_rptr_gpu_addr; 896 volatile u32 *next_rptr_cpu_addr; 897 unsigned wptr; 898 unsigned wptr_old; 899 unsigned ring_size; 900 unsigned ring_free_dw; 901 int count_dw; 902 atomic_t last_rptr; 903 atomic64_t last_activity; 904 uint64_t gpu_addr; 905 uint32_t align_mask; 906 uint32_t ptr_mask; 907 bool ready; 908 u32 nop; 909 u32 idx; 910 u64 last_semaphore_signal_addr; 911 u64 last_semaphore_wait_addr; 912 u32 me; 913 u32 pipe; 914 u32 queue; 915 struct amdgpu_bo *mqd_obj; 916 u32 doorbell_index; 917 bool use_doorbell; 918 unsigned wptr_offs; 919 unsigned next_rptr_offs; 920 unsigned fence_offs; 921 struct amdgpu_ctx *current_ctx; 922 enum amdgpu_ring_type type; 923 char name[16]; 924 bool is_pte_ring; 925 }; 926 927 /* 928 * VM 929 */ 930 931 /* maximum number of VMIDs */ 932 #define AMDGPU_NUM_VM 16 933 934 /* number of entries in page table */ 935 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 936 937 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 938 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 939 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 940 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 941 942 #define AMDGPU_PTE_VALID (1 << 0) 943 #define AMDGPU_PTE_SYSTEM (1 << 1) 944 #define AMDGPU_PTE_SNOOPED (1 << 2) 945 946 /* VI only */ 947 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 948 949 #define AMDGPU_PTE_READABLE (1 << 5) 950 #define AMDGPU_PTE_WRITEABLE (1 << 6) 951 952 /* PTE (Page Table Entry) fragment field for different page sizes */ 953 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 954 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 955 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 956 957 struct amdgpu_vm_pt { 958 struct amdgpu_bo *bo; 959 uint64_t addr; 960 }; 961 962 struct amdgpu_vm_id { 963 unsigned id; 964 uint64_t pd_gpu_addr; 965 /* last flushed PD/PT update */ 966 struct fence *flushed_updates; 967 /* last use of vmid */ 968 struct amdgpu_fence *last_id_use; 969 }; 970 971 struct amdgpu_vm { 972 struct mutex mutex; 973 974 struct rb_root va; 975 976 /* protecting invalidated */ 977 spinlock_t status_lock; 978 979 /* BOs moved, but not yet updated in the PT */ 980 struct list_head invalidated; 981 982 /* BOs cleared in the PT because of a move */ 983 struct list_head cleared; 984 985 /* BO mappings freed, but not yet updated in the PT */ 986 struct list_head freed; 987 988 /* contains the page directory */ 989 struct amdgpu_bo *page_directory; 990 unsigned max_pde_used; 991 struct fence *page_directory_fence; 992 993 /* array of page tables, one for each page directory entry */ 994 struct amdgpu_vm_pt *page_tables; 995 996 /* for id and flush management per ring */ 997 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 998 }; 999 1000 struct amdgpu_vm_manager { 1001 struct amdgpu_fence *active[AMDGPU_NUM_VM]; 1002 uint32_t max_pfn; 1003 /* number of VMIDs */ 1004 unsigned nvm; 1005 /* vram base address for page table entry */ 1006 u64 vram_base_offset; 1007 /* is vm enabled? */ 1008 bool enabled; 1009 /* for hw to save the PD addr on suspend/resume */ 1010 uint32_t saved_table_addr[AMDGPU_NUM_VM]; 1011 /* vm pte handling */ 1012 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 1013 struct amdgpu_ring *vm_pte_funcs_ring; 1014 }; 1015 1016 /* 1017 * context related structures 1018 */ 1019 1020 #define AMDGPU_CTX_MAX_CS_PENDING 16 1021 1022 struct amdgpu_ctx_ring { 1023 uint64_t sequence; 1024 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1025 struct amd_sched_entity entity; 1026 }; 1027 1028 struct amdgpu_ctx { 1029 struct kref refcount; 1030 struct amdgpu_device *adev; 1031 unsigned reset_counter; 1032 spinlock_t ring_lock; 1033 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1034 }; 1035 1036 struct amdgpu_ctx_mgr { 1037 struct amdgpu_device *adev; 1038 struct mutex lock; 1039 /* protected by lock */ 1040 struct idr ctx_handles; 1041 }; 1042 1043 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1044 struct amdgpu_ctx *ctx); 1045 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1046 1047 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1048 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1049 1050 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1051 struct fence *fence); 1052 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1053 struct amdgpu_ring *ring, uint64_t seq); 1054 1055 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1056 struct drm_file *filp); 1057 1058 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1059 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1060 1061 /* 1062 * file private structure 1063 */ 1064 1065 struct amdgpu_fpriv { 1066 struct amdgpu_vm vm; 1067 struct mutex bo_list_lock; 1068 struct idr bo_list_handles; 1069 struct amdgpu_ctx_mgr ctx_mgr; 1070 }; 1071 1072 /* 1073 * residency list 1074 */ 1075 1076 struct amdgpu_bo_list { 1077 struct mutex lock; 1078 struct amdgpu_bo *gds_obj; 1079 struct amdgpu_bo *gws_obj; 1080 struct amdgpu_bo *oa_obj; 1081 bool has_userptr; 1082 unsigned num_entries; 1083 struct amdgpu_bo_list_entry *array; 1084 }; 1085 1086 struct amdgpu_bo_list * 1087 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1088 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1089 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1090 1091 /* 1092 * GFX stuff 1093 */ 1094 #include "clearstate_defs.h" 1095 1096 struct amdgpu_rlc { 1097 /* for power gating */ 1098 struct amdgpu_bo *save_restore_obj; 1099 uint64_t save_restore_gpu_addr; 1100 volatile uint32_t *sr_ptr; 1101 const u32 *reg_list; 1102 u32 reg_list_size; 1103 /* for clear state */ 1104 struct amdgpu_bo *clear_state_obj; 1105 uint64_t clear_state_gpu_addr; 1106 volatile uint32_t *cs_ptr; 1107 const struct cs_section_def *cs_data; 1108 u32 clear_state_size; 1109 /* for cp tables */ 1110 struct amdgpu_bo *cp_table_obj; 1111 uint64_t cp_table_gpu_addr; 1112 volatile uint32_t *cp_table_ptr; 1113 u32 cp_table_size; 1114 }; 1115 1116 struct amdgpu_mec { 1117 struct amdgpu_bo *hpd_eop_obj; 1118 u64 hpd_eop_gpu_addr; 1119 u32 num_pipe; 1120 u32 num_mec; 1121 u32 num_queue; 1122 }; 1123 1124 /* 1125 * GPU scratch registers structures, functions & helpers 1126 */ 1127 struct amdgpu_scratch { 1128 unsigned num_reg; 1129 uint32_t reg_base; 1130 bool free[32]; 1131 uint32_t reg[32]; 1132 }; 1133 1134 /* 1135 * GFX configurations 1136 */ 1137 struct amdgpu_gca_config { 1138 unsigned max_shader_engines; 1139 unsigned max_tile_pipes; 1140 unsigned max_cu_per_sh; 1141 unsigned max_sh_per_se; 1142 unsigned max_backends_per_se; 1143 unsigned max_texture_channel_caches; 1144 unsigned max_gprs; 1145 unsigned max_gs_threads; 1146 unsigned max_hw_contexts; 1147 unsigned sc_prim_fifo_size_frontend; 1148 unsigned sc_prim_fifo_size_backend; 1149 unsigned sc_hiz_tile_fifo_size; 1150 unsigned sc_earlyz_tile_fifo_size; 1151 1152 unsigned num_tile_pipes; 1153 unsigned backend_enable_mask; 1154 unsigned mem_max_burst_length_bytes; 1155 unsigned mem_row_size_in_kb; 1156 unsigned shader_engine_tile_size; 1157 unsigned num_gpus; 1158 unsigned multi_gpu_tile_size; 1159 unsigned mc_arb_ramcfg; 1160 unsigned gb_addr_config; 1161 1162 uint32_t tile_mode_array[32]; 1163 uint32_t macrotile_mode_array[16]; 1164 }; 1165 1166 struct amdgpu_gfx { 1167 struct mutex gpu_clock_mutex; 1168 struct amdgpu_gca_config config; 1169 struct amdgpu_rlc rlc; 1170 struct amdgpu_mec mec; 1171 struct amdgpu_scratch scratch; 1172 const struct firmware *me_fw; /* ME firmware */ 1173 uint32_t me_fw_version; 1174 const struct firmware *pfp_fw; /* PFP firmware */ 1175 uint32_t pfp_fw_version; 1176 const struct firmware *ce_fw; /* CE firmware */ 1177 uint32_t ce_fw_version; 1178 const struct firmware *rlc_fw; /* RLC firmware */ 1179 uint32_t rlc_fw_version; 1180 const struct firmware *mec_fw; /* MEC firmware */ 1181 uint32_t mec_fw_version; 1182 const struct firmware *mec2_fw; /* MEC2 firmware */ 1183 uint32_t mec2_fw_version; 1184 uint32_t me_feature_version; 1185 uint32_t ce_feature_version; 1186 uint32_t pfp_feature_version; 1187 uint32_t rlc_feature_version; 1188 uint32_t mec_feature_version; 1189 uint32_t mec2_feature_version; 1190 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1191 unsigned num_gfx_rings; 1192 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1193 unsigned num_compute_rings; 1194 struct amdgpu_irq_src eop_irq; 1195 struct amdgpu_irq_src priv_reg_irq; 1196 struct amdgpu_irq_src priv_inst_irq; 1197 /* gfx status */ 1198 uint32_t gfx_current_status; 1199 /* sync signal for const engine */ 1200 unsigned ce_sync_offs; 1201 /* ce ram size*/ 1202 unsigned ce_ram_size; 1203 }; 1204 1205 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1206 unsigned size, struct amdgpu_ib *ib); 1207 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1208 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1209 struct amdgpu_ib *ib, void *owner); 1210 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1211 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1212 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1213 /* Ring access between begin & end cannot sleep */ 1214 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1215 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1216 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1217 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1218 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1219 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1220 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1221 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); 1222 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); 1223 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1224 uint32_t **data); 1225 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1226 unsigned size, uint32_t *data); 1227 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1228 unsigned ring_size, u32 nop, u32 align_mask, 1229 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1230 enum amdgpu_ring_type ring_type); 1231 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1232 1233 /* 1234 * CS. 1235 */ 1236 struct amdgpu_cs_chunk { 1237 uint32_t chunk_id; 1238 uint32_t length_dw; 1239 uint32_t *kdata; 1240 void __user *user_ptr; 1241 }; 1242 1243 struct amdgpu_cs_parser { 1244 struct amdgpu_device *adev; 1245 struct drm_file *filp; 1246 struct amdgpu_ctx *ctx; 1247 struct amdgpu_bo_list *bo_list; 1248 /* chunks */ 1249 unsigned nchunks; 1250 struct amdgpu_cs_chunk *chunks; 1251 /* relocations */ 1252 struct amdgpu_bo_list_entry *vm_bos; 1253 struct list_head validated; 1254 1255 struct amdgpu_ib *ibs; 1256 uint32_t num_ibs; 1257 1258 struct ww_acquire_ctx ticket; 1259 1260 /* user fence */ 1261 struct amdgpu_user_fence uf; 1262 }; 1263 1264 struct amdgpu_job { 1265 struct amd_sched_job base; 1266 struct amdgpu_device *adev; 1267 struct amdgpu_ib *ibs; 1268 uint32_t num_ibs; 1269 struct mutex job_lock; 1270 struct amdgpu_user_fence uf; 1271 int (*free_job)(struct amdgpu_job *sched_job); 1272 }; 1273 1274 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1275 { 1276 return p->ibs[ib_idx].ptr[idx]; 1277 } 1278 1279 /* 1280 * Writeback 1281 */ 1282 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1283 1284 struct amdgpu_wb { 1285 struct amdgpu_bo *wb_obj; 1286 volatile uint32_t *wb; 1287 uint64_t gpu_addr; 1288 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1289 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1290 }; 1291 1292 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1293 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1294 1295 /** 1296 * struct amdgpu_pm - power management datas 1297 * It keeps track of various data needed to take powermanagement decision. 1298 */ 1299 1300 enum amdgpu_pm_state_type { 1301 /* not used for dpm */ 1302 POWER_STATE_TYPE_DEFAULT, 1303 POWER_STATE_TYPE_POWERSAVE, 1304 /* user selectable states */ 1305 POWER_STATE_TYPE_BATTERY, 1306 POWER_STATE_TYPE_BALANCED, 1307 POWER_STATE_TYPE_PERFORMANCE, 1308 /* internal states */ 1309 POWER_STATE_TYPE_INTERNAL_UVD, 1310 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1311 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1312 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1313 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1314 POWER_STATE_TYPE_INTERNAL_BOOT, 1315 POWER_STATE_TYPE_INTERNAL_THERMAL, 1316 POWER_STATE_TYPE_INTERNAL_ACPI, 1317 POWER_STATE_TYPE_INTERNAL_ULV, 1318 POWER_STATE_TYPE_INTERNAL_3DPERF, 1319 }; 1320 1321 enum amdgpu_int_thermal_type { 1322 THERMAL_TYPE_NONE, 1323 THERMAL_TYPE_EXTERNAL, 1324 THERMAL_TYPE_EXTERNAL_GPIO, 1325 THERMAL_TYPE_RV6XX, 1326 THERMAL_TYPE_RV770, 1327 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1328 THERMAL_TYPE_EVERGREEN, 1329 THERMAL_TYPE_SUMO, 1330 THERMAL_TYPE_NI, 1331 THERMAL_TYPE_SI, 1332 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1333 THERMAL_TYPE_CI, 1334 THERMAL_TYPE_KV, 1335 }; 1336 1337 enum amdgpu_dpm_auto_throttle_src { 1338 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1339 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1340 }; 1341 1342 enum amdgpu_dpm_event_src { 1343 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1344 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1345 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1346 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1347 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1348 }; 1349 1350 #define AMDGPU_MAX_VCE_LEVELS 6 1351 1352 enum amdgpu_vce_level { 1353 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1354 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1355 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1356 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1357 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1358 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1359 }; 1360 1361 struct amdgpu_ps { 1362 u32 caps; /* vbios flags */ 1363 u32 class; /* vbios flags */ 1364 u32 class2; /* vbios flags */ 1365 /* UVD clocks */ 1366 u32 vclk; 1367 u32 dclk; 1368 /* VCE clocks */ 1369 u32 evclk; 1370 u32 ecclk; 1371 bool vce_active; 1372 enum amdgpu_vce_level vce_level; 1373 /* asic priv */ 1374 void *ps_priv; 1375 }; 1376 1377 struct amdgpu_dpm_thermal { 1378 /* thermal interrupt work */ 1379 struct work_struct work; 1380 /* low temperature threshold */ 1381 int min_temp; 1382 /* high temperature threshold */ 1383 int max_temp; 1384 /* was last interrupt low to high or high to low */ 1385 bool high_to_low; 1386 /* interrupt source */ 1387 struct amdgpu_irq_src irq; 1388 }; 1389 1390 enum amdgpu_clk_action 1391 { 1392 AMDGPU_SCLK_UP = 1, 1393 AMDGPU_SCLK_DOWN 1394 }; 1395 1396 struct amdgpu_blacklist_clocks 1397 { 1398 u32 sclk; 1399 u32 mclk; 1400 enum amdgpu_clk_action action; 1401 }; 1402 1403 struct amdgpu_clock_and_voltage_limits { 1404 u32 sclk; 1405 u32 mclk; 1406 u16 vddc; 1407 u16 vddci; 1408 }; 1409 1410 struct amdgpu_clock_array { 1411 u32 count; 1412 u32 *values; 1413 }; 1414 1415 struct amdgpu_clock_voltage_dependency_entry { 1416 u32 clk; 1417 u16 v; 1418 }; 1419 1420 struct amdgpu_clock_voltage_dependency_table { 1421 u32 count; 1422 struct amdgpu_clock_voltage_dependency_entry *entries; 1423 }; 1424 1425 union amdgpu_cac_leakage_entry { 1426 struct { 1427 u16 vddc; 1428 u32 leakage; 1429 }; 1430 struct { 1431 u16 vddc1; 1432 u16 vddc2; 1433 u16 vddc3; 1434 }; 1435 }; 1436 1437 struct amdgpu_cac_leakage_table { 1438 u32 count; 1439 union amdgpu_cac_leakage_entry *entries; 1440 }; 1441 1442 struct amdgpu_phase_shedding_limits_entry { 1443 u16 voltage; 1444 u32 sclk; 1445 u32 mclk; 1446 }; 1447 1448 struct amdgpu_phase_shedding_limits_table { 1449 u32 count; 1450 struct amdgpu_phase_shedding_limits_entry *entries; 1451 }; 1452 1453 struct amdgpu_uvd_clock_voltage_dependency_entry { 1454 u32 vclk; 1455 u32 dclk; 1456 u16 v; 1457 }; 1458 1459 struct amdgpu_uvd_clock_voltage_dependency_table { 1460 u8 count; 1461 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1462 }; 1463 1464 struct amdgpu_vce_clock_voltage_dependency_entry { 1465 u32 ecclk; 1466 u32 evclk; 1467 u16 v; 1468 }; 1469 1470 struct amdgpu_vce_clock_voltage_dependency_table { 1471 u8 count; 1472 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1473 }; 1474 1475 struct amdgpu_ppm_table { 1476 u8 ppm_design; 1477 u16 cpu_core_number; 1478 u32 platform_tdp; 1479 u32 small_ac_platform_tdp; 1480 u32 platform_tdc; 1481 u32 small_ac_platform_tdc; 1482 u32 apu_tdp; 1483 u32 dgpu_tdp; 1484 u32 dgpu_ulv_power; 1485 u32 tj_max; 1486 }; 1487 1488 struct amdgpu_cac_tdp_table { 1489 u16 tdp; 1490 u16 configurable_tdp; 1491 u16 tdc; 1492 u16 battery_power_limit; 1493 u16 small_power_limit; 1494 u16 low_cac_leakage; 1495 u16 high_cac_leakage; 1496 u16 maximum_power_delivery_limit; 1497 }; 1498 1499 struct amdgpu_dpm_dynamic_state { 1500 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1501 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1502 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1503 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1504 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1505 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1506 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1507 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1508 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1509 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1510 struct amdgpu_clock_array valid_sclk_values; 1511 struct amdgpu_clock_array valid_mclk_values; 1512 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1513 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1514 u32 mclk_sclk_ratio; 1515 u32 sclk_mclk_delta; 1516 u16 vddc_vddci_delta; 1517 u16 min_vddc_for_pcie_gen2; 1518 struct amdgpu_cac_leakage_table cac_leakage_table; 1519 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1520 struct amdgpu_ppm_table *ppm_table; 1521 struct amdgpu_cac_tdp_table *cac_tdp_table; 1522 }; 1523 1524 struct amdgpu_dpm_fan { 1525 u16 t_min; 1526 u16 t_med; 1527 u16 t_high; 1528 u16 pwm_min; 1529 u16 pwm_med; 1530 u16 pwm_high; 1531 u8 t_hyst; 1532 u32 cycle_delay; 1533 u16 t_max; 1534 u8 control_mode; 1535 u16 default_max_fan_pwm; 1536 u16 default_fan_output_sensitivity; 1537 u16 fan_output_sensitivity; 1538 bool ucode_fan_control; 1539 }; 1540 1541 enum amdgpu_pcie_gen { 1542 AMDGPU_PCIE_GEN1 = 0, 1543 AMDGPU_PCIE_GEN2 = 1, 1544 AMDGPU_PCIE_GEN3 = 2, 1545 AMDGPU_PCIE_GEN_INVALID = 0xffff 1546 }; 1547 1548 enum amdgpu_dpm_forced_level { 1549 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1550 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1551 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1552 }; 1553 1554 struct amdgpu_vce_state { 1555 /* vce clocks */ 1556 u32 evclk; 1557 u32 ecclk; 1558 /* gpu clocks */ 1559 u32 sclk; 1560 u32 mclk; 1561 u8 clk_idx; 1562 u8 pstate; 1563 }; 1564 1565 struct amdgpu_dpm_funcs { 1566 int (*get_temperature)(struct amdgpu_device *adev); 1567 int (*pre_set_power_state)(struct amdgpu_device *adev); 1568 int (*set_power_state)(struct amdgpu_device *adev); 1569 void (*post_set_power_state)(struct amdgpu_device *adev); 1570 void (*display_configuration_changed)(struct amdgpu_device *adev); 1571 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1572 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1573 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1574 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1575 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1576 bool (*vblank_too_short)(struct amdgpu_device *adev); 1577 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1578 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1579 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1580 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1581 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1582 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1583 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1584 }; 1585 1586 struct amdgpu_dpm { 1587 struct amdgpu_ps *ps; 1588 /* number of valid power states */ 1589 int num_ps; 1590 /* current power state that is active */ 1591 struct amdgpu_ps *current_ps; 1592 /* requested power state */ 1593 struct amdgpu_ps *requested_ps; 1594 /* boot up power state */ 1595 struct amdgpu_ps *boot_ps; 1596 /* default uvd power state */ 1597 struct amdgpu_ps *uvd_ps; 1598 /* vce requirements */ 1599 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1600 enum amdgpu_vce_level vce_level; 1601 enum amdgpu_pm_state_type state; 1602 enum amdgpu_pm_state_type user_state; 1603 u32 platform_caps; 1604 u32 voltage_response_time; 1605 u32 backbias_response_time; 1606 void *priv; 1607 u32 new_active_crtcs; 1608 int new_active_crtc_count; 1609 u32 current_active_crtcs; 1610 int current_active_crtc_count; 1611 struct amdgpu_dpm_dynamic_state dyn_state; 1612 struct amdgpu_dpm_fan fan; 1613 u32 tdp_limit; 1614 u32 near_tdp_limit; 1615 u32 near_tdp_limit_adjusted; 1616 u32 sq_ramping_threshold; 1617 u32 cac_leakage; 1618 u16 tdp_od_limit; 1619 u32 tdp_adjustment; 1620 u16 load_line_slope; 1621 bool power_control; 1622 bool ac_power; 1623 /* special states active */ 1624 bool thermal_active; 1625 bool uvd_active; 1626 bool vce_active; 1627 /* thermal handling */ 1628 struct amdgpu_dpm_thermal thermal; 1629 /* forced levels */ 1630 enum amdgpu_dpm_forced_level forced_level; 1631 }; 1632 1633 struct amdgpu_pm { 1634 struct mutex mutex; 1635 u32 current_sclk; 1636 u32 current_mclk; 1637 u32 default_sclk; 1638 u32 default_mclk; 1639 struct amdgpu_i2c_chan *i2c_bus; 1640 /* internal thermal controller on rv6xx+ */ 1641 enum amdgpu_int_thermal_type int_thermal_type; 1642 struct device *int_hwmon_dev; 1643 /* fan control parameters */ 1644 bool no_fan; 1645 u8 fan_pulses_per_revolution; 1646 u8 fan_min_rpm; 1647 u8 fan_max_rpm; 1648 /* dpm */ 1649 bool dpm_enabled; 1650 struct amdgpu_dpm dpm; 1651 const struct firmware *fw; /* SMC firmware */ 1652 uint32_t fw_version; 1653 const struct amdgpu_dpm_funcs *funcs; 1654 }; 1655 1656 /* 1657 * UVD 1658 */ 1659 #define AMDGPU_MAX_UVD_HANDLES 10 1660 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1661 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1662 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1663 1664 struct amdgpu_uvd { 1665 struct amdgpu_bo *vcpu_bo; 1666 void *cpu_addr; 1667 uint64_t gpu_addr; 1668 void *saved_bo; 1669 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1670 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1671 struct delayed_work idle_work; 1672 const struct firmware *fw; /* UVD firmware */ 1673 struct amdgpu_ring ring; 1674 struct amdgpu_irq_src irq; 1675 bool address_64_bit; 1676 }; 1677 1678 /* 1679 * VCE 1680 */ 1681 #define AMDGPU_MAX_VCE_HANDLES 16 1682 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1683 1684 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1685 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1686 1687 struct amdgpu_vce { 1688 struct amdgpu_bo *vcpu_bo; 1689 uint64_t gpu_addr; 1690 unsigned fw_version; 1691 unsigned fb_version; 1692 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1693 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1694 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1695 struct delayed_work idle_work; 1696 const struct firmware *fw; /* VCE firmware */ 1697 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1698 struct amdgpu_irq_src irq; 1699 unsigned harvest_config; 1700 }; 1701 1702 /* 1703 * SDMA 1704 */ 1705 struct amdgpu_sdma { 1706 /* SDMA firmware */ 1707 const struct firmware *fw; 1708 uint32_t fw_version; 1709 uint32_t feature_version; 1710 1711 struct amdgpu_ring ring; 1712 }; 1713 1714 /* 1715 * Firmware 1716 */ 1717 struct amdgpu_firmware { 1718 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1719 bool smu_load; 1720 struct amdgpu_bo *fw_buf; 1721 unsigned int fw_size; 1722 }; 1723 1724 /* 1725 * Benchmarking 1726 */ 1727 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1728 1729 1730 /* 1731 * Testing 1732 */ 1733 void amdgpu_test_moves(struct amdgpu_device *adev); 1734 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1735 struct amdgpu_ring *cpA, 1736 struct amdgpu_ring *cpB); 1737 void amdgpu_test_syncing(struct amdgpu_device *adev); 1738 1739 /* 1740 * MMU Notifier 1741 */ 1742 #if defined(CONFIG_MMU_NOTIFIER) 1743 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1744 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1745 #else 1746 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1747 { 1748 return -ENODEV; 1749 } 1750 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1751 #endif 1752 1753 /* 1754 * Debugfs 1755 */ 1756 struct amdgpu_debugfs { 1757 struct drm_info_list *files; 1758 unsigned num_files; 1759 }; 1760 1761 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1762 struct drm_info_list *files, 1763 unsigned nfiles); 1764 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1765 1766 #if defined(CONFIG_DEBUG_FS) 1767 int amdgpu_debugfs_init(struct drm_minor *minor); 1768 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1769 #endif 1770 1771 /* 1772 * amdgpu smumgr functions 1773 */ 1774 struct amdgpu_smumgr_funcs { 1775 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1776 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1777 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1778 }; 1779 1780 /* 1781 * amdgpu smumgr 1782 */ 1783 struct amdgpu_smumgr { 1784 struct amdgpu_bo *toc_buf; 1785 struct amdgpu_bo *smu_buf; 1786 /* asic priv smu data */ 1787 void *priv; 1788 spinlock_t smu_lock; 1789 /* smumgr functions */ 1790 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1791 /* ucode loading complete flag */ 1792 uint32_t fw_flags; 1793 }; 1794 1795 /* 1796 * ASIC specific register table accessible by UMD 1797 */ 1798 struct amdgpu_allowed_register_entry { 1799 uint32_t reg_offset; 1800 bool untouched; 1801 bool grbm_indexed; 1802 }; 1803 1804 struct amdgpu_cu_info { 1805 uint32_t number; /* total active CU number */ 1806 uint32_t ao_cu_mask; 1807 uint32_t bitmap[4][4]; 1808 }; 1809 1810 1811 /* 1812 * ASIC specific functions. 1813 */ 1814 struct amdgpu_asic_funcs { 1815 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1816 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1817 u32 sh_num, u32 reg_offset, u32 *value); 1818 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1819 int (*reset)(struct amdgpu_device *adev); 1820 /* wait for mc_idle */ 1821 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1822 /* get the reference clock */ 1823 u32 (*get_xclk)(struct amdgpu_device *adev); 1824 /* get the gpu clock counter */ 1825 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1826 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1827 /* MM block clocks */ 1828 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1829 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1830 }; 1831 1832 /* 1833 * IOCTL. 1834 */ 1835 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1836 struct drm_file *filp); 1837 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1838 struct drm_file *filp); 1839 1840 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1841 struct drm_file *filp); 1842 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1843 struct drm_file *filp); 1844 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1845 struct drm_file *filp); 1846 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1847 struct drm_file *filp); 1848 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1849 struct drm_file *filp); 1850 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1853 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1854 1855 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1856 struct drm_file *filp); 1857 1858 /* VRAM scratch page for HDP bug, default vram page */ 1859 struct amdgpu_vram_scratch { 1860 struct amdgpu_bo *robj; 1861 volatile uint32_t *ptr; 1862 u64 gpu_addr; 1863 }; 1864 1865 /* 1866 * ACPI 1867 */ 1868 struct amdgpu_atif_notification_cfg { 1869 bool enabled; 1870 int command_code; 1871 }; 1872 1873 struct amdgpu_atif_notifications { 1874 bool display_switch; 1875 bool expansion_mode_change; 1876 bool thermal_state; 1877 bool forced_power_state; 1878 bool system_power_state; 1879 bool display_conf_change; 1880 bool px_gfx_switch; 1881 bool brightness_change; 1882 bool dgpu_display_event; 1883 }; 1884 1885 struct amdgpu_atif_functions { 1886 bool system_params; 1887 bool sbios_requests; 1888 bool select_active_disp; 1889 bool lid_state; 1890 bool get_tv_standard; 1891 bool set_tv_standard; 1892 bool get_panel_expansion_mode; 1893 bool set_panel_expansion_mode; 1894 bool temperature_change; 1895 bool graphics_device_types; 1896 }; 1897 1898 struct amdgpu_atif { 1899 struct amdgpu_atif_notifications notifications; 1900 struct amdgpu_atif_functions functions; 1901 struct amdgpu_atif_notification_cfg notification_cfg; 1902 struct amdgpu_encoder *encoder_for_bl; 1903 }; 1904 1905 struct amdgpu_atcs_functions { 1906 bool get_ext_state; 1907 bool pcie_perf_req; 1908 bool pcie_dev_rdy; 1909 bool pcie_bus_width; 1910 }; 1911 1912 struct amdgpu_atcs { 1913 struct amdgpu_atcs_functions functions; 1914 }; 1915 1916 /* 1917 * CGS 1918 */ 1919 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1920 void amdgpu_cgs_destroy_device(void *cgs_device); 1921 1922 1923 /* 1924 * Core structure, functions and helpers. 1925 */ 1926 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1927 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1928 1929 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1930 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1931 1932 struct amdgpu_ip_block_status { 1933 bool valid; 1934 bool sw; 1935 bool hw; 1936 }; 1937 1938 struct amdgpu_device { 1939 struct device *dev; 1940 struct drm_device *ddev; 1941 struct pci_dev *pdev; 1942 struct rw_semaphore exclusive_lock; 1943 1944 /* ASIC */ 1945 enum amd_asic_type asic_type; 1946 uint32_t family; 1947 uint32_t rev_id; 1948 uint32_t external_rev_id; 1949 unsigned long flags; 1950 int usec_timeout; 1951 const struct amdgpu_asic_funcs *asic_funcs; 1952 bool shutdown; 1953 bool suspend; 1954 bool need_dma32; 1955 bool accel_working; 1956 bool needs_reset; 1957 struct work_struct reset_work; 1958 struct notifier_block acpi_nb; 1959 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1960 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1961 unsigned debugfs_count; 1962 #if defined(CONFIG_DEBUG_FS) 1963 struct dentry *debugfs_regs; 1964 #endif 1965 struct amdgpu_atif atif; 1966 struct amdgpu_atcs atcs; 1967 struct mutex srbm_mutex; 1968 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1969 struct mutex grbm_idx_mutex; 1970 struct dev_pm_domain vga_pm_domain; 1971 bool have_disp_power_ref; 1972 1973 /* BIOS */ 1974 uint8_t *bios; 1975 bool is_atom_bios; 1976 uint16_t bios_header_start; 1977 struct amdgpu_bo *stollen_vga_memory; 1978 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1979 1980 /* Register/doorbell mmio */ 1981 resource_size_t rmmio_base; 1982 resource_size_t rmmio_size; 1983 void __iomem *rmmio; 1984 /* protects concurrent MM_INDEX/DATA based register access */ 1985 spinlock_t mmio_idx_lock; 1986 /* protects concurrent SMC based register access */ 1987 spinlock_t smc_idx_lock; 1988 amdgpu_rreg_t smc_rreg; 1989 amdgpu_wreg_t smc_wreg; 1990 /* protects concurrent PCIE register access */ 1991 spinlock_t pcie_idx_lock; 1992 amdgpu_rreg_t pcie_rreg; 1993 amdgpu_wreg_t pcie_wreg; 1994 /* protects concurrent UVD register access */ 1995 spinlock_t uvd_ctx_idx_lock; 1996 amdgpu_rreg_t uvd_ctx_rreg; 1997 amdgpu_wreg_t uvd_ctx_wreg; 1998 /* protects concurrent DIDT register access */ 1999 spinlock_t didt_idx_lock; 2000 amdgpu_rreg_t didt_rreg; 2001 amdgpu_wreg_t didt_wreg; 2002 /* protects concurrent ENDPOINT (audio) register access */ 2003 spinlock_t audio_endpt_idx_lock; 2004 amdgpu_block_rreg_t audio_endpt_rreg; 2005 amdgpu_block_wreg_t audio_endpt_wreg; 2006 void __iomem *rio_mem; 2007 resource_size_t rio_mem_size; 2008 struct amdgpu_doorbell doorbell; 2009 2010 /* clock/pll info */ 2011 struct amdgpu_clock clock; 2012 2013 /* MC */ 2014 struct amdgpu_mc mc; 2015 struct amdgpu_gart gart; 2016 struct amdgpu_dummy_page dummy_page; 2017 struct amdgpu_vm_manager vm_manager; 2018 2019 /* memory management */ 2020 struct amdgpu_mman mman; 2021 struct amdgpu_gem gem; 2022 struct amdgpu_vram_scratch vram_scratch; 2023 struct amdgpu_wb wb; 2024 atomic64_t vram_usage; 2025 atomic64_t vram_vis_usage; 2026 atomic64_t gtt_usage; 2027 atomic64_t num_bytes_moved; 2028 atomic_t gpu_reset_counter; 2029 2030 /* display */ 2031 struct amdgpu_mode_info mode_info; 2032 struct work_struct hotplug_work; 2033 struct amdgpu_irq_src crtc_irq; 2034 struct amdgpu_irq_src pageflip_irq; 2035 struct amdgpu_irq_src hpd_irq; 2036 2037 /* rings */ 2038 unsigned fence_context; 2039 struct mutex ring_lock; 2040 unsigned num_rings; 2041 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2042 bool ib_pool_ready; 2043 struct amdgpu_sa_manager ring_tmp_bo; 2044 2045 /* interrupts */ 2046 struct amdgpu_irq irq; 2047 2048 /* dpm */ 2049 struct amdgpu_pm pm; 2050 u32 cg_flags; 2051 u32 pg_flags; 2052 2053 /* amdgpu smumgr */ 2054 struct amdgpu_smumgr smu; 2055 2056 /* gfx */ 2057 struct amdgpu_gfx gfx; 2058 2059 /* sdma */ 2060 struct amdgpu_sdma sdma[2]; 2061 struct amdgpu_irq_src sdma_trap_irq; 2062 struct amdgpu_irq_src sdma_illegal_inst_irq; 2063 2064 /* uvd */ 2065 bool has_uvd; 2066 struct amdgpu_uvd uvd; 2067 2068 /* vce */ 2069 struct amdgpu_vce vce; 2070 2071 /* firmwares */ 2072 struct amdgpu_firmware firmware; 2073 2074 /* GDS */ 2075 struct amdgpu_gds gds; 2076 2077 const struct amdgpu_ip_block_version *ip_blocks; 2078 int num_ip_blocks; 2079 struct amdgpu_ip_block_status *ip_block_status; 2080 struct mutex mn_lock; 2081 DECLARE_HASHTABLE(mn_hash, 7); 2082 2083 /* tracking pinned memory */ 2084 u64 vram_pin_size; 2085 u64 gart_pin_size; 2086 2087 /* amdkfd interface */ 2088 struct kfd_dev *kfd; 2089 2090 /* kernel conext for IB submission */ 2091 struct amdgpu_ctx kernel_ctx; 2092 }; 2093 2094 bool amdgpu_device_is_px(struct drm_device *dev); 2095 int amdgpu_device_init(struct amdgpu_device *adev, 2096 struct drm_device *ddev, 2097 struct pci_dev *pdev, 2098 uint32_t flags); 2099 void amdgpu_device_fini(struct amdgpu_device *adev); 2100 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2101 2102 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2103 bool always_indirect); 2104 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2105 bool always_indirect); 2106 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2107 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2108 2109 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2110 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2111 2112 /* 2113 * Cast helper 2114 */ 2115 extern const struct fence_ops amdgpu_fence_ops; 2116 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2117 { 2118 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2119 2120 if (__f->base.ops == &amdgpu_fence_ops) 2121 return __f; 2122 2123 return NULL; 2124 } 2125 2126 /* 2127 * Registers read & write functions. 2128 */ 2129 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2130 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2131 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2132 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2133 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2134 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2135 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2136 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2137 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2138 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2139 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2140 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2141 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2142 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2143 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2144 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2145 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2146 #define WREG32_P(reg, val, mask) \ 2147 do { \ 2148 uint32_t tmp_ = RREG32(reg); \ 2149 tmp_ &= (mask); \ 2150 tmp_ |= ((val) & ~(mask)); \ 2151 WREG32(reg, tmp_); \ 2152 } while (0) 2153 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2154 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2155 #define WREG32_PLL_P(reg, val, mask) \ 2156 do { \ 2157 uint32_t tmp_ = RREG32_PLL(reg); \ 2158 tmp_ &= (mask); \ 2159 tmp_ |= ((val) & ~(mask)); \ 2160 WREG32_PLL(reg, tmp_); \ 2161 } while (0) 2162 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2163 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2164 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2165 2166 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2167 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2168 2169 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2170 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2171 2172 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2173 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2174 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2175 2176 #define REG_GET_FIELD(value, reg, field) \ 2177 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2178 2179 /* 2180 * BIOS helpers. 2181 */ 2182 #define RBIOS8(i) (adev->bios[i]) 2183 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2184 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2185 2186 /* 2187 * RING helpers. 2188 */ 2189 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2190 { 2191 if (ring->count_dw <= 0) 2192 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2193 ring->ring[ring->wptr++] = v; 2194 ring->wptr &= ring->ptr_mask; 2195 ring->count_dw--; 2196 ring->ring_free_dw--; 2197 } 2198 2199 /* 2200 * ASICs macro. 2201 */ 2202 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2203 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2204 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2205 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2206 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2207 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2208 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2209 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2210 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2211 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2212 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2213 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2214 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2215 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2216 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2217 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2218 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2219 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2220 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2221 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) 2222 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2223 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2224 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2225 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2226 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2227 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2228 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2229 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2230 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2231 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2232 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2233 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2234 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2235 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2236 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2237 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2238 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2239 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2240 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2241 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2242 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2243 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2244 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2245 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2246 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2247 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2248 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2249 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2250 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2251 #define amdgpu_emit_fill_buffer(adev, r, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((r), (s), (d), (b)) 2252 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2253 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2254 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2255 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2256 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2257 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2258 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2259 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2260 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2261 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2262 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2263 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2264 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2265 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2266 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2267 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2268 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2269 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2270 2271 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2272 2273 /* Common functions */ 2274 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2275 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2276 bool amdgpu_card_posted(struct amdgpu_device *adev); 2277 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2278 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2279 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 2280 struct drm_file *filp, 2281 struct amdgpu_ctx *ctx, 2282 struct amdgpu_ib *ibs, 2283 uint32_t num_ibs); 2284 2285 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2286 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2287 u32 ip_instance, u32 ring, 2288 struct amdgpu_ring **out_ring); 2289 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2290 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2291 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2292 uint32_t flags); 2293 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2294 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2295 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2296 struct ttm_mem_reg *mem); 2297 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2298 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2299 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2300 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2301 const u32 *registers, 2302 const u32 array_size); 2303 2304 bool amdgpu_device_is_px(struct drm_device *dev); 2305 /* atpx handler */ 2306 #if defined(CONFIG_VGA_SWITCHEROO) 2307 void amdgpu_register_atpx_handler(void); 2308 void amdgpu_unregister_atpx_handler(void); 2309 #else 2310 static inline void amdgpu_register_atpx_handler(void) {} 2311 static inline void amdgpu_unregister_atpx_handler(void) {} 2312 #endif 2313 2314 /* 2315 * KMS 2316 */ 2317 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2318 extern int amdgpu_max_kms_ioctl; 2319 2320 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2321 int amdgpu_driver_unload_kms(struct drm_device *dev); 2322 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2323 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2324 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2325 struct drm_file *file_priv); 2326 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2327 struct drm_file *file_priv); 2328 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2329 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2330 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); 2331 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); 2332 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); 2333 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 2334 int *max_error, 2335 struct timeval *vblank_time, 2336 unsigned flags); 2337 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2338 unsigned long arg); 2339 2340 /* 2341 * vm 2342 */ 2343 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2344 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2345 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2346 struct amdgpu_vm *vm, 2347 struct list_head *head); 2348 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 2349 struct amdgpu_sync *sync); 2350 void amdgpu_vm_flush(struct amdgpu_ring *ring, 2351 struct amdgpu_vm *vm, 2352 struct fence *updates); 2353 void amdgpu_vm_fence(struct amdgpu_device *adev, 2354 struct amdgpu_vm *vm, 2355 struct amdgpu_fence *fence); 2356 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2357 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2358 struct amdgpu_vm *vm); 2359 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2360 struct amdgpu_vm *vm); 2361 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2362 struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2363 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2364 struct amdgpu_bo_va *bo_va, 2365 struct ttm_mem_reg *mem); 2366 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2367 struct amdgpu_bo *bo); 2368 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2369 struct amdgpu_bo *bo); 2370 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2371 struct amdgpu_vm *vm, 2372 struct amdgpu_bo *bo); 2373 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2374 struct amdgpu_bo_va *bo_va, 2375 uint64_t addr, uint64_t offset, 2376 uint64_t size, uint32_t flags); 2377 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2378 struct amdgpu_bo_va *bo_va, 2379 uint64_t addr); 2380 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2381 struct amdgpu_bo_va *bo_va); 2382 int amdgpu_vm_free_job(struct amdgpu_job *job); 2383 /* 2384 * functions used by amdgpu_encoder.c 2385 */ 2386 struct amdgpu_afmt_acr { 2387 u32 clock; 2388 2389 int n_32khz; 2390 int cts_32khz; 2391 2392 int n_44_1khz; 2393 int cts_44_1khz; 2394 2395 int n_48khz; 2396 int cts_48khz; 2397 2398 }; 2399 2400 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2401 2402 /* amdgpu_acpi.c */ 2403 #if defined(CONFIG_ACPI) 2404 int amdgpu_acpi_init(struct amdgpu_device *adev); 2405 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2406 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2407 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2408 u8 perf_req, bool advertise); 2409 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2410 #else 2411 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2412 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2413 #endif 2414 2415 struct amdgpu_bo_va_mapping * 2416 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2417 uint64_t addr, struct amdgpu_bo **bo); 2418 2419 #include "amdgpu_object.h" 2420 2421 #endif 2422