1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 86 #define MAX_GPU_INSTANCE 16 87 88 struct amdgpu_gpu_instance 89 { 90 struct amdgpu_device *adev; 91 int mgpu_fan_enabled; 92 }; 93 94 struct amdgpu_mgpu_info 95 { 96 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 97 struct mutex mutex; 98 uint32_t num_gpu; 99 uint32_t num_dgpu; 100 uint32_t num_apu; 101 }; 102 103 /* 104 * Modules parameters. 105 */ 106 extern int amdgpu_modeset; 107 extern int amdgpu_vram_limit; 108 extern int amdgpu_vis_vram_limit; 109 extern int amdgpu_gart_size; 110 extern int amdgpu_gtt_size; 111 extern int amdgpu_moverate; 112 extern int amdgpu_benchmarking; 113 extern int amdgpu_testing; 114 extern int amdgpu_audio; 115 extern int amdgpu_disp_priority; 116 extern int amdgpu_hw_i2c; 117 extern int amdgpu_pcie_gen2; 118 extern int amdgpu_msi; 119 extern int amdgpu_lockup_timeout; 120 extern int amdgpu_dpm; 121 extern int amdgpu_fw_load_type; 122 extern int amdgpu_aspm; 123 extern int amdgpu_runtime_pm; 124 extern uint amdgpu_ip_block_mask; 125 extern int amdgpu_bapm; 126 extern int amdgpu_deep_color; 127 extern int amdgpu_vm_size; 128 extern int amdgpu_vm_block_size; 129 extern int amdgpu_vm_fragment_size; 130 extern int amdgpu_vm_fault_stop; 131 extern int amdgpu_vm_debug; 132 extern int amdgpu_vm_update_mode; 133 extern int amdgpu_dc; 134 extern int amdgpu_sched_jobs; 135 extern int amdgpu_sched_hw_submission; 136 extern uint amdgpu_pcie_gen_cap; 137 extern uint amdgpu_pcie_lane_cap; 138 extern uint amdgpu_cg_mask; 139 extern uint amdgpu_pg_mask; 140 extern uint amdgpu_sdma_phase_quantum; 141 extern char *amdgpu_disable_cu; 142 extern char *amdgpu_virtual_display; 143 extern uint amdgpu_pp_feature_mask; 144 extern int amdgpu_vram_page_split; 145 extern int amdgpu_ngg; 146 extern int amdgpu_prim_buf_per_se; 147 extern int amdgpu_pos_buf_per_se; 148 extern int amdgpu_cntl_sb_buf_per_se; 149 extern int amdgpu_param_buf_per_se; 150 extern int amdgpu_job_hang_limit; 151 extern int amdgpu_lbpw; 152 extern int amdgpu_compute_multipipe; 153 extern int amdgpu_gpu_recovery; 154 extern int amdgpu_emu_mode; 155 extern uint amdgpu_smu_memory_pool_size; 156 extern uint amdgpu_dc_feature_mask; 157 extern struct amdgpu_mgpu_info mgpu_info; 158 159 #ifdef CONFIG_DRM_AMDGPU_SI 160 extern int amdgpu_si_support; 161 #endif 162 #ifdef CONFIG_DRM_AMDGPU_CIK 163 extern int amdgpu_cik_support; 164 #endif 165 166 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 167 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 168 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 169 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 170 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 171 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 172 #define AMDGPU_IB_POOL_SIZE 16 173 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 174 #define AMDGPUFB_CONN_LIMIT 4 175 #define AMDGPU_BIOS_NUM_SCRATCH 16 176 177 /* hard reset data */ 178 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 179 180 /* reset flags */ 181 #define AMDGPU_RESET_GFX (1 << 0) 182 #define AMDGPU_RESET_COMPUTE (1 << 1) 183 #define AMDGPU_RESET_DMA (1 << 2) 184 #define AMDGPU_RESET_CP (1 << 3) 185 #define AMDGPU_RESET_GRBM (1 << 4) 186 #define AMDGPU_RESET_DMA1 (1 << 5) 187 #define AMDGPU_RESET_RLC (1 << 6) 188 #define AMDGPU_RESET_SEM (1 << 7) 189 #define AMDGPU_RESET_IH (1 << 8) 190 #define AMDGPU_RESET_VMC (1 << 9) 191 #define AMDGPU_RESET_MC (1 << 10) 192 #define AMDGPU_RESET_DISPLAY (1 << 11) 193 #define AMDGPU_RESET_UVD (1 << 12) 194 #define AMDGPU_RESET_VCE (1 << 13) 195 #define AMDGPU_RESET_VCE1 (1 << 14) 196 197 /* max cursor sizes (in pixels) */ 198 #define CIK_CURSOR_WIDTH 128 199 #define CIK_CURSOR_HEIGHT 128 200 201 struct amdgpu_device; 202 struct amdgpu_ib; 203 struct amdgpu_cs_parser; 204 struct amdgpu_job; 205 struct amdgpu_irq_src; 206 struct amdgpu_fpriv; 207 struct amdgpu_bo_va_mapping; 208 struct amdgpu_atif; 209 210 enum amdgpu_cp_irq { 211 AMDGPU_CP_IRQ_GFX_EOP = 0, 212 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 213 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 214 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 215 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 216 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 217 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 220 221 AMDGPU_CP_IRQ_LAST 222 }; 223 224 enum amdgpu_thermal_irq { 225 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 226 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 227 228 AMDGPU_THERMAL_IRQ_LAST 229 }; 230 231 enum amdgpu_kiq_irq { 232 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 233 AMDGPU_CP_KIQ_IRQ_LAST 234 }; 235 236 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 237 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 238 #define MAX_KIQ_REG_TRY 20 239 240 int amdgpu_device_ip_set_clockgating_state(void *dev, 241 enum amd_ip_block_type block_type, 242 enum amd_clockgating_state state); 243 int amdgpu_device_ip_set_powergating_state(void *dev, 244 enum amd_ip_block_type block_type, 245 enum amd_powergating_state state); 246 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 247 u32 *flags); 248 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 249 enum amd_ip_block_type block_type); 250 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 251 enum amd_ip_block_type block_type); 252 253 #define AMDGPU_MAX_IP_NUM 16 254 255 struct amdgpu_ip_block_status { 256 bool valid; 257 bool sw; 258 bool hw; 259 bool late_initialized; 260 bool hang; 261 }; 262 263 struct amdgpu_ip_block_version { 264 const enum amd_ip_block_type type; 265 const u32 major; 266 const u32 minor; 267 const u32 rev; 268 const struct amd_ip_funcs *funcs; 269 }; 270 271 struct amdgpu_ip_block { 272 struct amdgpu_ip_block_status status; 273 const struct amdgpu_ip_block_version *version; 274 }; 275 276 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 277 enum amd_ip_block_type type, 278 u32 major, u32 minor); 279 280 struct amdgpu_ip_block * 281 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 282 enum amd_ip_block_type type); 283 284 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 285 const struct amdgpu_ip_block_version *ip_block_version); 286 287 /* 288 * BIOS. 289 */ 290 bool amdgpu_get_bios(struct amdgpu_device *adev); 291 bool amdgpu_read_bios(struct amdgpu_device *adev); 292 293 /* 294 * Clocks 295 */ 296 297 #define AMDGPU_MAX_PPLL 3 298 299 struct amdgpu_clock { 300 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 301 struct amdgpu_pll spll; 302 struct amdgpu_pll mpll; 303 /* 10 Khz units */ 304 uint32_t default_mclk; 305 uint32_t default_sclk; 306 uint32_t default_dispclk; 307 uint32_t current_dispclk; 308 uint32_t dp_extclk; 309 uint32_t max_pixel_clock; 310 }; 311 312 /* sub-allocation manager, it has to be protected by another lock. 313 * By conception this is an helper for other part of the driver 314 * like the indirect buffer or semaphore, which both have their 315 * locking. 316 * 317 * Principe is simple, we keep a list of sub allocation in offset 318 * order (first entry has offset == 0, last entry has the highest 319 * offset). 320 * 321 * When allocating new object we first check if there is room at 322 * the end total_size - (last_object_offset + last_object_size) >= 323 * alloc_size. If so we allocate new object there. 324 * 325 * When there is not enough room at the end, we start waiting for 326 * each sub object until we reach object_offset+object_size >= 327 * alloc_size, this object then become the sub object we return. 328 * 329 * Alignment can't be bigger than page size. 330 * 331 * Hole are not considered for allocation to keep things simple. 332 * Assumption is that there won't be hole (all object on same 333 * alignment). 334 */ 335 336 #define AMDGPU_SA_NUM_FENCE_LISTS 32 337 338 struct amdgpu_sa_manager { 339 wait_queue_head_t wq; 340 struct amdgpu_bo *bo; 341 struct list_head *hole; 342 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 343 struct list_head olist; 344 unsigned size; 345 uint64_t gpu_addr; 346 void *cpu_ptr; 347 uint32_t domain; 348 uint32_t align; 349 }; 350 351 /* sub-allocation buffer */ 352 struct amdgpu_sa_bo { 353 struct list_head olist; 354 struct list_head flist; 355 struct amdgpu_sa_manager *manager; 356 unsigned soffset; 357 unsigned eoffset; 358 struct dma_fence *fence; 359 }; 360 361 int amdgpu_fence_slab_init(void); 362 void amdgpu_fence_slab_fini(void); 363 364 /* 365 * IRQS. 366 */ 367 368 struct amdgpu_flip_work { 369 struct delayed_work flip_work; 370 struct work_struct unpin_work; 371 struct amdgpu_device *adev; 372 int crtc_id; 373 u32 target_vblank; 374 uint64_t base; 375 struct drm_pending_vblank_event *event; 376 struct amdgpu_bo *old_abo; 377 struct dma_fence *excl; 378 unsigned shared_count; 379 struct dma_fence **shared; 380 struct dma_fence_cb cb; 381 bool async; 382 }; 383 384 385 /* 386 * CP & rings. 387 */ 388 389 struct amdgpu_ib { 390 struct amdgpu_sa_bo *sa_bo; 391 uint32_t length_dw; 392 uint64_t gpu_addr; 393 uint32_t *ptr; 394 uint32_t flags; 395 }; 396 397 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 398 399 /* 400 * file private structure 401 */ 402 403 struct amdgpu_fpriv { 404 struct amdgpu_vm vm; 405 struct amdgpu_bo_va *prt_va; 406 struct amdgpu_bo_va *csa_va; 407 struct mutex bo_list_lock; 408 struct idr bo_list_handles; 409 struct amdgpu_ctx_mgr ctx_mgr; 410 }; 411 412 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 413 unsigned size, struct amdgpu_ib *ib); 414 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 415 struct dma_fence *f); 416 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 417 struct amdgpu_ib *ibs, struct amdgpu_job *job, 418 struct dma_fence **f); 419 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 420 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 421 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 422 423 /* 424 * CS. 425 */ 426 struct amdgpu_cs_chunk { 427 uint32_t chunk_id; 428 uint32_t length_dw; 429 void *kdata; 430 }; 431 432 struct amdgpu_cs_parser { 433 struct amdgpu_device *adev; 434 struct drm_file *filp; 435 struct amdgpu_ctx *ctx; 436 437 /* chunks */ 438 unsigned nchunks; 439 struct amdgpu_cs_chunk *chunks; 440 441 /* scheduler job object */ 442 struct amdgpu_job *job; 443 struct drm_sched_entity *entity; 444 445 /* buffer objects */ 446 struct ww_acquire_ctx ticket; 447 struct amdgpu_bo_list *bo_list; 448 struct amdgpu_mn *mn; 449 struct amdgpu_bo_list_entry vm_pd; 450 struct list_head validated; 451 struct dma_fence *fence; 452 uint64_t bytes_moved_threshold; 453 uint64_t bytes_moved_vis_threshold; 454 uint64_t bytes_moved; 455 uint64_t bytes_moved_vis; 456 struct amdgpu_bo_list_entry *evictable; 457 458 /* user fence */ 459 struct amdgpu_bo_list_entry uf_entry; 460 461 unsigned num_post_dep_syncobjs; 462 struct drm_syncobj **post_dep_syncobjs; 463 }; 464 465 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 466 uint32_t ib_idx, int idx) 467 { 468 return p->job->ibs[ib_idx].ptr[idx]; 469 } 470 471 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 472 uint32_t ib_idx, int idx, 473 uint32_t value) 474 { 475 p->job->ibs[ib_idx].ptr[idx] = value; 476 } 477 478 /* 479 * Writeback 480 */ 481 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 482 483 struct amdgpu_wb { 484 struct amdgpu_bo *wb_obj; 485 volatile uint32_t *wb; 486 uint64_t gpu_addr; 487 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 488 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 489 }; 490 491 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 492 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 493 494 /* 495 * Benchmarking 496 */ 497 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 498 499 500 /* 501 * Testing 502 */ 503 void amdgpu_test_moves(struct amdgpu_device *adev); 504 505 /* 506 * ASIC specific register table accessible by UMD 507 */ 508 struct amdgpu_allowed_register_entry { 509 uint32_t reg_offset; 510 bool grbm_indexed; 511 }; 512 513 /* 514 * ASIC specific functions. 515 */ 516 struct amdgpu_asic_funcs { 517 bool (*read_disabled_bios)(struct amdgpu_device *adev); 518 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 519 u8 *bios, u32 length_bytes); 520 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 521 u32 sh_num, u32 reg_offset, u32 *value); 522 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 523 int (*reset)(struct amdgpu_device *adev); 524 /* get the reference clock */ 525 u32 (*get_xclk)(struct amdgpu_device *adev); 526 /* MM block clocks */ 527 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 528 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 529 /* static power management */ 530 int (*get_pcie_lanes)(struct amdgpu_device *adev); 531 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 532 /* get config memsize register */ 533 u32 (*get_config_memsize)(struct amdgpu_device *adev); 534 /* flush hdp write queue */ 535 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 536 /* invalidate hdp read cache */ 537 void (*invalidate_hdp)(struct amdgpu_device *adev, 538 struct amdgpu_ring *ring); 539 /* check if the asic needs a full reset of if soft reset will work */ 540 bool (*need_full_reset)(struct amdgpu_device *adev); 541 /* initialize doorbell layout for specific asic*/ 542 void (*init_doorbell_index)(struct amdgpu_device *adev); 543 }; 544 545 /* 546 * IOCTL. 547 */ 548 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 549 struct drm_file *filp); 550 551 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 552 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 553 struct drm_file *filp); 554 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 555 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 556 struct drm_file *filp); 557 558 /* VRAM scratch page for HDP bug, default vram page */ 559 struct amdgpu_vram_scratch { 560 struct amdgpu_bo *robj; 561 volatile uint32_t *ptr; 562 u64 gpu_addr; 563 }; 564 565 /* 566 * ACPI 567 */ 568 struct amdgpu_atcs_functions { 569 bool get_ext_state; 570 bool pcie_perf_req; 571 bool pcie_dev_rdy; 572 bool pcie_bus_width; 573 }; 574 575 struct amdgpu_atcs { 576 struct amdgpu_atcs_functions functions; 577 }; 578 579 /* 580 * Firmware VRAM reservation 581 */ 582 struct amdgpu_fw_vram_usage { 583 u64 start_offset; 584 u64 size; 585 struct amdgpu_bo *reserved_bo; 586 void *va; 587 }; 588 589 /* 590 * CGS 591 */ 592 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 593 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 594 595 /* 596 * Core structure, functions and helpers. 597 */ 598 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 599 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 600 601 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 602 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 603 604 605 /* 606 * amdgpu nbio functions 607 * 608 */ 609 struct nbio_hdp_flush_reg { 610 u32 ref_and_mask_cp0; 611 u32 ref_and_mask_cp1; 612 u32 ref_and_mask_cp2; 613 u32 ref_and_mask_cp3; 614 u32 ref_and_mask_cp4; 615 u32 ref_and_mask_cp5; 616 u32 ref_and_mask_cp6; 617 u32 ref_and_mask_cp7; 618 u32 ref_and_mask_cp8; 619 u32 ref_and_mask_cp9; 620 u32 ref_and_mask_sdma0; 621 u32 ref_and_mask_sdma1; 622 }; 623 624 struct amdgpu_nbio_funcs { 625 const struct nbio_hdp_flush_reg *hdp_flush_reg; 626 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 627 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 628 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 629 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 630 u32 (*get_rev_id)(struct amdgpu_device *adev); 631 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 632 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 633 u32 (*get_memsize)(struct amdgpu_device *adev); 634 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 635 bool use_doorbell, int doorbell_index); 636 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 637 bool enable); 638 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 639 bool enable); 640 void (*ih_doorbell_range)(struct amdgpu_device *adev, 641 bool use_doorbell, int doorbell_index); 642 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 643 bool enable); 644 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 645 bool enable); 646 void (*get_clockgating_state)(struct amdgpu_device *adev, 647 u32 *flags); 648 void (*ih_control)(struct amdgpu_device *adev); 649 void (*init_registers)(struct amdgpu_device *adev); 650 void (*detect_hw_virt)(struct amdgpu_device *adev); 651 }; 652 653 struct amdgpu_df_funcs { 654 void (*init)(struct amdgpu_device *adev); 655 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 656 bool enable); 657 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 658 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 659 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 660 bool enable); 661 void (*get_clockgating_state)(struct amdgpu_device *adev, 662 u32 *flags); 663 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 664 bool enable); 665 }; 666 /* Define the HW IP blocks will be used in driver , add more if necessary */ 667 enum amd_hw_ip_block_type { 668 GC_HWIP = 1, 669 HDP_HWIP, 670 SDMA0_HWIP, 671 SDMA1_HWIP, 672 MMHUB_HWIP, 673 ATHUB_HWIP, 674 NBIO_HWIP, 675 MP0_HWIP, 676 MP1_HWIP, 677 UVD_HWIP, 678 VCN_HWIP = UVD_HWIP, 679 VCE_HWIP, 680 DF_HWIP, 681 DCE_HWIP, 682 OSSSYS_HWIP, 683 SMUIO_HWIP, 684 PWR_HWIP, 685 NBIF_HWIP, 686 THM_HWIP, 687 CLK_HWIP, 688 MAX_HWIP 689 }; 690 691 #define HWIP_MAX_INSTANCE 6 692 693 struct amd_powerplay { 694 void *pp_handle; 695 const struct amd_pm_funcs *pp_funcs; 696 uint32_t pp_feature; 697 }; 698 699 #define AMDGPU_RESET_MAGIC_NUM 64 700 struct amdgpu_device { 701 struct device *dev; 702 struct drm_device *ddev; 703 struct pci_dev *pdev; 704 705 #ifdef CONFIG_DRM_AMD_ACP 706 struct amdgpu_acp acp; 707 #endif 708 709 /* ASIC */ 710 enum amd_asic_type asic_type; 711 uint32_t family; 712 uint32_t rev_id; 713 uint32_t external_rev_id; 714 unsigned long flags; 715 int usec_timeout; 716 const struct amdgpu_asic_funcs *asic_funcs; 717 bool shutdown; 718 bool need_dma32; 719 bool need_swiotlb; 720 bool accel_working; 721 struct notifier_block acpi_nb; 722 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 723 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 724 unsigned debugfs_count; 725 #if defined(CONFIG_DEBUG_FS) 726 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 727 #endif 728 struct amdgpu_atif *atif; 729 struct amdgpu_atcs atcs; 730 struct mutex srbm_mutex; 731 /* GRBM index mutex. Protects concurrent access to GRBM index */ 732 struct mutex grbm_idx_mutex; 733 struct dev_pm_domain vga_pm_domain; 734 bool have_disp_power_ref; 735 736 /* BIOS */ 737 bool is_atom_fw; 738 uint8_t *bios; 739 uint32_t bios_size; 740 struct amdgpu_bo *stolen_vga_memory; 741 uint32_t bios_scratch_reg_offset; 742 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 743 744 /* Register/doorbell mmio */ 745 resource_size_t rmmio_base; 746 resource_size_t rmmio_size; 747 void __iomem *rmmio; 748 /* protects concurrent MM_INDEX/DATA based register access */ 749 spinlock_t mmio_idx_lock; 750 /* protects concurrent SMC based register access */ 751 spinlock_t smc_idx_lock; 752 amdgpu_rreg_t smc_rreg; 753 amdgpu_wreg_t smc_wreg; 754 /* protects concurrent PCIE register access */ 755 spinlock_t pcie_idx_lock; 756 amdgpu_rreg_t pcie_rreg; 757 amdgpu_wreg_t pcie_wreg; 758 amdgpu_rreg_t pciep_rreg; 759 amdgpu_wreg_t pciep_wreg; 760 /* protects concurrent UVD register access */ 761 spinlock_t uvd_ctx_idx_lock; 762 amdgpu_rreg_t uvd_ctx_rreg; 763 amdgpu_wreg_t uvd_ctx_wreg; 764 /* protects concurrent DIDT register access */ 765 spinlock_t didt_idx_lock; 766 amdgpu_rreg_t didt_rreg; 767 amdgpu_wreg_t didt_wreg; 768 /* protects concurrent gc_cac register access */ 769 spinlock_t gc_cac_idx_lock; 770 amdgpu_rreg_t gc_cac_rreg; 771 amdgpu_wreg_t gc_cac_wreg; 772 /* protects concurrent se_cac register access */ 773 spinlock_t se_cac_idx_lock; 774 amdgpu_rreg_t se_cac_rreg; 775 amdgpu_wreg_t se_cac_wreg; 776 /* protects concurrent ENDPOINT (audio) register access */ 777 spinlock_t audio_endpt_idx_lock; 778 amdgpu_block_rreg_t audio_endpt_rreg; 779 amdgpu_block_wreg_t audio_endpt_wreg; 780 void __iomem *rio_mem; 781 resource_size_t rio_mem_size; 782 struct amdgpu_doorbell doorbell; 783 784 /* clock/pll info */ 785 struct amdgpu_clock clock; 786 787 /* MC */ 788 struct amdgpu_gmc gmc; 789 struct amdgpu_gart gart; 790 dma_addr_t dummy_page_addr; 791 struct amdgpu_vm_manager vm_manager; 792 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 793 794 /* memory management */ 795 struct amdgpu_mman mman; 796 struct amdgpu_vram_scratch vram_scratch; 797 struct amdgpu_wb wb; 798 atomic64_t num_bytes_moved; 799 atomic64_t num_evictions; 800 atomic64_t num_vram_cpu_page_faults; 801 atomic_t gpu_reset_counter; 802 atomic_t vram_lost_counter; 803 804 /* data for buffer migration throttling */ 805 struct { 806 spinlock_t lock; 807 s64 last_update_us; 808 s64 accum_us; /* accumulated microseconds */ 809 s64 accum_us_vis; /* for visible VRAM */ 810 u32 log2_max_MBps; 811 } mm_stats; 812 813 /* display */ 814 bool enable_virtual_display; 815 struct amdgpu_mode_info mode_info; 816 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 817 struct work_struct hotplug_work; 818 struct amdgpu_irq_src crtc_irq; 819 struct amdgpu_irq_src pageflip_irq; 820 struct amdgpu_irq_src hpd_irq; 821 822 /* rings */ 823 u64 fence_context; 824 unsigned num_rings; 825 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 826 bool ib_pool_ready; 827 struct amdgpu_sa_manager ring_tmp_bo; 828 829 /* interrupts */ 830 struct amdgpu_irq irq; 831 832 /* powerplay */ 833 struct amd_powerplay powerplay; 834 bool pp_force_state_enabled; 835 836 /* dpm */ 837 struct amdgpu_pm pm; 838 u32 cg_flags; 839 u32 pg_flags; 840 841 /* gfx */ 842 struct amdgpu_gfx gfx; 843 844 /* sdma */ 845 struct amdgpu_sdma sdma; 846 847 /* uvd */ 848 struct amdgpu_uvd uvd; 849 850 /* vce */ 851 struct amdgpu_vce vce; 852 853 /* vcn */ 854 struct amdgpu_vcn vcn; 855 856 /* firmwares */ 857 struct amdgpu_firmware firmware; 858 859 /* PSP */ 860 struct psp_context psp; 861 862 /* GDS */ 863 struct amdgpu_gds gds; 864 865 /* display related functionality */ 866 struct amdgpu_display_manager dm; 867 868 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 869 int num_ip_blocks; 870 struct mutex mn_lock; 871 DECLARE_HASHTABLE(mn_hash, 7); 872 873 /* tracking pinned memory */ 874 atomic64_t vram_pin_size; 875 atomic64_t visible_pin_size; 876 atomic64_t gart_pin_size; 877 878 /* amdkfd interface */ 879 struct kfd_dev *kfd; 880 881 /* soc15 register offset based on ip, instance and segment */ 882 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 883 884 const struct amdgpu_nbio_funcs *nbio_funcs; 885 const struct amdgpu_df_funcs *df_funcs; 886 887 /* delayed work_func for deferring clockgating during resume */ 888 struct delayed_work late_init_work; 889 890 struct amdgpu_virt virt; 891 /* firmware VRAM reservation */ 892 struct amdgpu_fw_vram_usage fw_vram_usage; 893 894 /* link all shadow bo */ 895 struct list_head shadow_list; 896 struct mutex shadow_list_lock; 897 /* keep an lru list of rings by HW IP */ 898 struct list_head ring_lru_list; 899 spinlock_t ring_lru_list_lock; 900 901 /* record hw reset is performed */ 902 bool has_hw_reset; 903 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 904 905 /* s3/s4 mask */ 906 bool in_suspend; 907 908 /* record last mm index being written through WREG32*/ 909 unsigned long last_mm_index; 910 bool in_gpu_reset; 911 struct mutex lock_reset; 912 struct amdgpu_doorbell_index doorbell_index; 913 914 int asic_reset_res; 915 struct work_struct xgmi_reset_work; 916 }; 917 918 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 919 { 920 return container_of(bdev, struct amdgpu_device, mman.bdev); 921 } 922 923 int amdgpu_device_init(struct amdgpu_device *adev, 924 struct drm_device *ddev, 925 struct pci_dev *pdev, 926 uint32_t flags); 927 void amdgpu_device_fini(struct amdgpu_device *adev); 928 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 929 930 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 931 uint32_t acc_flags); 932 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 933 uint32_t acc_flags); 934 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 935 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 936 937 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 938 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 939 940 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 941 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 942 943 int emu_soc_asic_init(struct amdgpu_device *adev); 944 945 /* 946 * Registers read & write functions. 947 */ 948 949 #define AMDGPU_REGS_IDX (1<<0) 950 #define AMDGPU_REGS_NO_KIQ (1<<1) 951 952 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 953 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 954 955 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 956 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 957 958 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 959 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 960 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 961 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 962 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 963 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 964 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 965 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 966 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 967 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 968 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 969 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 970 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 971 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 972 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 973 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 974 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 975 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 976 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 977 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 978 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 979 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 980 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 981 #define WREG32_P(reg, val, mask) \ 982 do { \ 983 uint32_t tmp_ = RREG32(reg); \ 984 tmp_ &= (mask); \ 985 tmp_ |= ((val) & ~(mask)); \ 986 WREG32(reg, tmp_); \ 987 } while (0) 988 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 989 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 990 #define WREG32_PLL_P(reg, val, mask) \ 991 do { \ 992 uint32_t tmp_ = RREG32_PLL(reg); \ 993 tmp_ &= (mask); \ 994 tmp_ |= ((val) & ~(mask)); \ 995 WREG32_PLL(reg, tmp_); \ 996 } while (0) 997 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 998 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 999 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1000 1001 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1002 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1003 1004 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1005 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1006 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1007 1008 #define REG_GET_FIELD(value, reg, field) \ 1009 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1010 1011 #define WREG32_FIELD(reg, field, val) \ 1012 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1013 1014 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1015 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1016 1017 /* 1018 * BIOS helpers. 1019 */ 1020 #define RBIOS8(i) (adev->bios[i]) 1021 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1022 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1023 1024 /* 1025 * ASICs macro. 1026 */ 1027 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1028 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1029 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1030 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1031 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1032 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1033 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1034 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1035 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1036 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1037 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1038 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1039 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1040 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1041 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1042 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1043 1044 /* Common functions */ 1045 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1046 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1047 struct amdgpu_job* job); 1048 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1049 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1050 1051 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1052 u64 num_vis_bytes); 1053 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1054 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1055 const u32 *registers, 1056 const u32 array_size); 1057 1058 bool amdgpu_device_is_px(struct drm_device *dev); 1059 /* atpx handler */ 1060 #if defined(CONFIG_VGA_SWITCHEROO) 1061 void amdgpu_register_atpx_handler(void); 1062 void amdgpu_unregister_atpx_handler(void); 1063 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1064 bool amdgpu_is_atpx_hybrid(void); 1065 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1066 bool amdgpu_has_atpx(void); 1067 #else 1068 static inline void amdgpu_register_atpx_handler(void) {} 1069 static inline void amdgpu_unregister_atpx_handler(void) {} 1070 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1071 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1072 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1073 static inline bool amdgpu_has_atpx(void) { return false; } 1074 #endif 1075 1076 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1077 void *amdgpu_atpx_get_dhandle(void); 1078 #else 1079 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1080 #endif 1081 1082 /* 1083 * KMS 1084 */ 1085 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1086 extern const int amdgpu_max_kms_ioctl; 1087 1088 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1089 void amdgpu_driver_unload_kms(struct drm_device *dev); 1090 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1091 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1092 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1093 struct drm_file *file_priv); 1094 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1095 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1096 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1097 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1098 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1099 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1100 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1101 unsigned long arg); 1102 1103 /* 1104 * functions used by amdgpu_encoder.c 1105 */ 1106 struct amdgpu_afmt_acr { 1107 u32 clock; 1108 1109 int n_32khz; 1110 int cts_32khz; 1111 1112 int n_44_1khz; 1113 int cts_44_1khz; 1114 1115 int n_48khz; 1116 int cts_48khz; 1117 1118 }; 1119 1120 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1121 1122 /* amdgpu_acpi.c */ 1123 #if defined(CONFIG_ACPI) 1124 int amdgpu_acpi_init(struct amdgpu_device *adev); 1125 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1126 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1127 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1128 u8 perf_req, bool advertise); 1129 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1130 1131 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1132 struct amdgpu_dm_backlight_caps *caps); 1133 #else 1134 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1135 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1136 #endif 1137 1138 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1139 uint64_t addr, struct amdgpu_bo **bo, 1140 struct amdgpu_bo_va_mapping **mapping); 1141 1142 #if defined(CONFIG_DRM_AMD_DC) 1143 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1144 #else 1145 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1146 #endif 1147 1148 #include "amdgpu_object.h" 1149 #endif 1150