1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include "amdgpu_ctx.h" 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/rbtree.h> 38 #include <linux/hashtable.h> 39 #include <linux/dma-fence.h> 40 41 #include <drm/ttm/ttm_bo_api.h> 42 #include <drm/ttm/ttm_bo_driver.h> 43 #include <drm/ttm/ttm_placement.h> 44 #include <drm/ttm/ttm_module.h> 45 #include <drm/ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 #include <drm/gpu_scheduler.h> 51 52 #include <kgd_kfd_interface.h> 53 #include "dm_pp_interface.h" 54 #include "kgd_pp_interface.h" 55 56 #include "amd_shared.h" 57 #include "amdgpu_mode.h" 58 #include "amdgpu_ih.h" 59 #include "amdgpu_irq.h" 60 #include "amdgpu_ucode.h" 61 #include "amdgpu_ttm.h" 62 #include "amdgpu_psp.h" 63 #include "amdgpu_gds.h" 64 #include "amdgpu_sync.h" 65 #include "amdgpu_ring.h" 66 #include "amdgpu_vm.h" 67 #include "amdgpu_dpm.h" 68 #include "amdgpu_acp.h" 69 #include "amdgpu_uvd.h" 70 #include "amdgpu_vce.h" 71 #include "amdgpu_vcn.h" 72 #include "amdgpu_mn.h" 73 #include "amdgpu_gmc.h" 74 #include "amdgpu_gfx.h" 75 #include "amdgpu_sdma.h" 76 #include "amdgpu_dm.h" 77 #include "amdgpu_virt.h" 78 #include "amdgpu_csa.h" 79 #include "amdgpu_gart.h" 80 #include "amdgpu_debugfs.h" 81 #include "amdgpu_job.h" 82 #include "amdgpu_bo_list.h" 83 #include "amdgpu_gem.h" 84 #include "amdgpu_doorbell.h" 85 #include "amdgpu_amdkfd.h" 86 #include "amdgpu_smu.h" 87 88 #define MAX_GPU_INSTANCE 16 89 90 struct amdgpu_gpu_instance 91 { 92 struct amdgpu_device *adev; 93 int mgpu_fan_enabled; 94 }; 95 96 struct amdgpu_mgpu_info 97 { 98 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 99 struct mutex mutex; 100 uint32_t num_gpu; 101 uint32_t num_dgpu; 102 uint32_t num_apu; 103 }; 104 105 /* 106 * Modules parameters. 107 */ 108 extern int amdgpu_modeset; 109 extern int amdgpu_vram_limit; 110 extern int amdgpu_vis_vram_limit; 111 extern int amdgpu_gart_size; 112 extern int amdgpu_gtt_size; 113 extern int amdgpu_moverate; 114 extern int amdgpu_benchmarking; 115 extern int amdgpu_testing; 116 extern int amdgpu_audio; 117 extern int amdgpu_disp_priority; 118 extern int amdgpu_hw_i2c; 119 extern int amdgpu_pcie_gen2; 120 extern int amdgpu_msi; 121 extern int amdgpu_lockup_timeout; 122 extern int amdgpu_dpm; 123 extern int amdgpu_fw_load_type; 124 extern int amdgpu_aspm; 125 extern int amdgpu_runtime_pm; 126 extern uint amdgpu_ip_block_mask; 127 extern int amdgpu_bapm; 128 extern int amdgpu_deep_color; 129 extern int amdgpu_vm_size; 130 extern int amdgpu_vm_block_size; 131 extern int amdgpu_vm_fragment_size; 132 extern int amdgpu_vm_fault_stop; 133 extern int amdgpu_vm_debug; 134 extern int amdgpu_vm_update_mode; 135 extern int amdgpu_dc; 136 extern int amdgpu_sched_jobs; 137 extern int amdgpu_sched_hw_submission; 138 extern uint amdgpu_pcie_gen_cap; 139 extern uint amdgpu_pcie_lane_cap; 140 extern uint amdgpu_cg_mask; 141 extern uint amdgpu_pg_mask; 142 extern uint amdgpu_sdma_phase_quantum; 143 extern char *amdgpu_disable_cu; 144 extern char *amdgpu_virtual_display; 145 extern uint amdgpu_pp_feature_mask; 146 extern int amdgpu_vram_page_split; 147 extern int amdgpu_ngg; 148 extern int amdgpu_prim_buf_per_se; 149 extern int amdgpu_pos_buf_per_se; 150 extern int amdgpu_cntl_sb_buf_per_se; 151 extern int amdgpu_param_buf_per_se; 152 extern int amdgpu_job_hang_limit; 153 extern int amdgpu_lbpw; 154 extern int amdgpu_compute_multipipe; 155 extern int amdgpu_gpu_recovery; 156 extern int amdgpu_emu_mode; 157 extern uint amdgpu_smu_memory_pool_size; 158 extern uint amdgpu_dc_feature_mask; 159 extern struct amdgpu_mgpu_info mgpu_info; 160 extern int amdgpu_ras_enable; 161 extern uint amdgpu_ras_mask; 162 163 #ifdef CONFIG_DRM_AMDGPU_SI 164 extern int amdgpu_si_support; 165 #endif 166 #ifdef CONFIG_DRM_AMDGPU_CIK 167 extern int amdgpu_cik_support; 168 #endif 169 170 #define AMDGPU_VM_MAX_NUM_CTX 4096 171 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 172 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 173 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 174 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 175 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 176 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 177 #define AMDGPU_IB_POOL_SIZE 16 178 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 179 #define AMDGPUFB_CONN_LIMIT 4 180 #define AMDGPU_BIOS_NUM_SCRATCH 16 181 182 /* hard reset data */ 183 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 184 185 /* reset flags */ 186 #define AMDGPU_RESET_GFX (1 << 0) 187 #define AMDGPU_RESET_COMPUTE (1 << 1) 188 #define AMDGPU_RESET_DMA (1 << 2) 189 #define AMDGPU_RESET_CP (1 << 3) 190 #define AMDGPU_RESET_GRBM (1 << 4) 191 #define AMDGPU_RESET_DMA1 (1 << 5) 192 #define AMDGPU_RESET_RLC (1 << 6) 193 #define AMDGPU_RESET_SEM (1 << 7) 194 #define AMDGPU_RESET_IH (1 << 8) 195 #define AMDGPU_RESET_VMC (1 << 9) 196 #define AMDGPU_RESET_MC (1 << 10) 197 #define AMDGPU_RESET_DISPLAY (1 << 11) 198 #define AMDGPU_RESET_UVD (1 << 12) 199 #define AMDGPU_RESET_VCE (1 << 13) 200 #define AMDGPU_RESET_VCE1 (1 << 14) 201 202 /* max cursor sizes (in pixels) */ 203 #define CIK_CURSOR_WIDTH 128 204 #define CIK_CURSOR_HEIGHT 128 205 206 struct amdgpu_device; 207 struct amdgpu_ib; 208 struct amdgpu_cs_parser; 209 struct amdgpu_job; 210 struct amdgpu_irq_src; 211 struct amdgpu_fpriv; 212 struct amdgpu_bo_va_mapping; 213 struct amdgpu_atif; 214 215 enum amdgpu_cp_irq { 216 AMDGPU_CP_IRQ_GFX_EOP = 0, 217 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 218 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 219 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 220 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 221 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 222 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 223 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 224 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 225 226 AMDGPU_CP_IRQ_LAST 227 }; 228 229 enum amdgpu_thermal_irq { 230 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 231 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 232 233 AMDGPU_THERMAL_IRQ_LAST 234 }; 235 236 enum amdgpu_kiq_irq { 237 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 238 AMDGPU_CP_KIQ_IRQ_LAST 239 }; 240 241 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 242 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 243 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 244 245 int amdgpu_device_ip_set_clockgating_state(void *dev, 246 enum amd_ip_block_type block_type, 247 enum amd_clockgating_state state); 248 int amdgpu_device_ip_set_powergating_state(void *dev, 249 enum amd_ip_block_type block_type, 250 enum amd_powergating_state state); 251 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 252 u32 *flags); 253 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 254 enum amd_ip_block_type block_type); 255 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 256 enum amd_ip_block_type block_type); 257 258 #define AMDGPU_MAX_IP_NUM 16 259 260 struct amdgpu_ip_block_status { 261 bool valid; 262 bool sw; 263 bool hw; 264 bool late_initialized; 265 bool hang; 266 }; 267 268 struct amdgpu_ip_block_version { 269 const enum amd_ip_block_type type; 270 const u32 major; 271 const u32 minor; 272 const u32 rev; 273 const struct amd_ip_funcs *funcs; 274 }; 275 276 struct amdgpu_ip_block { 277 struct amdgpu_ip_block_status status; 278 const struct amdgpu_ip_block_version *version; 279 }; 280 281 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 282 enum amd_ip_block_type type, 283 u32 major, u32 minor); 284 285 struct amdgpu_ip_block * 286 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 287 enum amd_ip_block_type type); 288 289 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 290 const struct amdgpu_ip_block_version *ip_block_version); 291 292 /* 293 * BIOS. 294 */ 295 bool amdgpu_get_bios(struct amdgpu_device *adev); 296 bool amdgpu_read_bios(struct amdgpu_device *adev); 297 298 /* 299 * Clocks 300 */ 301 302 #define AMDGPU_MAX_PPLL 3 303 304 struct amdgpu_clock { 305 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 306 struct amdgpu_pll spll; 307 struct amdgpu_pll mpll; 308 /* 10 Khz units */ 309 uint32_t default_mclk; 310 uint32_t default_sclk; 311 uint32_t default_dispclk; 312 uint32_t current_dispclk; 313 uint32_t dp_extclk; 314 uint32_t max_pixel_clock; 315 }; 316 317 /* sub-allocation manager, it has to be protected by another lock. 318 * By conception this is an helper for other part of the driver 319 * like the indirect buffer or semaphore, which both have their 320 * locking. 321 * 322 * Principe is simple, we keep a list of sub allocation in offset 323 * order (first entry has offset == 0, last entry has the highest 324 * offset). 325 * 326 * When allocating new object we first check if there is room at 327 * the end total_size - (last_object_offset + last_object_size) >= 328 * alloc_size. If so we allocate new object there. 329 * 330 * When there is not enough room at the end, we start waiting for 331 * each sub object until we reach object_offset+object_size >= 332 * alloc_size, this object then become the sub object we return. 333 * 334 * Alignment can't be bigger than page size. 335 * 336 * Hole are not considered for allocation to keep things simple. 337 * Assumption is that there won't be hole (all object on same 338 * alignment). 339 */ 340 341 #define AMDGPU_SA_NUM_FENCE_LISTS 32 342 343 struct amdgpu_sa_manager { 344 wait_queue_head_t wq; 345 struct amdgpu_bo *bo; 346 struct list_head *hole; 347 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 348 struct list_head olist; 349 unsigned size; 350 uint64_t gpu_addr; 351 void *cpu_ptr; 352 uint32_t domain; 353 uint32_t align; 354 }; 355 356 /* sub-allocation buffer */ 357 struct amdgpu_sa_bo { 358 struct list_head olist; 359 struct list_head flist; 360 struct amdgpu_sa_manager *manager; 361 unsigned soffset; 362 unsigned eoffset; 363 struct dma_fence *fence; 364 }; 365 366 int amdgpu_fence_slab_init(void); 367 void amdgpu_fence_slab_fini(void); 368 369 /* 370 * IRQS. 371 */ 372 373 struct amdgpu_flip_work { 374 struct delayed_work flip_work; 375 struct work_struct unpin_work; 376 struct amdgpu_device *adev; 377 int crtc_id; 378 u32 target_vblank; 379 uint64_t base; 380 struct drm_pending_vblank_event *event; 381 struct amdgpu_bo *old_abo; 382 struct dma_fence *excl; 383 unsigned shared_count; 384 struct dma_fence **shared; 385 struct dma_fence_cb cb; 386 bool async; 387 }; 388 389 390 /* 391 * CP & rings. 392 */ 393 394 struct amdgpu_ib { 395 struct amdgpu_sa_bo *sa_bo; 396 uint32_t length_dw; 397 uint64_t gpu_addr; 398 uint32_t *ptr; 399 uint32_t flags; 400 }; 401 402 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 403 404 /* 405 * file private structure 406 */ 407 408 struct amdgpu_fpriv { 409 struct amdgpu_vm vm; 410 struct amdgpu_bo_va *prt_va; 411 struct amdgpu_bo_va *csa_va; 412 struct mutex bo_list_lock; 413 struct idr bo_list_handles; 414 struct amdgpu_ctx_mgr ctx_mgr; 415 }; 416 417 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 418 419 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 420 unsigned size, struct amdgpu_ib *ib); 421 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 422 struct dma_fence *f); 423 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 424 struct amdgpu_ib *ibs, struct amdgpu_job *job, 425 struct dma_fence **f); 426 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 427 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 428 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 429 430 /* 431 * CS. 432 */ 433 struct amdgpu_cs_chunk { 434 uint32_t chunk_id; 435 uint32_t length_dw; 436 void *kdata; 437 }; 438 439 struct amdgpu_cs_post_dep { 440 struct drm_syncobj *syncobj; 441 struct dma_fence_chain *chain; 442 u64 point; 443 }; 444 445 struct amdgpu_cs_parser { 446 struct amdgpu_device *adev; 447 struct drm_file *filp; 448 struct amdgpu_ctx *ctx; 449 450 /* chunks */ 451 unsigned nchunks; 452 struct amdgpu_cs_chunk *chunks; 453 454 /* scheduler job object */ 455 struct amdgpu_job *job; 456 struct drm_sched_entity *entity; 457 458 /* buffer objects */ 459 struct ww_acquire_ctx ticket; 460 struct amdgpu_bo_list *bo_list; 461 struct amdgpu_mn *mn; 462 struct amdgpu_bo_list_entry vm_pd; 463 struct list_head validated; 464 struct dma_fence *fence; 465 uint64_t bytes_moved_threshold; 466 uint64_t bytes_moved_vis_threshold; 467 uint64_t bytes_moved; 468 uint64_t bytes_moved_vis; 469 struct amdgpu_bo_list_entry *evictable; 470 471 /* user fence */ 472 struct amdgpu_bo_list_entry uf_entry; 473 474 unsigned num_post_deps; 475 struct amdgpu_cs_post_dep *post_deps; 476 }; 477 478 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 479 uint32_t ib_idx, int idx) 480 { 481 return p->job->ibs[ib_idx].ptr[idx]; 482 } 483 484 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 485 uint32_t ib_idx, int idx, 486 uint32_t value) 487 { 488 p->job->ibs[ib_idx].ptr[idx] = value; 489 } 490 491 /* 492 * Writeback 493 */ 494 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 495 496 struct amdgpu_wb { 497 struct amdgpu_bo *wb_obj; 498 volatile uint32_t *wb; 499 uint64_t gpu_addr; 500 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 501 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 502 }; 503 504 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 505 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 506 507 /* 508 * Benchmarking 509 */ 510 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 511 512 513 /* 514 * Testing 515 */ 516 void amdgpu_test_moves(struct amdgpu_device *adev); 517 518 /* 519 * ASIC specific register table accessible by UMD 520 */ 521 struct amdgpu_allowed_register_entry { 522 uint32_t reg_offset; 523 bool grbm_indexed; 524 }; 525 526 /* 527 * ASIC specific functions. 528 */ 529 struct amdgpu_asic_funcs { 530 bool (*read_disabled_bios)(struct amdgpu_device *adev); 531 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 532 u8 *bios, u32 length_bytes); 533 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 534 u32 sh_num, u32 reg_offset, u32 *value); 535 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 536 int (*reset)(struct amdgpu_device *adev); 537 /* get the reference clock */ 538 u32 (*get_xclk)(struct amdgpu_device *adev); 539 /* MM block clocks */ 540 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 541 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 542 /* static power management */ 543 int (*get_pcie_lanes)(struct amdgpu_device *adev); 544 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 545 /* get config memsize register */ 546 u32 (*get_config_memsize)(struct amdgpu_device *adev); 547 /* flush hdp write queue */ 548 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 549 /* invalidate hdp read cache */ 550 void (*invalidate_hdp)(struct amdgpu_device *adev, 551 struct amdgpu_ring *ring); 552 /* check if the asic needs a full reset of if soft reset will work */ 553 bool (*need_full_reset)(struct amdgpu_device *adev); 554 /* initialize doorbell layout for specific asic*/ 555 void (*init_doorbell_index)(struct amdgpu_device *adev); 556 /* PCIe bandwidth usage */ 557 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 558 uint64_t *count1); 559 /* do we need to reset the asic at init time (e.g., kexec) */ 560 bool (*need_reset_on_init)(struct amdgpu_device *adev); 561 }; 562 563 /* 564 * IOCTL. 565 */ 566 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 567 struct drm_file *filp); 568 569 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 570 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 571 struct drm_file *filp); 572 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 573 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 574 struct drm_file *filp); 575 576 /* VRAM scratch page for HDP bug, default vram page */ 577 struct amdgpu_vram_scratch { 578 struct amdgpu_bo *robj; 579 volatile uint32_t *ptr; 580 u64 gpu_addr; 581 }; 582 583 /* 584 * ACPI 585 */ 586 struct amdgpu_atcs_functions { 587 bool get_ext_state; 588 bool pcie_perf_req; 589 bool pcie_dev_rdy; 590 bool pcie_bus_width; 591 }; 592 593 struct amdgpu_atcs { 594 struct amdgpu_atcs_functions functions; 595 }; 596 597 /* 598 * Firmware VRAM reservation 599 */ 600 struct amdgpu_fw_vram_usage { 601 u64 start_offset; 602 u64 size; 603 struct amdgpu_bo *reserved_bo; 604 void *va; 605 }; 606 607 /* 608 * CGS 609 */ 610 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 611 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 612 613 /* 614 * Core structure, functions and helpers. 615 */ 616 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 617 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 618 619 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 620 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 621 622 623 /* 624 * amdgpu nbio functions 625 * 626 */ 627 struct nbio_hdp_flush_reg { 628 u32 ref_and_mask_cp0; 629 u32 ref_and_mask_cp1; 630 u32 ref_and_mask_cp2; 631 u32 ref_and_mask_cp3; 632 u32 ref_and_mask_cp4; 633 u32 ref_and_mask_cp5; 634 u32 ref_and_mask_cp6; 635 u32 ref_and_mask_cp7; 636 u32 ref_and_mask_cp8; 637 u32 ref_and_mask_cp9; 638 u32 ref_and_mask_sdma0; 639 u32 ref_and_mask_sdma1; 640 }; 641 642 struct amdgpu_nbio_funcs { 643 const struct nbio_hdp_flush_reg *hdp_flush_reg; 644 u32 (*get_hdp_flush_req_offset)(struct amdgpu_device *adev); 645 u32 (*get_hdp_flush_done_offset)(struct amdgpu_device *adev); 646 u32 (*get_pcie_index_offset)(struct amdgpu_device *adev); 647 u32 (*get_pcie_data_offset)(struct amdgpu_device *adev); 648 u32 (*get_rev_id)(struct amdgpu_device *adev); 649 void (*mc_access_enable)(struct amdgpu_device *adev, bool enable); 650 void (*hdp_flush)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 651 u32 (*get_memsize)(struct amdgpu_device *adev); 652 void (*sdma_doorbell_range)(struct amdgpu_device *adev, int instance, 653 bool use_doorbell, int doorbell_index, int doorbell_size); 654 void (*enable_doorbell_aperture)(struct amdgpu_device *adev, 655 bool enable); 656 void (*enable_doorbell_selfring_aperture)(struct amdgpu_device *adev, 657 bool enable); 658 void (*ih_doorbell_range)(struct amdgpu_device *adev, 659 bool use_doorbell, int doorbell_index); 660 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 661 bool enable); 662 void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 663 bool enable); 664 void (*get_clockgating_state)(struct amdgpu_device *adev, 665 u32 *flags); 666 void (*ih_control)(struct amdgpu_device *adev); 667 void (*init_registers)(struct amdgpu_device *adev); 668 void (*detect_hw_virt)(struct amdgpu_device *adev); 669 }; 670 671 struct amdgpu_df_funcs { 672 void (*init)(struct amdgpu_device *adev); 673 void (*enable_broadcast_mode)(struct amdgpu_device *adev, 674 bool enable); 675 u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 676 u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 677 void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 678 bool enable); 679 void (*get_clockgating_state)(struct amdgpu_device *adev, 680 u32 *flags); 681 void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 682 bool enable); 683 }; 684 /* Define the HW IP blocks will be used in driver , add more if necessary */ 685 enum amd_hw_ip_block_type { 686 GC_HWIP = 1, 687 HDP_HWIP, 688 SDMA0_HWIP, 689 SDMA1_HWIP, 690 MMHUB_HWIP, 691 ATHUB_HWIP, 692 NBIO_HWIP, 693 MP0_HWIP, 694 MP1_HWIP, 695 UVD_HWIP, 696 VCN_HWIP = UVD_HWIP, 697 VCE_HWIP, 698 DF_HWIP, 699 DCE_HWIP, 700 OSSSYS_HWIP, 701 SMUIO_HWIP, 702 PWR_HWIP, 703 NBIF_HWIP, 704 THM_HWIP, 705 CLK_HWIP, 706 MAX_HWIP 707 }; 708 709 #define HWIP_MAX_INSTANCE 6 710 711 struct amd_powerplay { 712 void *pp_handle; 713 const struct amd_pm_funcs *pp_funcs; 714 }; 715 716 #define AMDGPU_RESET_MAGIC_NUM 64 717 struct amdgpu_device { 718 struct device *dev; 719 struct drm_device *ddev; 720 struct pci_dev *pdev; 721 722 #ifdef CONFIG_DRM_AMD_ACP 723 struct amdgpu_acp acp; 724 #endif 725 726 /* ASIC */ 727 enum amd_asic_type asic_type; 728 uint32_t family; 729 uint32_t rev_id; 730 uint32_t external_rev_id; 731 unsigned long flags; 732 int usec_timeout; 733 const struct amdgpu_asic_funcs *asic_funcs; 734 bool shutdown; 735 bool need_dma32; 736 bool need_swiotlb; 737 bool accel_working; 738 struct notifier_block acpi_nb; 739 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 740 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 741 unsigned debugfs_count; 742 #if defined(CONFIG_DEBUG_FS) 743 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 744 #endif 745 struct amdgpu_atif *atif; 746 struct amdgpu_atcs atcs; 747 struct mutex srbm_mutex; 748 /* GRBM index mutex. Protects concurrent access to GRBM index */ 749 struct mutex grbm_idx_mutex; 750 struct dev_pm_domain vga_pm_domain; 751 bool have_disp_power_ref; 752 753 /* BIOS */ 754 bool is_atom_fw; 755 uint8_t *bios; 756 uint32_t bios_size; 757 struct amdgpu_bo *stolen_vga_memory; 758 uint32_t bios_scratch_reg_offset; 759 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 760 761 /* Register/doorbell mmio */ 762 resource_size_t rmmio_base; 763 resource_size_t rmmio_size; 764 void __iomem *rmmio; 765 /* protects concurrent MM_INDEX/DATA based register access */ 766 spinlock_t mmio_idx_lock; 767 /* protects concurrent SMC based register access */ 768 spinlock_t smc_idx_lock; 769 amdgpu_rreg_t smc_rreg; 770 amdgpu_wreg_t smc_wreg; 771 /* protects concurrent PCIE register access */ 772 spinlock_t pcie_idx_lock; 773 amdgpu_rreg_t pcie_rreg; 774 amdgpu_wreg_t pcie_wreg; 775 amdgpu_rreg_t pciep_rreg; 776 amdgpu_wreg_t pciep_wreg; 777 /* protects concurrent UVD register access */ 778 spinlock_t uvd_ctx_idx_lock; 779 amdgpu_rreg_t uvd_ctx_rreg; 780 amdgpu_wreg_t uvd_ctx_wreg; 781 /* protects concurrent DIDT register access */ 782 spinlock_t didt_idx_lock; 783 amdgpu_rreg_t didt_rreg; 784 amdgpu_wreg_t didt_wreg; 785 /* protects concurrent gc_cac register access */ 786 spinlock_t gc_cac_idx_lock; 787 amdgpu_rreg_t gc_cac_rreg; 788 amdgpu_wreg_t gc_cac_wreg; 789 /* protects concurrent se_cac register access */ 790 spinlock_t se_cac_idx_lock; 791 amdgpu_rreg_t se_cac_rreg; 792 amdgpu_wreg_t se_cac_wreg; 793 /* protects concurrent ENDPOINT (audio) register access */ 794 spinlock_t audio_endpt_idx_lock; 795 amdgpu_block_rreg_t audio_endpt_rreg; 796 amdgpu_block_wreg_t audio_endpt_wreg; 797 void __iomem *rio_mem; 798 resource_size_t rio_mem_size; 799 struct amdgpu_doorbell doorbell; 800 801 /* clock/pll info */ 802 struct amdgpu_clock clock; 803 804 /* MC */ 805 struct amdgpu_gmc gmc; 806 struct amdgpu_gart gart; 807 dma_addr_t dummy_page_addr; 808 struct amdgpu_vm_manager vm_manager; 809 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 810 811 /* memory management */ 812 struct amdgpu_mman mman; 813 struct amdgpu_vram_scratch vram_scratch; 814 struct amdgpu_wb wb; 815 atomic64_t num_bytes_moved; 816 atomic64_t num_evictions; 817 atomic64_t num_vram_cpu_page_faults; 818 atomic_t gpu_reset_counter; 819 atomic_t vram_lost_counter; 820 821 /* data for buffer migration throttling */ 822 struct { 823 spinlock_t lock; 824 s64 last_update_us; 825 s64 accum_us; /* accumulated microseconds */ 826 s64 accum_us_vis; /* for visible VRAM */ 827 u32 log2_max_MBps; 828 } mm_stats; 829 830 /* display */ 831 bool enable_virtual_display; 832 struct amdgpu_mode_info mode_info; 833 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 834 struct work_struct hotplug_work; 835 struct amdgpu_irq_src crtc_irq; 836 struct amdgpu_irq_src vupdate_irq; 837 struct amdgpu_irq_src pageflip_irq; 838 struct amdgpu_irq_src hpd_irq; 839 840 /* rings */ 841 u64 fence_context; 842 unsigned num_rings; 843 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 844 bool ib_pool_ready; 845 struct amdgpu_sa_manager ring_tmp_bo; 846 847 /* interrupts */ 848 struct amdgpu_irq irq; 849 850 /* powerplay */ 851 struct amd_powerplay powerplay; 852 bool pp_force_state_enabled; 853 854 /* smu */ 855 struct smu_context smu; 856 857 /* dpm */ 858 struct amdgpu_pm pm; 859 u32 cg_flags; 860 u32 pg_flags; 861 862 /* gfx */ 863 struct amdgpu_gfx gfx; 864 865 /* sdma */ 866 struct amdgpu_sdma sdma; 867 868 /* uvd */ 869 struct amdgpu_uvd uvd; 870 871 /* vce */ 872 struct amdgpu_vce vce; 873 874 /* vcn */ 875 struct amdgpu_vcn vcn; 876 877 /* firmwares */ 878 struct amdgpu_firmware firmware; 879 880 /* PSP */ 881 struct psp_context psp; 882 883 /* GDS */ 884 struct amdgpu_gds gds; 885 886 /* KFD */ 887 struct amdgpu_kfd_dev kfd; 888 889 /* display related functionality */ 890 struct amdgpu_display_manager dm; 891 892 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 893 int num_ip_blocks; 894 struct mutex mn_lock; 895 DECLARE_HASHTABLE(mn_hash, 7); 896 897 /* tracking pinned memory */ 898 atomic64_t vram_pin_size; 899 atomic64_t visible_pin_size; 900 atomic64_t gart_pin_size; 901 902 /* soc15 register offset based on ip, instance and segment */ 903 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 904 905 const struct amdgpu_nbio_funcs *nbio_funcs; 906 const struct amdgpu_df_funcs *df_funcs; 907 908 /* delayed work_func for deferring clockgating during resume */ 909 struct delayed_work late_init_work; 910 911 struct amdgpu_virt virt; 912 /* firmware VRAM reservation */ 913 struct amdgpu_fw_vram_usage fw_vram_usage; 914 915 /* link all shadow bo */ 916 struct list_head shadow_list; 917 struct mutex shadow_list_lock; 918 /* keep an lru list of rings by HW IP */ 919 struct list_head ring_lru_list; 920 spinlock_t ring_lru_list_lock; 921 922 /* record hw reset is performed */ 923 bool has_hw_reset; 924 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 925 926 /* s3/s4 mask */ 927 bool in_suspend; 928 929 /* record last mm index being written through WREG32*/ 930 unsigned long last_mm_index; 931 bool in_gpu_reset; 932 struct mutex lock_reset; 933 struct amdgpu_doorbell_index doorbell_index; 934 935 int asic_reset_res; 936 struct work_struct xgmi_reset_work; 937 938 bool in_baco_reset; 939 }; 940 941 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 942 { 943 return container_of(bdev, struct amdgpu_device, mman.bdev); 944 } 945 946 int amdgpu_device_init(struct amdgpu_device *adev, 947 struct drm_device *ddev, 948 struct pci_dev *pdev, 949 uint32_t flags); 950 void amdgpu_device_fini(struct amdgpu_device *adev); 951 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 952 953 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 954 uint32_t acc_flags); 955 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 956 uint32_t acc_flags); 957 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 958 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 959 960 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 961 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 962 963 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 964 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 965 966 int emu_soc_asic_init(struct amdgpu_device *adev); 967 968 /* 969 * Registers read & write functions. 970 */ 971 972 #define AMDGPU_REGS_IDX (1<<0) 973 #define AMDGPU_REGS_NO_KIQ (1<<1) 974 975 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 976 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 977 978 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 979 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 980 981 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 982 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 983 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 984 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 985 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 986 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 987 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 988 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 989 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 990 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 991 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 992 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 993 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 994 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 995 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 996 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 997 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 998 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 999 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1000 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1001 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1002 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1003 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1004 #define WREG32_P(reg, val, mask) \ 1005 do { \ 1006 uint32_t tmp_ = RREG32(reg); \ 1007 tmp_ &= (mask); \ 1008 tmp_ |= ((val) & ~(mask)); \ 1009 WREG32(reg, tmp_); \ 1010 } while (0) 1011 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1012 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1013 #define WREG32_PLL_P(reg, val, mask) \ 1014 do { \ 1015 uint32_t tmp_ = RREG32_PLL(reg); \ 1016 tmp_ &= (mask); \ 1017 tmp_ |= ((val) & ~(mask)); \ 1018 WREG32_PLL(reg, tmp_); \ 1019 } while (0) 1020 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1021 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1022 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1023 1024 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1025 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1026 1027 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1028 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1029 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1030 1031 #define REG_GET_FIELD(value, reg, field) \ 1032 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1033 1034 #define WREG32_FIELD(reg, field, val) \ 1035 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1036 1037 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1038 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1039 1040 /* 1041 * BIOS helpers. 1042 */ 1043 #define RBIOS8(i) (adev->bios[i]) 1044 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1045 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1046 1047 /* 1048 * ASICs macro. 1049 */ 1050 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1051 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1052 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1053 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1054 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1055 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1056 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1057 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1058 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1059 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1060 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1061 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1062 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1063 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1064 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1065 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1066 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1067 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1068 1069 /* Common functions */ 1070 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1071 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1072 struct amdgpu_job* job); 1073 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1074 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1075 1076 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1077 u64 num_vis_bytes); 1078 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1079 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1080 const u32 *registers, 1081 const u32 array_size); 1082 1083 bool amdgpu_device_is_px(struct drm_device *dev); 1084 /* atpx handler */ 1085 #if defined(CONFIG_VGA_SWITCHEROO) 1086 void amdgpu_register_atpx_handler(void); 1087 void amdgpu_unregister_atpx_handler(void); 1088 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1089 bool amdgpu_is_atpx_hybrid(void); 1090 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1091 bool amdgpu_has_atpx(void); 1092 #else 1093 static inline void amdgpu_register_atpx_handler(void) {} 1094 static inline void amdgpu_unregister_atpx_handler(void) {} 1095 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1096 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1097 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1098 static inline bool amdgpu_has_atpx(void) { return false; } 1099 #endif 1100 1101 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1102 void *amdgpu_atpx_get_dhandle(void); 1103 #else 1104 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1105 #endif 1106 1107 /* 1108 * KMS 1109 */ 1110 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1111 extern const int amdgpu_max_kms_ioctl; 1112 1113 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1114 void amdgpu_driver_unload_kms(struct drm_device *dev); 1115 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1116 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1117 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1118 struct drm_file *file_priv); 1119 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1120 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon); 1121 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon); 1122 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1123 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1124 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1125 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1126 unsigned long arg); 1127 1128 /* 1129 * functions used by amdgpu_encoder.c 1130 */ 1131 struct amdgpu_afmt_acr { 1132 u32 clock; 1133 1134 int n_32khz; 1135 int cts_32khz; 1136 1137 int n_44_1khz; 1138 int cts_44_1khz; 1139 1140 int n_48khz; 1141 int cts_48khz; 1142 1143 }; 1144 1145 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1146 1147 /* amdgpu_acpi.c */ 1148 #if defined(CONFIG_ACPI) 1149 int amdgpu_acpi_init(struct amdgpu_device *adev); 1150 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1151 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1152 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1153 u8 perf_req, bool advertise); 1154 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1155 1156 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1157 struct amdgpu_dm_backlight_caps *caps); 1158 #else 1159 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1160 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1161 #endif 1162 1163 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1164 uint64_t addr, struct amdgpu_bo **bo, 1165 struct amdgpu_bo_va_mapping **mapping); 1166 1167 #if defined(CONFIG_DRM_AMD_DC) 1168 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1169 #else 1170 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1171 #endif 1172 1173 #include "amdgpu_object.h" 1174 #endif 1175