1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __AMDGPU_H__ 29 #define __AMDGPU_H__ 30 31 #include <linux/atomic.h> 32 #include <linux/wait.h> 33 #include <linux/list.h> 34 #include <linux/kref.h> 35 #include <linux/interval_tree.h> 36 #include <linux/hashtable.h> 37 #include <linux/fence.h> 38 39 #include <ttm/ttm_bo_api.h> 40 #include <ttm/ttm_bo_driver.h> 41 #include <ttm/ttm_placement.h> 42 #include <ttm/ttm_module.h> 43 #include <ttm/ttm_execbuf_util.h> 44 45 #include <drm/drmP.h> 46 #include <drm/drm_gem.h> 47 #include <drm/amdgpu_drm.h> 48 49 #include "amd_shared.h" 50 #include "amdgpu_mode.h" 51 #include "amdgpu_ih.h" 52 #include "amdgpu_irq.h" 53 #include "amdgpu_ucode.h" 54 #include "amdgpu_gds.h" 55 56 #include "gpu_scheduler.h" 57 58 /* 59 * Modules parameters. 60 */ 61 extern int amdgpu_modeset; 62 extern int amdgpu_vram_limit; 63 extern int amdgpu_gart_size; 64 extern int amdgpu_benchmarking; 65 extern int amdgpu_testing; 66 extern int amdgpu_audio; 67 extern int amdgpu_disp_priority; 68 extern int amdgpu_hw_i2c; 69 extern int amdgpu_pcie_gen2; 70 extern int amdgpu_msi; 71 extern int amdgpu_lockup_timeout; 72 extern int amdgpu_dpm; 73 extern int amdgpu_smc_load_fw; 74 extern int amdgpu_aspm; 75 extern int amdgpu_runtime_pm; 76 extern int amdgpu_hard_reset; 77 extern unsigned amdgpu_ip_block_mask; 78 extern int amdgpu_bapm; 79 extern int amdgpu_deep_color; 80 extern int amdgpu_vm_size; 81 extern int amdgpu_vm_block_size; 82 extern int amdgpu_enable_scheduler; 83 extern int amdgpu_sched_jobs; 84 extern int amdgpu_sched_hw_submission; 85 extern int amdgpu_enable_semaphores; 86 87 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 88 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 89 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 90 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 91 #define AMDGPU_IB_POOL_SIZE 16 92 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 93 #define AMDGPUFB_CONN_LIMIT 4 94 #define AMDGPU_BIOS_NUM_SCRATCH 8 95 96 /* max number of rings */ 97 #define AMDGPU_MAX_RINGS 16 98 #define AMDGPU_MAX_GFX_RINGS 1 99 #define AMDGPU_MAX_COMPUTE_RINGS 8 100 #define AMDGPU_MAX_VCE_RINGS 2 101 102 /* max number of IP instances */ 103 #define AMDGPU_MAX_SDMA_INSTANCES 2 104 105 /* number of hw syncs before falling back on blocking */ 106 #define AMDGPU_NUM_SYNCS 4 107 108 /* hardcode that limit for now */ 109 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 110 111 /* hard reset data */ 112 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 113 114 /* reset flags */ 115 #define AMDGPU_RESET_GFX (1 << 0) 116 #define AMDGPU_RESET_COMPUTE (1 << 1) 117 #define AMDGPU_RESET_DMA (1 << 2) 118 #define AMDGPU_RESET_CP (1 << 3) 119 #define AMDGPU_RESET_GRBM (1 << 4) 120 #define AMDGPU_RESET_DMA1 (1 << 5) 121 #define AMDGPU_RESET_RLC (1 << 6) 122 #define AMDGPU_RESET_SEM (1 << 7) 123 #define AMDGPU_RESET_IH (1 << 8) 124 #define AMDGPU_RESET_VMC (1 << 9) 125 #define AMDGPU_RESET_MC (1 << 10) 126 #define AMDGPU_RESET_DISPLAY (1 << 11) 127 #define AMDGPU_RESET_UVD (1 << 12) 128 #define AMDGPU_RESET_VCE (1 << 13) 129 #define AMDGPU_RESET_VCE1 (1 << 14) 130 131 /* CG block flags */ 132 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 133 #define AMDGPU_CG_BLOCK_MC (1 << 1) 134 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 135 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 136 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 137 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 138 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 139 140 /* CG flags */ 141 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 142 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 143 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 144 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 145 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 146 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 147 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 148 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 149 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 150 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 151 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 152 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 153 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 154 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 155 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 156 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 157 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 158 159 /* PG flags */ 160 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 161 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 162 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 163 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 164 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 165 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 166 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 167 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 168 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 169 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 170 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 171 172 /* GFX current status */ 173 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 174 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 175 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 176 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 177 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 178 179 /* max cursor sizes (in pixels) */ 180 #define CIK_CURSOR_WIDTH 128 181 #define CIK_CURSOR_HEIGHT 128 182 183 struct amdgpu_device; 184 struct amdgpu_fence; 185 struct amdgpu_ib; 186 struct amdgpu_vm; 187 struct amdgpu_ring; 188 struct amdgpu_semaphore; 189 struct amdgpu_cs_parser; 190 struct amdgpu_job; 191 struct amdgpu_irq_src; 192 struct amdgpu_fpriv; 193 194 enum amdgpu_cp_irq { 195 AMDGPU_CP_IRQ_GFX_EOP = 0, 196 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 197 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 198 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 199 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 200 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 204 205 AMDGPU_CP_IRQ_LAST 206 }; 207 208 enum amdgpu_sdma_irq { 209 AMDGPU_SDMA_IRQ_TRAP0 = 0, 210 AMDGPU_SDMA_IRQ_TRAP1, 211 212 AMDGPU_SDMA_IRQ_LAST 213 }; 214 215 enum amdgpu_thermal_irq { 216 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 217 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 218 219 AMDGPU_THERMAL_IRQ_LAST 220 }; 221 222 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 223 enum amd_ip_block_type block_type, 224 enum amd_clockgating_state state); 225 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 226 enum amd_ip_block_type block_type, 227 enum amd_powergating_state state); 228 229 struct amdgpu_ip_block_version { 230 enum amd_ip_block_type type; 231 u32 major; 232 u32 minor; 233 u32 rev; 234 const struct amd_ip_funcs *funcs; 235 }; 236 237 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 238 enum amd_ip_block_type type, 239 u32 major, u32 minor); 240 241 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 242 struct amdgpu_device *adev, 243 enum amd_ip_block_type type); 244 245 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 246 struct amdgpu_buffer_funcs { 247 /* maximum bytes in a single operation */ 248 uint32_t copy_max_bytes; 249 250 /* number of dw to reserve per operation */ 251 unsigned copy_num_dw; 252 253 /* used for buffer migration */ 254 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 255 /* src addr in bytes */ 256 uint64_t src_offset, 257 /* dst addr in bytes */ 258 uint64_t dst_offset, 259 /* number of byte to transfer */ 260 uint32_t byte_count); 261 262 /* maximum bytes in a single operation */ 263 uint32_t fill_max_bytes; 264 265 /* number of dw to reserve per operation */ 266 unsigned fill_num_dw; 267 268 /* used for buffer clearing */ 269 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 270 /* value to write to memory */ 271 uint32_t src_data, 272 /* dst addr in bytes */ 273 uint64_t dst_offset, 274 /* number of byte to fill */ 275 uint32_t byte_count); 276 }; 277 278 /* provided by hw blocks that can write ptes, e.g., sdma */ 279 struct amdgpu_vm_pte_funcs { 280 /* copy pte entries from GART */ 281 void (*copy_pte)(struct amdgpu_ib *ib, 282 uint64_t pe, uint64_t src, 283 unsigned count); 284 /* write pte one entry at a time with addr mapping */ 285 void (*write_pte)(struct amdgpu_ib *ib, 286 uint64_t pe, 287 uint64_t addr, unsigned count, 288 uint32_t incr, uint32_t flags); 289 /* for linear pte/pde updates without addr mapping */ 290 void (*set_pte_pde)(struct amdgpu_ib *ib, 291 uint64_t pe, 292 uint64_t addr, unsigned count, 293 uint32_t incr, uint32_t flags); 294 /* pad the indirect buffer to the necessary number of dw */ 295 void (*pad_ib)(struct amdgpu_ib *ib); 296 }; 297 298 /* provided by the gmc block */ 299 struct amdgpu_gart_funcs { 300 /* flush the vm tlb via mmio */ 301 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 302 uint32_t vmid); 303 /* write pte/pde updates using the cpu */ 304 int (*set_pte_pde)(struct amdgpu_device *adev, 305 void *cpu_pt_addr, /* cpu addr of page table */ 306 uint32_t gpu_page_idx, /* pte/pde to update */ 307 uint64_t addr, /* addr to write into pte/pde */ 308 uint32_t flags); /* access flags */ 309 }; 310 311 /* provided by the ih block */ 312 struct amdgpu_ih_funcs { 313 /* ring read/write ptr handling, called from interrupt context */ 314 u32 (*get_wptr)(struct amdgpu_device *adev); 315 void (*decode_iv)(struct amdgpu_device *adev, 316 struct amdgpu_iv_entry *entry); 317 void (*set_rptr)(struct amdgpu_device *adev); 318 }; 319 320 /* provided by hw blocks that expose a ring buffer for commands */ 321 struct amdgpu_ring_funcs { 322 /* ring read/write ptr handling */ 323 u32 (*get_rptr)(struct amdgpu_ring *ring); 324 u32 (*get_wptr)(struct amdgpu_ring *ring); 325 void (*set_wptr)(struct amdgpu_ring *ring); 326 /* validating and patching of IBs */ 327 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 328 /* command emit functions */ 329 void (*emit_ib)(struct amdgpu_ring *ring, 330 struct amdgpu_ib *ib); 331 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 332 uint64_t seq, unsigned flags); 333 bool (*emit_semaphore)(struct amdgpu_ring *ring, 334 struct amdgpu_semaphore *semaphore, 335 bool emit_wait); 336 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 337 uint64_t pd_addr); 338 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 339 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 340 uint32_t gds_base, uint32_t gds_size, 341 uint32_t gws_base, uint32_t gws_size, 342 uint32_t oa_base, uint32_t oa_size); 343 /* testing functions */ 344 int (*test_ring)(struct amdgpu_ring *ring); 345 int (*test_ib)(struct amdgpu_ring *ring); 346 bool (*is_lockup)(struct amdgpu_ring *ring); 347 /* insert NOP packets */ 348 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 349 }; 350 351 /* 352 * BIOS. 353 */ 354 bool amdgpu_get_bios(struct amdgpu_device *adev); 355 bool amdgpu_read_bios(struct amdgpu_device *adev); 356 357 /* 358 * Dummy page 359 */ 360 struct amdgpu_dummy_page { 361 struct page *page; 362 dma_addr_t addr; 363 }; 364 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 365 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 366 367 368 /* 369 * Clocks 370 */ 371 372 #define AMDGPU_MAX_PPLL 3 373 374 struct amdgpu_clock { 375 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 376 struct amdgpu_pll spll; 377 struct amdgpu_pll mpll; 378 /* 10 Khz units */ 379 uint32_t default_mclk; 380 uint32_t default_sclk; 381 uint32_t default_dispclk; 382 uint32_t current_dispclk; 383 uint32_t dp_extclk; 384 uint32_t max_pixel_clock; 385 }; 386 387 /* 388 * Fences. 389 */ 390 struct amdgpu_fence_driver { 391 struct amdgpu_ring *ring; 392 uint64_t gpu_addr; 393 volatile uint32_t *cpu_addr; 394 /* sync_seq is protected by ring emission lock */ 395 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 396 atomic64_t last_seq; 397 bool initialized; 398 struct amdgpu_irq_src *irq_src; 399 unsigned irq_type; 400 struct delayed_work lockup_work; 401 wait_queue_head_t fence_queue; 402 }; 403 404 /* some special values for the owner field */ 405 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 406 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 407 #define AMDGPU_FENCE_OWNER_MOVE ((void*)2ul) 408 409 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 410 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 411 412 struct amdgpu_fence { 413 struct fence base; 414 415 /* RB, DMA, etc. */ 416 struct amdgpu_ring *ring; 417 uint64_t seq; 418 419 /* filp or special value for fence creator */ 420 void *owner; 421 422 wait_queue_t fence_wake; 423 }; 424 425 struct amdgpu_user_fence { 426 /* write-back bo */ 427 struct amdgpu_bo *bo; 428 /* write-back address offset to bo start */ 429 uint32_t offset; 430 }; 431 432 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 433 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 434 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 435 436 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 437 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 438 struct amdgpu_irq_src *irq_src, 439 unsigned irq_type); 440 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 441 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 442 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 443 struct amdgpu_fence **fence); 444 void amdgpu_fence_process(struct amdgpu_ring *ring); 445 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 446 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 447 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 448 449 signed long amdgpu_fence_wait_any(struct amdgpu_device *adev, 450 struct fence **array, 451 uint32_t count, 452 bool intr, 453 signed long t); 454 struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence); 455 void amdgpu_fence_unref(struct amdgpu_fence **fence); 456 457 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 458 struct amdgpu_ring *ring); 459 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 460 struct amdgpu_ring *ring); 461 462 static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a, 463 struct amdgpu_fence *b) 464 { 465 if (!a) { 466 return b; 467 } 468 469 if (!b) { 470 return a; 471 } 472 473 BUG_ON(a->ring != b->ring); 474 475 if (a->seq > b->seq) { 476 return a; 477 } else { 478 return b; 479 } 480 } 481 482 static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a, 483 struct amdgpu_fence *b) 484 { 485 if (!a) { 486 return false; 487 } 488 489 if (!b) { 490 return true; 491 } 492 493 BUG_ON(a->ring != b->ring); 494 495 return a->seq < b->seq; 496 } 497 498 int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user, 499 void *owner, struct amdgpu_fence **fence); 500 501 /* 502 * TTM. 503 */ 504 struct amdgpu_mman { 505 struct ttm_bo_global_ref bo_global_ref; 506 struct drm_global_reference mem_global_ref; 507 struct ttm_bo_device bdev; 508 bool mem_global_referenced; 509 bool initialized; 510 511 #if defined(CONFIG_DEBUG_FS) 512 struct dentry *vram; 513 struct dentry *gtt; 514 #endif 515 516 /* buffer handling */ 517 const struct amdgpu_buffer_funcs *buffer_funcs; 518 struct amdgpu_ring *buffer_funcs_ring; 519 }; 520 521 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 522 uint64_t src_offset, 523 uint64_t dst_offset, 524 uint32_t byte_count, 525 struct reservation_object *resv, 526 struct fence **fence); 527 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 528 529 struct amdgpu_bo_list_entry { 530 struct amdgpu_bo *robj; 531 struct ttm_validate_buffer tv; 532 struct amdgpu_bo_va *bo_va; 533 unsigned prefered_domains; 534 unsigned allowed_domains; 535 uint32_t priority; 536 }; 537 538 struct amdgpu_bo_va_mapping { 539 struct list_head list; 540 struct interval_tree_node it; 541 uint64_t offset; 542 uint32_t flags; 543 }; 544 545 /* bo virtual addresses in a specific vm */ 546 struct amdgpu_bo_va { 547 /* protected by bo being reserved */ 548 struct list_head bo_list; 549 struct fence *last_pt_update; 550 unsigned ref_count; 551 552 /* protected by vm mutex and spinlock */ 553 struct list_head vm_status; 554 555 /* mappings for this bo_va */ 556 struct list_head invalids; 557 struct list_head valids; 558 559 /* constant after initialization */ 560 struct amdgpu_vm *vm; 561 struct amdgpu_bo *bo; 562 }; 563 564 #define AMDGPU_GEM_DOMAIN_MAX 0x3 565 566 struct amdgpu_bo { 567 /* Protected by gem.mutex */ 568 struct list_head list; 569 /* Protected by tbo.reserved */ 570 u32 initial_domain; 571 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 572 struct ttm_placement placement; 573 struct ttm_buffer_object tbo; 574 struct ttm_bo_kmap_obj kmap; 575 u64 flags; 576 unsigned pin_count; 577 void *kptr; 578 u64 tiling_flags; 579 u64 metadata_flags; 580 void *metadata; 581 u32 metadata_size; 582 /* list of all virtual address to which this bo 583 * is associated to 584 */ 585 struct list_head va; 586 /* Constant after initialization */ 587 struct amdgpu_device *adev; 588 struct drm_gem_object gem_base; 589 590 struct ttm_bo_kmap_obj dma_buf_vmap; 591 pid_t pid; 592 struct amdgpu_mn *mn; 593 struct list_head mn_list; 594 }; 595 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 596 597 void amdgpu_gem_object_free(struct drm_gem_object *obj); 598 int amdgpu_gem_object_open(struct drm_gem_object *obj, 599 struct drm_file *file_priv); 600 void amdgpu_gem_object_close(struct drm_gem_object *obj, 601 struct drm_file *file_priv); 602 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 603 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 604 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 605 struct dma_buf_attachment *attach, 606 struct sg_table *sg); 607 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 608 struct drm_gem_object *gobj, 609 int flags); 610 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 611 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 612 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 613 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 614 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 615 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 616 617 /* sub-allocation manager, it has to be protected by another lock. 618 * By conception this is an helper for other part of the driver 619 * like the indirect buffer or semaphore, which both have their 620 * locking. 621 * 622 * Principe is simple, we keep a list of sub allocation in offset 623 * order (first entry has offset == 0, last entry has the highest 624 * offset). 625 * 626 * When allocating new object we first check if there is room at 627 * the end total_size - (last_object_offset + last_object_size) >= 628 * alloc_size. If so we allocate new object there. 629 * 630 * When there is not enough room at the end, we start waiting for 631 * each sub object until we reach object_offset+object_size >= 632 * alloc_size, this object then become the sub object we return. 633 * 634 * Alignment can't be bigger than page size. 635 * 636 * Hole are not considered for allocation to keep things simple. 637 * Assumption is that there won't be hole (all object on same 638 * alignment). 639 */ 640 struct amdgpu_sa_manager { 641 wait_queue_head_t wq; 642 struct amdgpu_bo *bo; 643 struct list_head *hole; 644 struct list_head flist[AMDGPU_MAX_RINGS]; 645 struct list_head olist; 646 unsigned size; 647 uint64_t gpu_addr; 648 void *cpu_ptr; 649 uint32_t domain; 650 uint32_t align; 651 }; 652 653 struct amdgpu_sa_bo; 654 655 /* sub-allocation buffer */ 656 struct amdgpu_sa_bo { 657 struct list_head olist; 658 struct list_head flist; 659 struct amdgpu_sa_manager *manager; 660 unsigned soffset; 661 unsigned eoffset; 662 struct fence *fence; 663 }; 664 665 /* 666 * GEM objects. 667 */ 668 struct amdgpu_gem { 669 struct mutex mutex; 670 struct list_head objects; 671 }; 672 673 int amdgpu_gem_init(struct amdgpu_device *adev); 674 void amdgpu_gem_fini(struct amdgpu_device *adev); 675 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 676 int alignment, u32 initial_domain, 677 u64 flags, bool kernel, 678 struct drm_gem_object **obj); 679 680 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 681 struct drm_device *dev, 682 struct drm_mode_create_dumb *args); 683 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 684 struct drm_device *dev, 685 uint32_t handle, uint64_t *offset_p); 686 687 /* 688 * Semaphores. 689 */ 690 struct amdgpu_semaphore { 691 struct amdgpu_sa_bo *sa_bo; 692 signed waiters; 693 uint64_t gpu_addr; 694 }; 695 696 int amdgpu_semaphore_create(struct amdgpu_device *adev, 697 struct amdgpu_semaphore **semaphore); 698 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 699 struct amdgpu_semaphore *semaphore); 700 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 701 struct amdgpu_semaphore *semaphore); 702 void amdgpu_semaphore_free(struct amdgpu_device *adev, 703 struct amdgpu_semaphore **semaphore, 704 struct fence *fence); 705 706 /* 707 * Synchronization 708 */ 709 struct amdgpu_sync { 710 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 711 struct amdgpu_fence *sync_to[AMDGPU_MAX_RINGS]; 712 DECLARE_HASHTABLE(fences, 4); 713 struct fence *last_vm_update; 714 }; 715 716 void amdgpu_sync_create(struct amdgpu_sync *sync); 717 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 718 struct fence *f); 719 int amdgpu_sync_resv(struct amdgpu_device *adev, 720 struct amdgpu_sync *sync, 721 struct reservation_object *resv, 722 void *owner); 723 int amdgpu_sync_rings(struct amdgpu_sync *sync, 724 struct amdgpu_ring *ring); 725 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 726 int amdgpu_sync_wait(struct amdgpu_sync *sync); 727 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 728 struct fence *fence); 729 730 /* 731 * GART structures, functions & helpers 732 */ 733 struct amdgpu_mc; 734 735 #define AMDGPU_GPU_PAGE_SIZE 4096 736 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 737 #define AMDGPU_GPU_PAGE_SHIFT 12 738 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 739 740 struct amdgpu_gart { 741 dma_addr_t table_addr; 742 struct amdgpu_bo *robj; 743 void *ptr; 744 unsigned num_gpu_pages; 745 unsigned num_cpu_pages; 746 unsigned table_size; 747 struct page **pages; 748 dma_addr_t *pages_addr; 749 bool ready; 750 const struct amdgpu_gart_funcs *gart_funcs; 751 }; 752 753 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 754 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 755 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 756 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 757 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 758 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 759 int amdgpu_gart_init(struct amdgpu_device *adev); 760 void amdgpu_gart_fini(struct amdgpu_device *adev); 761 void amdgpu_gart_unbind(struct amdgpu_device *adev, unsigned offset, 762 int pages); 763 int amdgpu_gart_bind(struct amdgpu_device *adev, unsigned offset, 764 int pages, struct page **pagelist, 765 dma_addr_t *dma_addr, uint32_t flags); 766 767 /* 768 * GPU MC structures, functions & helpers 769 */ 770 struct amdgpu_mc { 771 resource_size_t aper_size; 772 resource_size_t aper_base; 773 resource_size_t agp_base; 774 /* for some chips with <= 32MB we need to lie 775 * about vram size near mc fb location */ 776 u64 mc_vram_size; 777 u64 visible_vram_size; 778 u64 gtt_size; 779 u64 gtt_start; 780 u64 gtt_end; 781 u64 vram_start; 782 u64 vram_end; 783 unsigned vram_width; 784 u64 real_vram_size; 785 int vram_mtrr; 786 u64 gtt_base_align; 787 u64 mc_mask; 788 const struct firmware *fw; /* MC firmware */ 789 uint32_t fw_version; 790 struct amdgpu_irq_src vm_fault; 791 uint32_t vram_type; 792 }; 793 794 /* 795 * GPU doorbell structures, functions & helpers 796 */ 797 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 798 { 799 AMDGPU_DOORBELL_KIQ = 0x000, 800 AMDGPU_DOORBELL_HIQ = 0x001, 801 AMDGPU_DOORBELL_DIQ = 0x002, 802 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 803 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 804 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 805 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 806 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 807 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 808 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 809 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 810 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 811 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 812 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 813 AMDGPU_DOORBELL_IH = 0x1E8, 814 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 815 AMDGPU_DOORBELL_INVALID = 0xFFFF 816 } AMDGPU_DOORBELL_ASSIGNMENT; 817 818 struct amdgpu_doorbell { 819 /* doorbell mmio */ 820 resource_size_t base; 821 resource_size_t size; 822 u32 __iomem *ptr; 823 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 824 }; 825 826 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 827 phys_addr_t *aperture_base, 828 size_t *aperture_size, 829 size_t *start_offset); 830 831 /* 832 * IRQS. 833 */ 834 835 struct amdgpu_flip_work { 836 struct work_struct flip_work; 837 struct work_struct unpin_work; 838 struct amdgpu_device *adev; 839 int crtc_id; 840 uint64_t base; 841 struct drm_pending_vblank_event *event; 842 struct amdgpu_bo *old_rbo; 843 struct fence *excl; 844 unsigned shared_count; 845 struct fence **shared; 846 }; 847 848 849 /* 850 * CP & rings. 851 */ 852 853 struct amdgpu_ib { 854 struct amdgpu_sa_bo *sa_bo; 855 uint32_t length_dw; 856 uint64_t gpu_addr; 857 uint32_t *ptr; 858 struct amdgpu_ring *ring; 859 struct amdgpu_fence *fence; 860 struct amdgpu_user_fence *user; 861 struct amdgpu_vm *vm; 862 struct amdgpu_ctx *ctx; 863 struct amdgpu_sync sync; 864 uint32_t gds_base, gds_size; 865 uint32_t gws_base, gws_size; 866 uint32_t oa_base, oa_size; 867 uint32_t flags; 868 /* resulting sequence number */ 869 uint64_t sequence; 870 }; 871 872 enum amdgpu_ring_type { 873 AMDGPU_RING_TYPE_GFX, 874 AMDGPU_RING_TYPE_COMPUTE, 875 AMDGPU_RING_TYPE_SDMA, 876 AMDGPU_RING_TYPE_UVD, 877 AMDGPU_RING_TYPE_VCE 878 }; 879 880 extern struct amd_sched_backend_ops amdgpu_sched_ops; 881 882 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 883 struct amdgpu_ring *ring, 884 struct amdgpu_ib *ibs, 885 unsigned num_ibs, 886 int (*free_job)(struct amdgpu_job *), 887 void *owner, 888 struct fence **fence); 889 890 struct amdgpu_ring { 891 struct amdgpu_device *adev; 892 const struct amdgpu_ring_funcs *funcs; 893 struct amdgpu_fence_driver fence_drv; 894 struct amd_gpu_scheduler sched; 895 896 spinlock_t fence_lock; 897 struct mutex *ring_lock; 898 struct amdgpu_bo *ring_obj; 899 volatile uint32_t *ring; 900 unsigned rptr_offs; 901 u64 next_rptr_gpu_addr; 902 volatile u32 *next_rptr_cpu_addr; 903 unsigned wptr; 904 unsigned wptr_old; 905 unsigned ring_size; 906 unsigned ring_free_dw; 907 int count_dw; 908 atomic_t last_rptr; 909 atomic64_t last_activity; 910 uint64_t gpu_addr; 911 uint32_t align_mask; 912 uint32_t ptr_mask; 913 bool ready; 914 u32 nop; 915 u32 idx; 916 u64 last_semaphore_signal_addr; 917 u64 last_semaphore_wait_addr; 918 u32 me; 919 u32 pipe; 920 u32 queue; 921 struct amdgpu_bo *mqd_obj; 922 u32 doorbell_index; 923 bool use_doorbell; 924 unsigned wptr_offs; 925 unsigned next_rptr_offs; 926 unsigned fence_offs; 927 struct amdgpu_ctx *current_ctx; 928 enum amdgpu_ring_type type; 929 char name[16]; 930 bool is_pte_ring; 931 }; 932 933 /* 934 * VM 935 */ 936 937 /* maximum number of VMIDs */ 938 #define AMDGPU_NUM_VM 16 939 940 /* number of entries in page table */ 941 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 942 943 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 944 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 945 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 946 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 947 948 #define AMDGPU_PTE_VALID (1 << 0) 949 #define AMDGPU_PTE_SYSTEM (1 << 1) 950 #define AMDGPU_PTE_SNOOPED (1 << 2) 951 952 /* VI only */ 953 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 954 955 #define AMDGPU_PTE_READABLE (1 << 5) 956 #define AMDGPU_PTE_WRITEABLE (1 << 6) 957 958 /* PTE (Page Table Entry) fragment field for different page sizes */ 959 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 960 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 961 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 962 963 struct amdgpu_vm_pt { 964 struct amdgpu_bo *bo; 965 uint64_t addr; 966 }; 967 968 struct amdgpu_vm_id { 969 unsigned id; 970 uint64_t pd_gpu_addr; 971 /* last flushed PD/PT update */ 972 struct fence *flushed_updates; 973 /* last use of vmid */ 974 struct amdgpu_fence *last_id_use; 975 }; 976 977 struct amdgpu_vm { 978 struct mutex mutex; 979 980 struct rb_root va; 981 982 /* protecting invalidated */ 983 spinlock_t status_lock; 984 985 /* BOs moved, but not yet updated in the PT */ 986 struct list_head invalidated; 987 988 /* BOs cleared in the PT because of a move */ 989 struct list_head cleared; 990 991 /* BO mappings freed, but not yet updated in the PT */ 992 struct list_head freed; 993 994 /* contains the page directory */ 995 struct amdgpu_bo *page_directory; 996 unsigned max_pde_used; 997 struct fence *page_directory_fence; 998 999 /* array of page tables, one for each page directory entry */ 1000 struct amdgpu_vm_pt *page_tables; 1001 1002 /* for id and flush management per ring */ 1003 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 1004 }; 1005 1006 struct amdgpu_vm_manager { 1007 struct amdgpu_fence *active[AMDGPU_NUM_VM]; 1008 uint32_t max_pfn; 1009 /* number of VMIDs */ 1010 unsigned nvm; 1011 /* vram base address for page table entry */ 1012 u64 vram_base_offset; 1013 /* is vm enabled? */ 1014 bool enabled; 1015 /* for hw to save the PD addr on suspend/resume */ 1016 uint32_t saved_table_addr[AMDGPU_NUM_VM]; 1017 /* vm pte handling */ 1018 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 1019 struct amdgpu_ring *vm_pte_funcs_ring; 1020 }; 1021 1022 /* 1023 * context related structures 1024 */ 1025 1026 #define AMDGPU_CTX_MAX_CS_PENDING 16 1027 1028 struct amdgpu_ctx_ring { 1029 uint64_t sequence; 1030 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1031 struct amd_sched_entity entity; 1032 }; 1033 1034 struct amdgpu_ctx { 1035 struct kref refcount; 1036 struct amdgpu_device *adev; 1037 unsigned reset_counter; 1038 spinlock_t ring_lock; 1039 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1040 }; 1041 1042 struct amdgpu_ctx_mgr { 1043 struct amdgpu_device *adev; 1044 struct mutex lock; 1045 /* protected by lock */ 1046 struct idr ctx_handles; 1047 }; 1048 1049 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1050 struct amdgpu_ctx *ctx); 1051 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1052 1053 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1054 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1055 1056 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1057 struct fence *fence); 1058 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1059 struct amdgpu_ring *ring, uint64_t seq); 1060 1061 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1062 struct drm_file *filp); 1063 1064 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1065 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1066 1067 /* 1068 * file private structure 1069 */ 1070 1071 struct amdgpu_fpriv { 1072 struct amdgpu_vm vm; 1073 struct mutex bo_list_lock; 1074 struct idr bo_list_handles; 1075 struct amdgpu_ctx_mgr ctx_mgr; 1076 }; 1077 1078 /* 1079 * residency list 1080 */ 1081 1082 struct amdgpu_bo_list { 1083 struct mutex lock; 1084 struct amdgpu_bo *gds_obj; 1085 struct amdgpu_bo *gws_obj; 1086 struct amdgpu_bo *oa_obj; 1087 bool has_userptr; 1088 unsigned num_entries; 1089 struct amdgpu_bo_list_entry *array; 1090 }; 1091 1092 struct amdgpu_bo_list * 1093 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1094 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1095 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1096 1097 /* 1098 * GFX stuff 1099 */ 1100 #include "clearstate_defs.h" 1101 1102 struct amdgpu_rlc { 1103 /* for power gating */ 1104 struct amdgpu_bo *save_restore_obj; 1105 uint64_t save_restore_gpu_addr; 1106 volatile uint32_t *sr_ptr; 1107 const u32 *reg_list; 1108 u32 reg_list_size; 1109 /* for clear state */ 1110 struct amdgpu_bo *clear_state_obj; 1111 uint64_t clear_state_gpu_addr; 1112 volatile uint32_t *cs_ptr; 1113 const struct cs_section_def *cs_data; 1114 u32 clear_state_size; 1115 /* for cp tables */ 1116 struct amdgpu_bo *cp_table_obj; 1117 uint64_t cp_table_gpu_addr; 1118 volatile uint32_t *cp_table_ptr; 1119 u32 cp_table_size; 1120 }; 1121 1122 struct amdgpu_mec { 1123 struct amdgpu_bo *hpd_eop_obj; 1124 u64 hpd_eop_gpu_addr; 1125 u32 num_pipe; 1126 u32 num_mec; 1127 u32 num_queue; 1128 }; 1129 1130 /* 1131 * GPU scratch registers structures, functions & helpers 1132 */ 1133 struct amdgpu_scratch { 1134 unsigned num_reg; 1135 uint32_t reg_base; 1136 bool free[32]; 1137 uint32_t reg[32]; 1138 }; 1139 1140 /* 1141 * GFX configurations 1142 */ 1143 struct amdgpu_gca_config { 1144 unsigned max_shader_engines; 1145 unsigned max_tile_pipes; 1146 unsigned max_cu_per_sh; 1147 unsigned max_sh_per_se; 1148 unsigned max_backends_per_se; 1149 unsigned max_texture_channel_caches; 1150 unsigned max_gprs; 1151 unsigned max_gs_threads; 1152 unsigned max_hw_contexts; 1153 unsigned sc_prim_fifo_size_frontend; 1154 unsigned sc_prim_fifo_size_backend; 1155 unsigned sc_hiz_tile_fifo_size; 1156 unsigned sc_earlyz_tile_fifo_size; 1157 1158 unsigned num_tile_pipes; 1159 unsigned backend_enable_mask; 1160 unsigned mem_max_burst_length_bytes; 1161 unsigned mem_row_size_in_kb; 1162 unsigned shader_engine_tile_size; 1163 unsigned num_gpus; 1164 unsigned multi_gpu_tile_size; 1165 unsigned mc_arb_ramcfg; 1166 unsigned gb_addr_config; 1167 1168 uint32_t tile_mode_array[32]; 1169 uint32_t macrotile_mode_array[16]; 1170 }; 1171 1172 struct amdgpu_gfx { 1173 struct mutex gpu_clock_mutex; 1174 struct amdgpu_gca_config config; 1175 struct amdgpu_rlc rlc; 1176 struct amdgpu_mec mec; 1177 struct amdgpu_scratch scratch; 1178 const struct firmware *me_fw; /* ME firmware */ 1179 uint32_t me_fw_version; 1180 const struct firmware *pfp_fw; /* PFP firmware */ 1181 uint32_t pfp_fw_version; 1182 const struct firmware *ce_fw; /* CE firmware */ 1183 uint32_t ce_fw_version; 1184 const struct firmware *rlc_fw; /* RLC firmware */ 1185 uint32_t rlc_fw_version; 1186 const struct firmware *mec_fw; /* MEC firmware */ 1187 uint32_t mec_fw_version; 1188 const struct firmware *mec2_fw; /* MEC2 firmware */ 1189 uint32_t mec2_fw_version; 1190 uint32_t me_feature_version; 1191 uint32_t ce_feature_version; 1192 uint32_t pfp_feature_version; 1193 uint32_t rlc_feature_version; 1194 uint32_t mec_feature_version; 1195 uint32_t mec2_feature_version; 1196 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1197 unsigned num_gfx_rings; 1198 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1199 unsigned num_compute_rings; 1200 struct amdgpu_irq_src eop_irq; 1201 struct amdgpu_irq_src priv_reg_irq; 1202 struct amdgpu_irq_src priv_inst_irq; 1203 /* gfx status */ 1204 uint32_t gfx_current_status; 1205 /* ce ram size*/ 1206 unsigned ce_ram_size; 1207 }; 1208 1209 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1210 unsigned size, struct amdgpu_ib *ib); 1211 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1212 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1213 struct amdgpu_ib *ib, void *owner); 1214 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1215 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1216 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1217 /* Ring access between begin & end cannot sleep */ 1218 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1219 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1220 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1221 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1222 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1223 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1224 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1225 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1226 void amdgpu_ring_lockup_update(struct amdgpu_ring *ring); 1227 bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring); 1228 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1229 uint32_t **data); 1230 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1231 unsigned size, uint32_t *data); 1232 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1233 unsigned ring_size, u32 nop, u32 align_mask, 1234 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1235 enum amdgpu_ring_type ring_type); 1236 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1237 1238 /* 1239 * CS. 1240 */ 1241 struct amdgpu_cs_chunk { 1242 uint32_t chunk_id; 1243 uint32_t length_dw; 1244 uint32_t *kdata; 1245 void __user *user_ptr; 1246 }; 1247 1248 struct amdgpu_cs_parser { 1249 struct amdgpu_device *adev; 1250 struct drm_file *filp; 1251 struct amdgpu_ctx *ctx; 1252 struct amdgpu_bo_list *bo_list; 1253 /* chunks */ 1254 unsigned nchunks; 1255 struct amdgpu_cs_chunk *chunks; 1256 /* relocations */ 1257 struct amdgpu_bo_list_entry *vm_bos; 1258 struct list_head validated; 1259 1260 struct amdgpu_ib *ibs; 1261 uint32_t num_ibs; 1262 1263 struct ww_acquire_ctx ticket; 1264 1265 /* user fence */ 1266 struct amdgpu_user_fence uf; 1267 }; 1268 1269 struct amdgpu_job { 1270 struct amd_sched_job base; 1271 struct amdgpu_device *adev; 1272 struct amdgpu_ib *ibs; 1273 uint32_t num_ibs; 1274 struct mutex job_lock; 1275 struct amdgpu_user_fence uf; 1276 int (*free_job)(struct amdgpu_job *job); 1277 }; 1278 #define to_amdgpu_job(sched_job) \ 1279 container_of((sched_job), struct amdgpu_job, base) 1280 1281 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1282 { 1283 return p->ibs[ib_idx].ptr[idx]; 1284 } 1285 1286 /* 1287 * Writeback 1288 */ 1289 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1290 1291 struct amdgpu_wb { 1292 struct amdgpu_bo *wb_obj; 1293 volatile uint32_t *wb; 1294 uint64_t gpu_addr; 1295 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1296 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1297 }; 1298 1299 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1300 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1301 1302 /** 1303 * struct amdgpu_pm - power management datas 1304 * It keeps track of various data needed to take powermanagement decision. 1305 */ 1306 1307 enum amdgpu_pm_state_type { 1308 /* not used for dpm */ 1309 POWER_STATE_TYPE_DEFAULT, 1310 POWER_STATE_TYPE_POWERSAVE, 1311 /* user selectable states */ 1312 POWER_STATE_TYPE_BATTERY, 1313 POWER_STATE_TYPE_BALANCED, 1314 POWER_STATE_TYPE_PERFORMANCE, 1315 /* internal states */ 1316 POWER_STATE_TYPE_INTERNAL_UVD, 1317 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1318 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1319 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1320 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1321 POWER_STATE_TYPE_INTERNAL_BOOT, 1322 POWER_STATE_TYPE_INTERNAL_THERMAL, 1323 POWER_STATE_TYPE_INTERNAL_ACPI, 1324 POWER_STATE_TYPE_INTERNAL_ULV, 1325 POWER_STATE_TYPE_INTERNAL_3DPERF, 1326 }; 1327 1328 enum amdgpu_int_thermal_type { 1329 THERMAL_TYPE_NONE, 1330 THERMAL_TYPE_EXTERNAL, 1331 THERMAL_TYPE_EXTERNAL_GPIO, 1332 THERMAL_TYPE_RV6XX, 1333 THERMAL_TYPE_RV770, 1334 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1335 THERMAL_TYPE_EVERGREEN, 1336 THERMAL_TYPE_SUMO, 1337 THERMAL_TYPE_NI, 1338 THERMAL_TYPE_SI, 1339 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1340 THERMAL_TYPE_CI, 1341 THERMAL_TYPE_KV, 1342 }; 1343 1344 enum amdgpu_dpm_auto_throttle_src { 1345 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1346 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1347 }; 1348 1349 enum amdgpu_dpm_event_src { 1350 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1351 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1352 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1353 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1354 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1355 }; 1356 1357 #define AMDGPU_MAX_VCE_LEVELS 6 1358 1359 enum amdgpu_vce_level { 1360 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1361 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1362 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1363 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1364 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1365 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1366 }; 1367 1368 struct amdgpu_ps { 1369 u32 caps; /* vbios flags */ 1370 u32 class; /* vbios flags */ 1371 u32 class2; /* vbios flags */ 1372 /* UVD clocks */ 1373 u32 vclk; 1374 u32 dclk; 1375 /* VCE clocks */ 1376 u32 evclk; 1377 u32 ecclk; 1378 bool vce_active; 1379 enum amdgpu_vce_level vce_level; 1380 /* asic priv */ 1381 void *ps_priv; 1382 }; 1383 1384 struct amdgpu_dpm_thermal { 1385 /* thermal interrupt work */ 1386 struct work_struct work; 1387 /* low temperature threshold */ 1388 int min_temp; 1389 /* high temperature threshold */ 1390 int max_temp; 1391 /* was last interrupt low to high or high to low */ 1392 bool high_to_low; 1393 /* interrupt source */ 1394 struct amdgpu_irq_src irq; 1395 }; 1396 1397 enum amdgpu_clk_action 1398 { 1399 AMDGPU_SCLK_UP = 1, 1400 AMDGPU_SCLK_DOWN 1401 }; 1402 1403 struct amdgpu_blacklist_clocks 1404 { 1405 u32 sclk; 1406 u32 mclk; 1407 enum amdgpu_clk_action action; 1408 }; 1409 1410 struct amdgpu_clock_and_voltage_limits { 1411 u32 sclk; 1412 u32 mclk; 1413 u16 vddc; 1414 u16 vddci; 1415 }; 1416 1417 struct amdgpu_clock_array { 1418 u32 count; 1419 u32 *values; 1420 }; 1421 1422 struct amdgpu_clock_voltage_dependency_entry { 1423 u32 clk; 1424 u16 v; 1425 }; 1426 1427 struct amdgpu_clock_voltage_dependency_table { 1428 u32 count; 1429 struct amdgpu_clock_voltage_dependency_entry *entries; 1430 }; 1431 1432 union amdgpu_cac_leakage_entry { 1433 struct { 1434 u16 vddc; 1435 u32 leakage; 1436 }; 1437 struct { 1438 u16 vddc1; 1439 u16 vddc2; 1440 u16 vddc3; 1441 }; 1442 }; 1443 1444 struct amdgpu_cac_leakage_table { 1445 u32 count; 1446 union amdgpu_cac_leakage_entry *entries; 1447 }; 1448 1449 struct amdgpu_phase_shedding_limits_entry { 1450 u16 voltage; 1451 u32 sclk; 1452 u32 mclk; 1453 }; 1454 1455 struct amdgpu_phase_shedding_limits_table { 1456 u32 count; 1457 struct amdgpu_phase_shedding_limits_entry *entries; 1458 }; 1459 1460 struct amdgpu_uvd_clock_voltage_dependency_entry { 1461 u32 vclk; 1462 u32 dclk; 1463 u16 v; 1464 }; 1465 1466 struct amdgpu_uvd_clock_voltage_dependency_table { 1467 u8 count; 1468 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1469 }; 1470 1471 struct amdgpu_vce_clock_voltage_dependency_entry { 1472 u32 ecclk; 1473 u32 evclk; 1474 u16 v; 1475 }; 1476 1477 struct amdgpu_vce_clock_voltage_dependency_table { 1478 u8 count; 1479 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1480 }; 1481 1482 struct amdgpu_ppm_table { 1483 u8 ppm_design; 1484 u16 cpu_core_number; 1485 u32 platform_tdp; 1486 u32 small_ac_platform_tdp; 1487 u32 platform_tdc; 1488 u32 small_ac_platform_tdc; 1489 u32 apu_tdp; 1490 u32 dgpu_tdp; 1491 u32 dgpu_ulv_power; 1492 u32 tj_max; 1493 }; 1494 1495 struct amdgpu_cac_tdp_table { 1496 u16 tdp; 1497 u16 configurable_tdp; 1498 u16 tdc; 1499 u16 battery_power_limit; 1500 u16 small_power_limit; 1501 u16 low_cac_leakage; 1502 u16 high_cac_leakage; 1503 u16 maximum_power_delivery_limit; 1504 }; 1505 1506 struct amdgpu_dpm_dynamic_state { 1507 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1508 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1509 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1510 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1511 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1512 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1513 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1514 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1515 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1516 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1517 struct amdgpu_clock_array valid_sclk_values; 1518 struct amdgpu_clock_array valid_mclk_values; 1519 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1520 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1521 u32 mclk_sclk_ratio; 1522 u32 sclk_mclk_delta; 1523 u16 vddc_vddci_delta; 1524 u16 min_vddc_for_pcie_gen2; 1525 struct amdgpu_cac_leakage_table cac_leakage_table; 1526 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1527 struct amdgpu_ppm_table *ppm_table; 1528 struct amdgpu_cac_tdp_table *cac_tdp_table; 1529 }; 1530 1531 struct amdgpu_dpm_fan { 1532 u16 t_min; 1533 u16 t_med; 1534 u16 t_high; 1535 u16 pwm_min; 1536 u16 pwm_med; 1537 u16 pwm_high; 1538 u8 t_hyst; 1539 u32 cycle_delay; 1540 u16 t_max; 1541 u8 control_mode; 1542 u16 default_max_fan_pwm; 1543 u16 default_fan_output_sensitivity; 1544 u16 fan_output_sensitivity; 1545 bool ucode_fan_control; 1546 }; 1547 1548 enum amdgpu_pcie_gen { 1549 AMDGPU_PCIE_GEN1 = 0, 1550 AMDGPU_PCIE_GEN2 = 1, 1551 AMDGPU_PCIE_GEN3 = 2, 1552 AMDGPU_PCIE_GEN_INVALID = 0xffff 1553 }; 1554 1555 enum amdgpu_dpm_forced_level { 1556 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1557 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1558 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1559 }; 1560 1561 struct amdgpu_vce_state { 1562 /* vce clocks */ 1563 u32 evclk; 1564 u32 ecclk; 1565 /* gpu clocks */ 1566 u32 sclk; 1567 u32 mclk; 1568 u8 clk_idx; 1569 u8 pstate; 1570 }; 1571 1572 struct amdgpu_dpm_funcs { 1573 int (*get_temperature)(struct amdgpu_device *adev); 1574 int (*pre_set_power_state)(struct amdgpu_device *adev); 1575 int (*set_power_state)(struct amdgpu_device *adev); 1576 void (*post_set_power_state)(struct amdgpu_device *adev); 1577 void (*display_configuration_changed)(struct amdgpu_device *adev); 1578 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1579 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1580 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1581 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1582 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1583 bool (*vblank_too_short)(struct amdgpu_device *adev); 1584 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1585 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1586 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1587 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1588 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1589 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1590 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1591 }; 1592 1593 struct amdgpu_dpm { 1594 struct amdgpu_ps *ps; 1595 /* number of valid power states */ 1596 int num_ps; 1597 /* current power state that is active */ 1598 struct amdgpu_ps *current_ps; 1599 /* requested power state */ 1600 struct amdgpu_ps *requested_ps; 1601 /* boot up power state */ 1602 struct amdgpu_ps *boot_ps; 1603 /* default uvd power state */ 1604 struct amdgpu_ps *uvd_ps; 1605 /* vce requirements */ 1606 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1607 enum amdgpu_vce_level vce_level; 1608 enum amdgpu_pm_state_type state; 1609 enum amdgpu_pm_state_type user_state; 1610 u32 platform_caps; 1611 u32 voltage_response_time; 1612 u32 backbias_response_time; 1613 void *priv; 1614 u32 new_active_crtcs; 1615 int new_active_crtc_count; 1616 u32 current_active_crtcs; 1617 int current_active_crtc_count; 1618 struct amdgpu_dpm_dynamic_state dyn_state; 1619 struct amdgpu_dpm_fan fan; 1620 u32 tdp_limit; 1621 u32 near_tdp_limit; 1622 u32 near_tdp_limit_adjusted; 1623 u32 sq_ramping_threshold; 1624 u32 cac_leakage; 1625 u16 tdp_od_limit; 1626 u32 tdp_adjustment; 1627 u16 load_line_slope; 1628 bool power_control; 1629 bool ac_power; 1630 /* special states active */ 1631 bool thermal_active; 1632 bool uvd_active; 1633 bool vce_active; 1634 /* thermal handling */ 1635 struct amdgpu_dpm_thermal thermal; 1636 /* forced levels */ 1637 enum amdgpu_dpm_forced_level forced_level; 1638 }; 1639 1640 struct amdgpu_pm { 1641 struct mutex mutex; 1642 u32 current_sclk; 1643 u32 current_mclk; 1644 u32 default_sclk; 1645 u32 default_mclk; 1646 struct amdgpu_i2c_chan *i2c_bus; 1647 /* internal thermal controller on rv6xx+ */ 1648 enum amdgpu_int_thermal_type int_thermal_type; 1649 struct device *int_hwmon_dev; 1650 /* fan control parameters */ 1651 bool no_fan; 1652 u8 fan_pulses_per_revolution; 1653 u8 fan_min_rpm; 1654 u8 fan_max_rpm; 1655 /* dpm */ 1656 bool dpm_enabled; 1657 bool sysfs_initialized; 1658 struct amdgpu_dpm dpm; 1659 const struct firmware *fw; /* SMC firmware */ 1660 uint32_t fw_version; 1661 const struct amdgpu_dpm_funcs *funcs; 1662 }; 1663 1664 /* 1665 * UVD 1666 */ 1667 #define AMDGPU_MAX_UVD_HANDLES 10 1668 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1669 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1670 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1671 1672 struct amdgpu_uvd { 1673 struct amdgpu_bo *vcpu_bo; 1674 void *cpu_addr; 1675 uint64_t gpu_addr; 1676 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1677 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1678 struct delayed_work idle_work; 1679 const struct firmware *fw; /* UVD firmware */ 1680 struct amdgpu_ring ring; 1681 struct amdgpu_irq_src irq; 1682 bool address_64_bit; 1683 }; 1684 1685 /* 1686 * VCE 1687 */ 1688 #define AMDGPU_MAX_VCE_HANDLES 16 1689 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1690 1691 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1692 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1693 1694 struct amdgpu_vce { 1695 struct amdgpu_bo *vcpu_bo; 1696 uint64_t gpu_addr; 1697 unsigned fw_version; 1698 unsigned fb_version; 1699 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1700 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1701 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1702 struct delayed_work idle_work; 1703 const struct firmware *fw; /* VCE firmware */ 1704 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1705 struct amdgpu_irq_src irq; 1706 unsigned harvest_config; 1707 }; 1708 1709 /* 1710 * SDMA 1711 */ 1712 struct amdgpu_sdma { 1713 /* SDMA firmware */ 1714 const struct firmware *fw; 1715 uint32_t fw_version; 1716 uint32_t feature_version; 1717 1718 struct amdgpu_ring ring; 1719 bool burst_nop; 1720 }; 1721 1722 /* 1723 * Firmware 1724 */ 1725 struct amdgpu_firmware { 1726 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1727 bool smu_load; 1728 struct amdgpu_bo *fw_buf; 1729 unsigned int fw_size; 1730 }; 1731 1732 /* 1733 * Benchmarking 1734 */ 1735 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1736 1737 1738 /* 1739 * Testing 1740 */ 1741 void amdgpu_test_moves(struct amdgpu_device *adev); 1742 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1743 struct amdgpu_ring *cpA, 1744 struct amdgpu_ring *cpB); 1745 void amdgpu_test_syncing(struct amdgpu_device *adev); 1746 1747 /* 1748 * MMU Notifier 1749 */ 1750 #if defined(CONFIG_MMU_NOTIFIER) 1751 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1752 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1753 #else 1754 static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1755 { 1756 return -ENODEV; 1757 } 1758 static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1759 #endif 1760 1761 /* 1762 * Debugfs 1763 */ 1764 struct amdgpu_debugfs { 1765 struct drm_info_list *files; 1766 unsigned num_files; 1767 }; 1768 1769 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1770 struct drm_info_list *files, 1771 unsigned nfiles); 1772 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1773 1774 #if defined(CONFIG_DEBUG_FS) 1775 int amdgpu_debugfs_init(struct drm_minor *minor); 1776 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1777 #endif 1778 1779 /* 1780 * amdgpu smumgr functions 1781 */ 1782 struct amdgpu_smumgr_funcs { 1783 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1784 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1785 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1786 }; 1787 1788 /* 1789 * amdgpu smumgr 1790 */ 1791 struct amdgpu_smumgr { 1792 struct amdgpu_bo *toc_buf; 1793 struct amdgpu_bo *smu_buf; 1794 /* asic priv smu data */ 1795 void *priv; 1796 spinlock_t smu_lock; 1797 /* smumgr functions */ 1798 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1799 /* ucode loading complete flag */ 1800 uint32_t fw_flags; 1801 }; 1802 1803 /* 1804 * ASIC specific register table accessible by UMD 1805 */ 1806 struct amdgpu_allowed_register_entry { 1807 uint32_t reg_offset; 1808 bool untouched; 1809 bool grbm_indexed; 1810 }; 1811 1812 struct amdgpu_cu_info { 1813 uint32_t number; /* total active CU number */ 1814 uint32_t ao_cu_mask; 1815 uint32_t bitmap[4][4]; 1816 }; 1817 1818 1819 /* 1820 * ASIC specific functions. 1821 */ 1822 struct amdgpu_asic_funcs { 1823 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1824 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1825 u32 sh_num, u32 reg_offset, u32 *value); 1826 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1827 int (*reset)(struct amdgpu_device *adev); 1828 /* wait for mc_idle */ 1829 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1830 /* get the reference clock */ 1831 u32 (*get_xclk)(struct amdgpu_device *adev); 1832 /* get the gpu clock counter */ 1833 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1834 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1835 /* MM block clocks */ 1836 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1837 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1838 }; 1839 1840 /* 1841 * IOCTL. 1842 */ 1843 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1844 struct drm_file *filp); 1845 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1846 struct drm_file *filp); 1847 1848 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1849 struct drm_file *filp); 1850 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1851 struct drm_file *filp); 1852 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1853 struct drm_file *filp); 1854 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1857 struct drm_file *filp); 1858 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1859 struct drm_file *filp); 1860 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1861 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1862 1863 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1864 struct drm_file *filp); 1865 1866 /* VRAM scratch page for HDP bug, default vram page */ 1867 struct amdgpu_vram_scratch { 1868 struct amdgpu_bo *robj; 1869 volatile uint32_t *ptr; 1870 u64 gpu_addr; 1871 }; 1872 1873 /* 1874 * ACPI 1875 */ 1876 struct amdgpu_atif_notification_cfg { 1877 bool enabled; 1878 int command_code; 1879 }; 1880 1881 struct amdgpu_atif_notifications { 1882 bool display_switch; 1883 bool expansion_mode_change; 1884 bool thermal_state; 1885 bool forced_power_state; 1886 bool system_power_state; 1887 bool display_conf_change; 1888 bool px_gfx_switch; 1889 bool brightness_change; 1890 bool dgpu_display_event; 1891 }; 1892 1893 struct amdgpu_atif_functions { 1894 bool system_params; 1895 bool sbios_requests; 1896 bool select_active_disp; 1897 bool lid_state; 1898 bool get_tv_standard; 1899 bool set_tv_standard; 1900 bool get_panel_expansion_mode; 1901 bool set_panel_expansion_mode; 1902 bool temperature_change; 1903 bool graphics_device_types; 1904 }; 1905 1906 struct amdgpu_atif { 1907 struct amdgpu_atif_notifications notifications; 1908 struct amdgpu_atif_functions functions; 1909 struct amdgpu_atif_notification_cfg notification_cfg; 1910 struct amdgpu_encoder *encoder_for_bl; 1911 }; 1912 1913 struct amdgpu_atcs_functions { 1914 bool get_ext_state; 1915 bool pcie_perf_req; 1916 bool pcie_dev_rdy; 1917 bool pcie_bus_width; 1918 }; 1919 1920 struct amdgpu_atcs { 1921 struct amdgpu_atcs_functions functions; 1922 }; 1923 1924 /* 1925 * CGS 1926 */ 1927 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1928 void amdgpu_cgs_destroy_device(void *cgs_device); 1929 1930 1931 /* 1932 * Core structure, functions and helpers. 1933 */ 1934 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1935 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1936 1937 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1938 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1939 1940 struct amdgpu_ip_block_status { 1941 bool valid; 1942 bool sw; 1943 bool hw; 1944 }; 1945 1946 struct amdgpu_device { 1947 struct device *dev; 1948 struct drm_device *ddev; 1949 struct pci_dev *pdev; 1950 struct rw_semaphore exclusive_lock; 1951 1952 /* ASIC */ 1953 enum amd_asic_type asic_type; 1954 uint32_t family; 1955 uint32_t rev_id; 1956 uint32_t external_rev_id; 1957 unsigned long flags; 1958 int usec_timeout; 1959 const struct amdgpu_asic_funcs *asic_funcs; 1960 bool shutdown; 1961 bool suspend; 1962 bool need_dma32; 1963 bool accel_working; 1964 bool needs_reset; 1965 struct work_struct reset_work; 1966 struct notifier_block acpi_nb; 1967 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1968 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1969 unsigned debugfs_count; 1970 #if defined(CONFIG_DEBUG_FS) 1971 struct dentry *debugfs_regs; 1972 #endif 1973 struct amdgpu_atif atif; 1974 struct amdgpu_atcs atcs; 1975 struct mutex srbm_mutex; 1976 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1977 struct mutex grbm_idx_mutex; 1978 struct dev_pm_domain vga_pm_domain; 1979 bool have_disp_power_ref; 1980 1981 /* BIOS */ 1982 uint8_t *bios; 1983 bool is_atom_bios; 1984 uint16_t bios_header_start; 1985 struct amdgpu_bo *stollen_vga_memory; 1986 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1987 1988 /* Register/doorbell mmio */ 1989 resource_size_t rmmio_base; 1990 resource_size_t rmmio_size; 1991 void __iomem *rmmio; 1992 /* protects concurrent MM_INDEX/DATA based register access */ 1993 spinlock_t mmio_idx_lock; 1994 /* protects concurrent SMC based register access */ 1995 spinlock_t smc_idx_lock; 1996 amdgpu_rreg_t smc_rreg; 1997 amdgpu_wreg_t smc_wreg; 1998 /* protects concurrent PCIE register access */ 1999 spinlock_t pcie_idx_lock; 2000 amdgpu_rreg_t pcie_rreg; 2001 amdgpu_wreg_t pcie_wreg; 2002 /* protects concurrent UVD register access */ 2003 spinlock_t uvd_ctx_idx_lock; 2004 amdgpu_rreg_t uvd_ctx_rreg; 2005 amdgpu_wreg_t uvd_ctx_wreg; 2006 /* protects concurrent DIDT register access */ 2007 spinlock_t didt_idx_lock; 2008 amdgpu_rreg_t didt_rreg; 2009 amdgpu_wreg_t didt_wreg; 2010 /* protects concurrent ENDPOINT (audio) register access */ 2011 spinlock_t audio_endpt_idx_lock; 2012 amdgpu_block_rreg_t audio_endpt_rreg; 2013 amdgpu_block_wreg_t audio_endpt_wreg; 2014 void __iomem *rio_mem; 2015 resource_size_t rio_mem_size; 2016 struct amdgpu_doorbell doorbell; 2017 2018 /* clock/pll info */ 2019 struct amdgpu_clock clock; 2020 2021 /* MC */ 2022 struct amdgpu_mc mc; 2023 struct amdgpu_gart gart; 2024 struct amdgpu_dummy_page dummy_page; 2025 struct amdgpu_vm_manager vm_manager; 2026 2027 /* memory management */ 2028 struct amdgpu_mman mman; 2029 struct amdgpu_gem gem; 2030 struct amdgpu_vram_scratch vram_scratch; 2031 struct amdgpu_wb wb; 2032 atomic64_t vram_usage; 2033 atomic64_t vram_vis_usage; 2034 atomic64_t gtt_usage; 2035 atomic64_t num_bytes_moved; 2036 atomic_t gpu_reset_counter; 2037 2038 /* display */ 2039 struct amdgpu_mode_info mode_info; 2040 struct work_struct hotplug_work; 2041 struct amdgpu_irq_src crtc_irq; 2042 struct amdgpu_irq_src pageflip_irq; 2043 struct amdgpu_irq_src hpd_irq; 2044 2045 /* rings */ 2046 unsigned fence_context; 2047 struct mutex ring_lock; 2048 unsigned num_rings; 2049 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2050 bool ib_pool_ready; 2051 struct amdgpu_sa_manager ring_tmp_bo; 2052 2053 /* interrupts */ 2054 struct amdgpu_irq irq; 2055 2056 /* dpm */ 2057 struct amdgpu_pm pm; 2058 u32 cg_flags; 2059 u32 pg_flags; 2060 2061 /* amdgpu smumgr */ 2062 struct amdgpu_smumgr smu; 2063 2064 /* gfx */ 2065 struct amdgpu_gfx gfx; 2066 2067 /* sdma */ 2068 struct amdgpu_sdma sdma[AMDGPU_MAX_SDMA_INSTANCES]; 2069 struct amdgpu_irq_src sdma_trap_irq; 2070 struct amdgpu_irq_src sdma_illegal_inst_irq; 2071 2072 /* uvd */ 2073 bool has_uvd; 2074 struct amdgpu_uvd uvd; 2075 2076 /* vce */ 2077 struct amdgpu_vce vce; 2078 2079 /* firmwares */ 2080 struct amdgpu_firmware firmware; 2081 2082 /* GDS */ 2083 struct amdgpu_gds gds; 2084 2085 const struct amdgpu_ip_block_version *ip_blocks; 2086 int num_ip_blocks; 2087 struct amdgpu_ip_block_status *ip_block_status; 2088 struct mutex mn_lock; 2089 DECLARE_HASHTABLE(mn_hash, 7); 2090 2091 /* tracking pinned memory */ 2092 u64 vram_pin_size; 2093 u64 gart_pin_size; 2094 2095 /* amdkfd interface */ 2096 struct kfd_dev *kfd; 2097 2098 /* kernel conext for IB submission */ 2099 struct amdgpu_ctx kernel_ctx; 2100 }; 2101 2102 bool amdgpu_device_is_px(struct drm_device *dev); 2103 int amdgpu_device_init(struct amdgpu_device *adev, 2104 struct drm_device *ddev, 2105 struct pci_dev *pdev, 2106 uint32_t flags); 2107 void amdgpu_device_fini(struct amdgpu_device *adev); 2108 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2109 2110 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2111 bool always_indirect); 2112 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2113 bool always_indirect); 2114 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2115 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2116 2117 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2118 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2119 2120 /* 2121 * Cast helper 2122 */ 2123 extern const struct fence_ops amdgpu_fence_ops; 2124 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2125 { 2126 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2127 2128 if (__f->base.ops == &amdgpu_fence_ops) 2129 return __f; 2130 2131 return NULL; 2132 } 2133 2134 /* 2135 * Registers read & write functions. 2136 */ 2137 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2138 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2139 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2140 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2141 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2142 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2143 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2144 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2145 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2146 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2147 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2148 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2149 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2150 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2151 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2152 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2153 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2154 #define WREG32_P(reg, val, mask) \ 2155 do { \ 2156 uint32_t tmp_ = RREG32(reg); \ 2157 tmp_ &= (mask); \ 2158 tmp_ |= ((val) & ~(mask)); \ 2159 WREG32(reg, tmp_); \ 2160 } while (0) 2161 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2162 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2163 #define WREG32_PLL_P(reg, val, mask) \ 2164 do { \ 2165 uint32_t tmp_ = RREG32_PLL(reg); \ 2166 tmp_ &= (mask); \ 2167 tmp_ |= ((val) & ~(mask)); \ 2168 WREG32_PLL(reg, tmp_); \ 2169 } while (0) 2170 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2171 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2172 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2173 2174 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2175 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2176 2177 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2178 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2179 2180 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2181 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2182 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2183 2184 #define REG_GET_FIELD(value, reg, field) \ 2185 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2186 2187 /* 2188 * BIOS helpers. 2189 */ 2190 #define RBIOS8(i) (adev->bios[i]) 2191 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2192 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2193 2194 /* 2195 * RING helpers. 2196 */ 2197 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2198 { 2199 if (ring->count_dw <= 0) 2200 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2201 ring->ring[ring->wptr++] = v; 2202 ring->wptr &= ring->ptr_mask; 2203 ring->count_dw--; 2204 ring->ring_free_dw--; 2205 } 2206 2207 static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2208 { 2209 struct amdgpu_device *adev = ring->adev; 2210 int i; 2211 2212 for (i = 0; i < AMDGPU_MAX_SDMA_INSTANCES; i++) 2213 if (&adev->sdma[i].ring == ring) 2214 break; 2215 2216 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2217 return &adev->sdma[i]; 2218 else 2219 return NULL; 2220 } 2221 2222 /* 2223 * ASICs macro. 2224 */ 2225 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2226 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2227 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2228 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2229 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2230 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2231 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2232 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2233 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2234 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2235 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2236 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2237 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2238 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2239 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2240 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2241 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2242 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2243 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2244 #define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r)) 2245 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2246 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2247 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2248 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2249 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2250 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2251 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2252 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2253 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2254 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2255 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2256 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2257 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2258 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2259 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2260 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2261 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2262 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2263 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2264 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2265 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2266 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2267 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2268 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2269 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2270 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2271 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2272 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2273 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2274 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2275 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2276 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2277 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2278 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2279 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2280 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2281 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2282 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2283 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2284 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2285 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2286 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2287 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2288 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2289 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2290 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2291 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2292 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2293 2294 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2295 2296 /* Common functions */ 2297 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2298 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2299 bool amdgpu_card_posted(struct amdgpu_device *adev); 2300 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2301 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2302 struct amdgpu_cs_parser *amdgpu_cs_parser_create(struct amdgpu_device *adev, 2303 struct drm_file *filp, 2304 struct amdgpu_ctx *ctx, 2305 struct amdgpu_ib *ibs, 2306 uint32_t num_ibs); 2307 2308 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2309 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2310 u32 ip_instance, u32 ring, 2311 struct amdgpu_ring **out_ring); 2312 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2313 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2314 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2315 uint32_t flags); 2316 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2317 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2318 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2319 struct ttm_mem_reg *mem); 2320 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2321 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2322 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2323 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2324 const u32 *registers, 2325 const u32 array_size); 2326 2327 bool amdgpu_device_is_px(struct drm_device *dev); 2328 /* atpx handler */ 2329 #if defined(CONFIG_VGA_SWITCHEROO) 2330 void amdgpu_register_atpx_handler(void); 2331 void amdgpu_unregister_atpx_handler(void); 2332 #else 2333 static inline void amdgpu_register_atpx_handler(void) {} 2334 static inline void amdgpu_unregister_atpx_handler(void) {} 2335 #endif 2336 2337 /* 2338 * KMS 2339 */ 2340 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2341 extern int amdgpu_max_kms_ioctl; 2342 2343 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2344 int amdgpu_driver_unload_kms(struct drm_device *dev); 2345 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2346 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2347 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2348 struct drm_file *file_priv); 2349 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2350 struct drm_file *file_priv); 2351 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2352 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2353 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc); 2354 int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc); 2355 void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc); 2356 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, 2357 int *max_error, 2358 struct timeval *vblank_time, 2359 unsigned flags); 2360 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2361 unsigned long arg); 2362 2363 /* 2364 * vm 2365 */ 2366 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2367 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 2368 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 2369 struct amdgpu_vm *vm, 2370 struct list_head *head); 2371 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 2372 struct amdgpu_sync *sync); 2373 void amdgpu_vm_flush(struct amdgpu_ring *ring, 2374 struct amdgpu_vm *vm, 2375 struct fence *updates); 2376 void amdgpu_vm_fence(struct amdgpu_device *adev, 2377 struct amdgpu_vm *vm, 2378 struct amdgpu_fence *fence); 2379 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 2380 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 2381 struct amdgpu_vm *vm); 2382 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 2383 struct amdgpu_vm *vm); 2384 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, 2385 struct amdgpu_vm *vm, struct amdgpu_sync *sync); 2386 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 2387 struct amdgpu_bo_va *bo_va, 2388 struct ttm_mem_reg *mem); 2389 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 2390 struct amdgpu_bo *bo); 2391 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 2392 struct amdgpu_bo *bo); 2393 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 2394 struct amdgpu_vm *vm, 2395 struct amdgpu_bo *bo); 2396 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 2397 struct amdgpu_bo_va *bo_va, 2398 uint64_t addr, uint64_t offset, 2399 uint64_t size, uint32_t flags); 2400 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 2401 struct amdgpu_bo_va *bo_va, 2402 uint64_t addr); 2403 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 2404 struct amdgpu_bo_va *bo_va); 2405 int amdgpu_vm_free_job(struct amdgpu_job *job); 2406 /* 2407 * functions used by amdgpu_encoder.c 2408 */ 2409 struct amdgpu_afmt_acr { 2410 u32 clock; 2411 2412 int n_32khz; 2413 int cts_32khz; 2414 2415 int n_44_1khz; 2416 int cts_44_1khz; 2417 2418 int n_48khz; 2419 int cts_48khz; 2420 2421 }; 2422 2423 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2424 2425 /* amdgpu_acpi.c */ 2426 #if defined(CONFIG_ACPI) 2427 int amdgpu_acpi_init(struct amdgpu_device *adev); 2428 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2429 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2430 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2431 u8 perf_req, bool advertise); 2432 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2433 #else 2434 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2435 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2436 #endif 2437 2438 struct amdgpu_bo_va_mapping * 2439 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2440 uint64_t addr, struct amdgpu_bo **bo); 2441 2442 #include "amdgpu_object.h" 2443 2444 #endif 2445